1" Vim syntax file 2" Language: VHDL 3" Maintainer: Czo <[email protected]> 4" Credits: Stephan Hegel <[email protected]> 5" $Id: vhdl.vim,v 1.1 2004/06/13 15:34:56 vimboss Exp $ 6 7" VHSIC Hardware Description Language 8" Very High Scale Integrated Circuit 9 10" For version 5.x: Clear all syntax items 11" For version 6.x: Quit when a syntax file was already loaded 12if version < 600 13 syntax clear 14elseif exists("b:current_syntax") 15 finish 16endif 17 18" This is not VHDL. I use the C-Preprocessor cpp to generate different binaries 19" from one VHDL source file. Unfortunately there is no preprocessor for VHDL 20" available. If you don't like this, please remove the following lines. 21syn match cDefine "^#ifdef[ ]\+[A-Za-z_]\+" 22syn match cDefine "^#endif" 23 24" case is not significant 25syn case ignore 26 27" VHDL keywords 28syn keyword vhdlStatement access after alias all assert 29syn keyword vhdlStatement architecture array attribute 30syn keyword vhdlStatement begin block body buffer bus 31syn keyword vhdlStatement case component configuration constant 32syn keyword vhdlStatement disconnect downto 33syn keyword vhdlStatement elsif end entity exit 34syn keyword vhdlStatement file for function 35syn keyword vhdlStatement generate generic group guarded 36syn keyword vhdlStatement impure in inertial inout is 37syn keyword vhdlStatement label library linkage literal loop 38syn keyword vhdlStatement map 39syn keyword vhdlStatement new next null 40syn keyword vhdlStatement of on open others out 41syn keyword vhdlStatement package port postponed procedure process pure 42syn keyword vhdlStatement range record register reject report return 43syn keyword vhdlStatement select severity signal shared 44syn keyword vhdlStatement subtype 45syn keyword vhdlStatement then to transport type 46syn keyword vhdlStatement unaffected units until use 47syn keyword vhdlStatement variable wait when while with 48syn keyword vhdlStatement note warning error failure 49 50" Special match for "if" and "else" since "else if" shouldn't be highlighted. 51" The right keyword is "elsif" 52syn match vhdlStatement "\<\(if\|else\)\>" 53syn match vhdlNone "\<else\s\+if\>$" 54syn match vhdlNone "\<else\s\+if\>\s" 55 56" Predifined VHDL types 57syn keyword vhdlType bit bit_vector 58syn keyword vhdlType character boolean integer real time 59syn keyword vhdlType string severity_level 60" Predifined standard ieee VHDL types 61syn keyword vhdlType positive natural signed unsigned 62syn keyword vhdlType line text 63syn keyword vhdlType std_logic std_logic_vector 64syn keyword vhdlType std_ulogic std_ulogic_vector 65" Predefined non standard VHDL types for Mentor Graphics Sys1076/QuickHDL 66syn keyword vhdlType qsim_state qsim_state_vector 67syn keyword vhdlType qsim_12state qsim_12state_vector 68syn keyword vhdlType qsim_strength 69" Predefined non standard VHDL types for Alliance VLSI CAD 70syn keyword vhdlType mux_bit mux_vector reg_bit reg_vector wor_bit wor_vector 71 72" array attributes 73syn match vhdlAttribute "\'high" 74syn match vhdlAttribute "\'left" 75syn match vhdlAttribute "\'length" 76syn match vhdlAttribute "\'low" 77syn match vhdlAttribute "\'range" 78syn match vhdlAttribute "\'reverse_range" 79syn match vhdlAttribute "\'right" 80syn match vhdlAttribute "\'ascending" 81" block attributes 82syn match vhdlAttribute "\'behaviour" 83syn match vhdlAttribute "\'structure" 84syn match vhdlAttribute "\'simple_name" 85syn match vhdlAttribute "\'instance_name" 86syn match vhdlAttribute "\'path_name" 87syn match vhdlAttribute "\'foreign" 88" signal attribute 89syn match vhdlAttribute "\'active" 90syn match vhdlAttribute "\'delayed" 91syn match vhdlAttribute "\'event" 92syn match vhdlAttribute "\'last_active" 93syn match vhdlAttribute "\'last_event" 94syn match vhdlAttribute "\'last_value" 95syn match vhdlAttribute "\'quiet" 96syn match vhdlAttribute "\'stable" 97syn match vhdlAttribute "\'transaction" 98syn match vhdlAttribute "\'driving" 99syn match vhdlAttribute "\'driving_value" 100" type attributes 101syn match vhdlAttribute "\'base" 102syn match vhdlAttribute "\'high" 103syn match vhdlAttribute "\'left" 104syn match vhdlAttribute "\'leftof" 105syn match vhdlAttribute "\'low" 106syn match vhdlAttribute "\'pos" 107syn match vhdlAttribute "\'pred" 108syn match vhdlAttribute "\'rightof" 109syn match vhdlAttribute "\'succ" 110syn match vhdlAttribute "\'val" 111syn match vhdlAttribute "\'image" 112syn match vhdlAttribute "\'value" 113 114syn keyword vhdlBoolean true false 115 116" for this vector values case is significant 117syn case match 118" Values for standard VHDL types 119syn match vhdlVector "\'[0L1HXWZU\-\?]\'" 120" Values for non standard VHDL types qsim_12state for Mentor Graphics Sys1076/QuickHDL 121syn keyword vhdlVector S0S S1S SXS S0R S1R SXR S0Z S1Z SXZ S0I S1I SXI 122syn case ignore 123 124syn match vhdlVector "B\"[01_]\+\"" 125syn match vhdlVector "O\"[0-7_]\+\"" 126syn match vhdlVector "X\"[0-9a-f_]\+\"" 127syn match vhdlCharacter "'.'" 128syn region vhdlString start=+"+ end=+"+ 129 130" floating numbers 131syn match vhdlNumber "-\=\<\d\+\.\d\+\(E[+\-]\=\d\+\)\>" 132syn match vhdlNumber "-\=\<\d\+\.\d\+\>" 133syn match vhdlNumber "0*2#[01_]\+\.[01_]\+#\(E[+\-]\=\d\+\)\=" 134syn match vhdlNumber "0*16#[0-9a-f_]\+\.[0-9a-f_]\+#\(E[+\-]\=\d\+\)\=" 135" integer numbers 136syn match vhdlNumber "-\=\<\d\+\(E[+\-]\=\d\+\)\>" 137syn match vhdlNumber "-\=\<\d\+\>" 138syn match vhdlNumber "0*2#[01_]\+#\(E[+\-]\=\d\+\)\=" 139syn match vhdlNumber "0*16#[0-9a-f_]\+#\(E[+\-]\=\d\+\)\=" 140" operators 141syn keyword vhdlOperator and nand or nor xor xnor 142syn keyword vhdlOperator rol ror sla sll sra srl 143syn keyword vhdlOperator mod rem abs not 144syn match vhdlOperator "[&><=:+\-*\/|]" 145syn match vhdlSpecial "[().,;]" 146" time 147syn match vhdlTime "\<\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>" 148syn match vhdlTime "\<\d\+\.\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>" 149 150syn match vhdlComment "--.*$" 151" syn match vhdlGlobal "[\'$#~!%@?\^\[\]{}\\]" 152 153" Define the default highlighting. 154" For version 5.7 and earlier: only when not done already 155" For version 5.8 and later: only when an item doesn't have highlighting yet 156if version >= 508 || !exists("did_vhdl_syntax_inits") 157 if version < 508 158 let did_vhdl_syntax_inits = 1 159 command -nargs=+ HiLink hi link <args> 160 else 161 command -nargs=+ HiLink hi def link <args> 162 endif 163 164 HiLink cDefine PreProc 165 HiLink vhdlSpecial Special 166 HiLink vhdlStatement Statement 167 HiLink vhdlCharacter String 168 HiLink vhdlString String 169 HiLink vhdlVector String 170 HiLink vhdlBoolean String 171 HiLink vhdlComment Comment 172 HiLink vhdlNumber String 173 HiLink vhdlTime String 174 HiLink vhdlType Type 175 HiLink vhdlOperator Type 176 HiLink vhdlGlobal Error 177 HiLink vhdlAttribute Type 178 179 delcommand HiLink 180endif 181 182let b:current_syntax = "vhdl" 183 184" vim: ts=8 185