1" Vim syntax file 2" Language: Verilog-AMS 3" Maintainer: S. Myles Prather <[email protected]> 4" 5" Version 1.1 S. Myles Prather <[email protected]> 6" Moved some keywords to the type category. 7" Added the metrix suffixes to the number matcher. 8" Version 1.2 Prasanna Tamhankar <[email protected]> 9" Minor reserved keyword updates. 10" Last Update: Thursday September 15 15:36:03 CST 2005 11 12" quit when a syntax file was already loaded 13if exists("b:current_syntax") 14 finish 15endif 16 17" Set the local value of the 'iskeyword' option 18setlocal iskeyword=@,48-57,_,192-255 19 20" Annex B.1 'All keywords' 21syn keyword verilogamsStatement above abs absdelay acos acosh ac_stim 22syn keyword verilogamsStatement always analog analysis and asin 23syn keyword verilogamsStatement asinh assign atan atan2 atanh 24syn keyword verilogamsStatement buf bufif0 bufif1 ceil cmos connectmodule 25syn keyword verilogamsStatement connectrules cos cosh cross ddt ddx deassign 26syn keyword verilogamsStatement defparam disable discipline 27syn keyword verilogamsStatement driver_update edge enddiscipline 28syn keyword verilogamsStatement endconnectrules endmodule endfunction endgenerate 29syn keyword verilogamsStatement endnature endparamset endprimitive endspecify 30syn keyword verilogamsStatement endtable endtask event exp final_step 31syn keyword verilogamsStatement flicker_noise floor flow force fork 32syn keyword verilogamsStatement function generate highz0 33syn keyword verilogamsStatement highz1 hypot idt idtmod if ifnone inf initial 34syn keyword verilogamsStatement initial_step inout input join 35syn keyword verilogamsStatement laplace_nd laplace_np laplace_zd laplace_zp 36syn keyword verilogamsStatement large last_crossing limexp ln localparam log 37syn keyword verilogamsStatement macromodule max medium min module nand nature 38syn keyword verilogamsStatement negedge net_resolution nmos noise_table nor not 39syn keyword verilogamsStatement notif0 notif1 or output paramset pmos 40syn keyword verilogamsType parameter real integer electrical input output 41syn keyword verilogamsType inout reg tri tri0 tri1 triand trior trireg 42syn keyword verilogamsType string from exclude aliasparam ground genvar 43syn keyword verilogamsType branch time realtime 44syn keyword verilogamsStatement posedge potential pow primitive pull0 pull1 45syn keyword verilogamsStatement pullup pulldown rcmos release 46syn keyword verilogamsStatement rnmos rpmos rtran rtranif0 rtranif1 47syn keyword verilogamsStatement scalared sin sinh slew small specify specparam 48syn keyword verilogamsStatement sqrt strong0 strong1 supply0 supply1 49syn keyword verilogamsStatement table tan tanh task timer tran tranif0 50syn keyword verilogamsStatement tranif1 transition 51syn keyword verilogamsStatement vectored wait wand weak0 weak1 52syn keyword verilogamsStatement white_noise wire wor wreal xnor xor zi_nd 53syn keyword verilogamsStatement zi_np zi_zd zi_zp 54syn keyword verilogamsRepeat forever repeat while for 55syn keyword verilogamsLabel begin end 56syn keyword verilogamsConditional if else case casex casez default endcase 57syn match verilogamsConstant ":inf"lc=1 58syn match verilogamsConstant "-inf"lc=1 59" Annex B.2 Discipline/nature 60syn keyword verilogamsStatement abstol access continuous ddt_nature discrete 61syn keyword verilogamsStatement domain idt_nature units 62" Annex B.3 Connect Rules 63syn keyword verilogamsStatement connect merged resolveto split 64 65syn match verilogamsOperator "[&|~><!)(*#%@+/=?:;}{,.\^\-\[\]]" 66syn match verilogamsOperator "<+" 67syn match verilogamsStatement "[vV]("me=e-1 68syn match verilogamsStatement "[iI]("me=e-1 69 70syn keyword verilogamsTodo contained TODO 71syn region verilogamsComment start="/\*" end="\*/" contains=verilogamsTodo 72syn match verilogamsComment "//.*" contains=verilogamsTodo 73 74syn match verilogamsGlobal "`celldefine" 75syn match verilogamsGlobal "`default_nettype" 76syn match verilogamsGlobal "`define" 77syn match verilogamsGlobal "`else" 78syn match verilogamsGlobal "`elsif" 79syn match verilogamsGlobal "`endcelldefine" 80syn match verilogamsGlobal "`endif" 81syn match verilogamsGlobal "`ifdef" 82syn match verilogamsGlobal "`ifndef" 83syn match verilogamsGlobal "`include" 84syn match verilogamsGlobal "`line" 85syn match verilogamsGlobal "`nounconnected_drive" 86syn match verilogamsGlobal "`resetall" 87syn match verilogamsGlobal "`timescale" 88syn match verilogamsGlobal "`unconnected_drive" 89syn match verilogamsGlobal "`undef" 90syn match verilogamsSystask "$[a-zA-Z0-9_]\+\>" 91 92syn match verilogamsConstant "\<[A-Z][A-Z0-9_]\+\>" 93 94syn match verilogamsNumber "\(\<\d\+\|\)'[bB]\s*[0-1_xXzZ?]\+\>" 95syn match verilogamsNumber "\(\<\d\+\|\)'[oO]\s*[0-7_xXzZ?]\+\>" 96syn match verilogamsNumber "\(\<\d\+\|\)'[dD]\s*[0-9_xXzZ?]\+\>" 97syn match verilogamsNumber "\(\<\d\+\|\)'[hH]\s*[0-9a-fA-F_xXzZ?]\+\>" 98syn match verilogamsNumber "\<[+-]\=[0-9_]\+\(\.[0-9_]*\|\)\(e[0-9_]*\|\)[TGMKkmunpfa]\=\>" 99 100syn region verilogamsString start=+"+ skip=+\\"+ end=+"+ contains=verilogamsEscape 101syn match verilogamsEscape +\\[nt"\\]+ contained 102syn match verilogamsEscape "\\\o\o\=\o\=" contained 103 104"Modify the following as needed. The trade-off is performance versus 105"functionality. 106syn sync lines=50 107 108" Define the default highlighting. 109" Only when an item doesn't have highlighting yet 110 111" The default highlighting. 112hi def link verilogamsCharacter Character 113hi def link verilogamsConditional Conditional 114hi def link verilogamsRepeat Repeat 115hi def link verilogamsString String 116hi def link verilogamsTodo Todo 117hi def link verilogamsComment Comment 118hi def link verilogamsConstant Constant 119hi def link verilogamsLabel Label 120hi def link verilogamsNumber Number 121hi def link verilogamsOperator Special 122hi def link verilogamsStatement Statement 123hi def link verilogamsGlobal Define 124hi def link verilogamsDirective SpecialComment 125hi def link verilogamsEscape Special 126hi def link verilogamsType Type 127hi def link verilogamsSystask Function 128 129 130let b:current_syntax = "verilogams" 131 132" vim: ts=8 133