1" Vim syntax file
2" Language:    SystemVerilog
3" Maintainer:  kocha <[email protected]>
4" Last Change: 12-Aug-2013.
5
6" For version 5.x: Clear all syntax items
7" For version 6.x: Quit when a syntax file was already loaded
8if version < 600
9    syntax clear
10elseif exists("b:current_syntax")
11    finish
12endif
13
14" Read in Verilog syntax files
15if version < 600
16    so <sfile>:p:h/verilog.vim
17else
18    runtime! syntax/verilog.vim
19    unlet b:current_syntax
20endif
21
22" IEEE1800-2005
23syn keyword systemverilogStatement   always_comb always_ff always_latch
24syn keyword systemverilogStatement   class endclass new
25syn keyword systemverilogStatement   virtual local const protected
26syn keyword systemverilogStatement   package endpackage
27syn keyword systemverilogStatement   rand randc constraint randomize
28syn keyword systemverilogStatement   with inside dist
29syn keyword systemverilogStatement   sequence endsequence randsequence
30syn keyword systemverilogStatement   srandom
31syn keyword systemverilogStatement   logic bit byte
32syn keyword systemverilogStatement   int longint shortint
33syn keyword systemverilogStatement   struct packed
34syn keyword systemverilogStatement   final
35syn keyword systemverilogStatement   import export
36syn keyword systemverilogStatement   context pure
37syn keyword systemverilogStatement   void shortreal chandle string
38syn keyword systemverilogStatement   clocking endclocking iff
39syn keyword systemverilogStatement   interface endinterface modport
40syn keyword systemverilogStatement   cover covergroup coverpoint endgroup
41syn keyword systemverilogStatement   property endproperty
42syn keyword systemverilogStatement   program endprogram
43syn keyword systemverilogStatement   bins binsof illegal_bins ignore_bins
44syn keyword systemverilogStatement   alias matches solve static assert
45syn keyword systemverilogStatement   assume super before expect bind
46syn keyword systemverilogStatement   extends null tagged extern this
47syn keyword systemverilogStatement   first_match throughout timeprecision
48syn keyword systemverilogStatement   timeunit type union
49syn keyword systemverilogStatement   uwire var cross ref wait_order intersect
50syn keyword systemverilogStatement   wildcard within
51
52syn keyword systemverilogTypeDef     typedef enum
53
54syn keyword systemverilogConditional randcase
55syn keyword systemverilogConditional unique priority
56
57syn keyword systemverilogRepeat      return break continue
58syn keyword systemverilogRepeat      do foreach
59
60syn keyword systemverilogLabel       join_any join_none forkjoin
61
62" IEEE1800-2009 add
63syn keyword systemverilogStatement   checker endchecker
64syn keyword systemverilogStatement   accept_on reject_on
65syn keyword systemverilogStatement   sync_accept_on sync_reject_on
66syn keyword systemverilogStatement   eventually nexttime until until_with
67syn keyword systemverilogStatement   s_always s_eventually s_nexttime s_until s_until_with
68syn keyword systemverilogStatement   let untyped
69syn keyword systemverilogStatement   strong weak
70syn keyword systemverilogStatement   restrict global implies
71
72syn keyword systemverilogConditional unique0
73
74" IEEE1800-2012 add
75syn keyword systemverilogStatement   implements
76syn keyword systemverilogStatement   interconnect soft nettype
77
78" Define the default highlighting.
79if version >= 508 || !exists("did_systemverilog_syn_inits")
80   if version < 508
81      let did_systemverilog_syn_inits = 1
82      command -nargs=+ HiLink hi link <args>
83   else
84      command -nargs=+ HiLink hi def link <args>
85   endif
86
87   " The default highlighting.
88   HiLink systemverilogStatement       Statement
89   HiLink systemverilogTypeDef         TypeDef
90   HiLink systemverilogConditional     Conditional
91   HiLink systemverilogRepeat          Repeat
92   HiLink systemverilogLabel           Label
93   HiLink systemverilogGlobal          Define
94   HiLink systemverilogNumber          Number
95
96   delcommand HiLink
97endif
98
99let b:current_syntax = "systemverilog"
100
101" vim: ts=8
102