1" Vim syntax file 2" Language: SystemVerilog 3" Maintainer: kocha <[email protected]> 4" Last Change: 12-Aug-2013. 5 6" quit when a syntax file was already loaded 7if exists("b:current_syntax") 8 finish 9endif 10 11" Read in Verilog syntax files 12runtime! syntax/verilog.vim 13unlet b:current_syntax 14 15" IEEE1800-2005 16syn keyword systemverilogStatement always_comb always_ff always_latch 17syn keyword systemverilogStatement class endclass new 18syn keyword systemverilogStatement virtual local const protected 19syn keyword systemverilogStatement package endpackage 20syn keyword systemverilogStatement rand randc constraint randomize 21syn keyword systemverilogStatement with inside dist 22syn keyword systemverilogStatement sequence endsequence randsequence 23syn keyword systemverilogStatement srandom 24syn keyword systemverilogStatement logic bit byte 25syn keyword systemverilogStatement int longint shortint 26syn keyword systemverilogStatement struct packed 27syn keyword systemverilogStatement final 28syn keyword systemverilogStatement import export 29syn keyword systemverilogStatement context pure 30syn keyword systemverilogStatement void shortreal chandle string 31syn keyword systemverilogStatement clocking endclocking iff 32syn keyword systemverilogStatement interface endinterface modport 33syn keyword systemverilogStatement cover covergroup coverpoint endgroup 34syn keyword systemverilogStatement property endproperty 35syn keyword systemverilogStatement program endprogram 36syn keyword systemverilogStatement bins binsof illegal_bins ignore_bins 37syn keyword systemverilogStatement alias matches solve static assert 38syn keyword systemverilogStatement assume super before expect bind 39syn keyword systemverilogStatement extends null tagged extern this 40syn keyword systemverilogStatement first_match throughout timeprecision 41syn keyword systemverilogStatement timeunit type union 42syn keyword systemverilogStatement uwire var cross ref wait_order intersect 43syn keyword systemverilogStatement wildcard within 44 45syn keyword systemverilogTypeDef typedef enum 46 47syn keyword systemverilogConditional randcase 48syn keyword systemverilogConditional unique priority 49 50syn keyword systemverilogRepeat return break continue 51syn keyword systemverilogRepeat do foreach 52 53syn keyword systemverilogLabel join_any join_none forkjoin 54 55" IEEE1800-2009 add 56syn keyword systemverilogStatement checker endchecker 57syn keyword systemverilogStatement accept_on reject_on 58syn keyword systemverilogStatement sync_accept_on sync_reject_on 59syn keyword systemverilogStatement eventually nexttime until until_with 60syn keyword systemverilogStatement s_always s_eventually s_nexttime s_until s_until_with 61syn keyword systemverilogStatement let untyped 62syn keyword systemverilogStatement strong weak 63syn keyword systemverilogStatement restrict global implies 64 65syn keyword systemverilogConditional unique0 66 67" IEEE1800-2012 add 68syn keyword systemverilogStatement implements 69syn keyword systemverilogStatement interconnect soft nettype 70 71" Define the default highlighting. 72 73" The default highlighting. 74hi def link systemverilogStatement Statement 75hi def link systemverilogTypeDef TypeDef 76hi def link systemverilogConditional Conditional 77hi def link systemverilogRepeat Repeat 78hi def link systemverilogLabel Label 79hi def link systemverilogGlobal Define 80hi def link systemverilogNumber Number 81 82 83let b:current_syntax = "systemverilog" 84 85" vim: ts=8 86