1*0089d489SMartin Mares00:00.0 Host bridge: Advanced Micro Devices, Inc. [AMD/ATI] RD890 PCI to PCI bridge (external gfx0 port A) (rev 02) 2*0089d489SMartin Mares Subsystem: Super Micro Computer Inc Device a711 3*0089d489SMartin Mares Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 4*0089d489SMartin Mares Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx- 5*0089d489SMartin Mares Capabilities: [f0] HyperTransport: MSI Mapping Enable+ Fixed+ 6*0089d489SMartin Mares Capabilities: [c4] HyperTransport: Slave or Primary Interface 7*0089d489SMartin Mares Command: BaseUnitID=0 UnitCnt=20 MastHost- DefDir- DUL- 8*0089d489SMartin Mares Link Control 0: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- 9*0089d489SMartin Mares Link Config 0: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- 10*0089d489SMartin Mares Link Control 1: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- 11*0089d489SMartin Mares Link Config 1: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- 12*0089d489SMartin Mares Revision ID: 3.00 13*0089d489SMartin Mares Link Frequency 0: [e] 14*0089d489SMartin Mares Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- 15*0089d489SMartin Mares Link Frequency Capability 0: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz+ 1.4GHz- 1.6GHz- Vend- 16*0089d489SMartin Mares Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA+ UIDRD- 17*0089d489SMartin Mares Link Frequency 1: 200MHz 18*0089d489SMartin Mares Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- 19*0089d489SMartin Mares Link Frequency Capability 1: 200MHz- 300MHz- 400MHz- 500MHz- 600MHz- 800MHz- 1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend- 20*0089d489SMartin Mares Error Handling: PFlE- OFlE- PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE- PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE- 21*0089d489SMartin Mares Prefetchable memory behind bridge Upper: 00-00 22*0089d489SMartin Mares Bus Number: 00 23*0089d489SMartin Mares Capabilities: [40] HyperTransport: Retry Mode 24*0089d489SMartin Mares Capabilities: [54] HyperTransport: UnitID Clumping 25*0089d489SMartin Mares Capabilities: [9c] HyperTransport: #1a 26*0089d489SMartin Mares Capabilities: [70] MSI: Enable- Count=1/4 Maskable- 64bit- 27*0089d489SMartin Mares Address: 00000000 Data: 0000 28*0089d489SMartin Mares00: 02 10 13 5a 02 00 10 20 02 00 00 06 00 00 80 00 29*0089d489SMartin Mares10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30*0089d489SMartin Mares20: 00 00 00 00 00 00 00 00 00 00 00 00 d9 15 11 a7 31*0089d489SMartin Mares30: 00 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 00 32*0089d489SMartin Mares40: 08 54 00 c0 c1 00 00 00 00 00 00 00 42 27 05 00 33*0089d489SMartin Mares50: d9 15 11 a7 08 9c 00 90 08 10 00 00 08 10 00 00 34*0089d489SMartin Mares60: 3c 00 00 00 00 00 00 00 00 00 00 40 63 4e 00 78 35*0089d489SMartin Mares70: 05 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 36*0089d489SMartin Mares80: 00 00 00 00 10 00 00 03 20 02 30 00 31 20 00 c0 37*0089d489SMartin Mares90: 00 00 00 e0 00 00 00 00 10 0d 00 00 08 70 3c d0 38*0089d489SMartin Maresa0: 66 00 00 00 00 00 00 83 00 00 00 00 79 41 00 00 39*0089d489SMartin Maresb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40*0089d489SMartin Maresc0: 00 00 00 80 08 40 80 02 20 00 11 11 d0 00 00 00 41*0089d489SMartin Maresd0: 60 0e f5 7f 13 00 00 00 00 00 00 00 00 00 00 00 42*0089d489SMartin Marese0: 00 00 05 00 ff ff ff ff 00 00 00 00 00 00 00 00 43*0089d489SMartin Maresf0: 08 c4 03 a8 00 80 80 00 01 00 00 00 08 00 c2 fe 44*0089d489SMartin Mares 45*0089d489SMartin Mares00:18.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 0 46*0089d489SMartin Mares Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 47*0089d489SMartin Mares Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 48*0089d489SMartin Mares Capabilities: [80] HyperTransport: Host or Secondary Interface 49*0089d489SMartin Mares Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- 50*0089d489SMartin Mares Link Control: CFlE- CST- CFE- <LkFail- Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- 51*0089d489SMartin Mares Link Config: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=N/C DwFcInEn- LWO=N/C DwFcOutEn- 52*0089d489SMartin Mares Revision ID: 3.00 53*0089d489SMartin Mares Link Frequency: 200MHz 54*0089d489SMartin Mares Link Error: <Prot- <Ovfl- <EOC- CTLTm- 55*0089d489SMartin Mares Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz+ 1.4GHz- 1.6GHz- Vend- 56*0089d489SMartin Mares Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA+ UIDRD- ExtRS- UCnfE- 57*0089d489SMartin Mares Capabilities: [a0] HyperTransport: Host or Secondary Interface 58*0089d489SMartin Mares Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- 59*0089d489SMartin Mares Link Control: CFlE- CST- CFE- <LkFail- Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- 60*0089d489SMartin Mares Link Config: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=N/C DwFcInEn- LWO=N/C DwFcOutEn- 61*0089d489SMartin Mares Revision ID: 3.00 62*0089d489SMartin Mares Link Frequency: 200MHz 63*0089d489SMartin Mares Link Error: <Prot- <Ovfl- <EOC- CTLTm- 64*0089d489SMartin Mares Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz+ 1.4GHz- 1.6GHz- Vend- 65*0089d489SMartin Mares Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA+ UIDRD- ExtRS- UCnfE- 66*0089d489SMartin Mares Capabilities: [c0] HyperTransport: Host or Secondary Interface 67*0089d489SMartin Mares Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- 68*0089d489SMartin Mares Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn+ ExtCTL- 64b- 69*0089d489SMartin Mares Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- 70*0089d489SMartin Mares Revision ID: 3.00 71*0089d489SMartin Mares Link Frequency: 500MHz 72*0089d489SMartin Mares Link Error: <Prot- <Ovfl- <EOC- CTLTm- 73*0089d489SMartin Mares Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz+ 1.4GHz- 1.6GHz- Vend- 74*0089d489SMartin Mares Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA+ UIDRD- ExtRS- UCnfE- 75*0089d489SMartin Mares Capabilities: [e0] HyperTransport: Host or Secondary Interface 76*0089d489SMartin Mares Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- 77*0089d489SMartin Mares Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn+ ExtCTL- 64b- 78*0089d489SMartin Mares Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- 79*0089d489SMartin Mares Revision ID: 3.00 80*0089d489SMartin Mares Link Frequency: [e] 81*0089d489SMartin Mares Link Error: <Prot- <Ovfl- <EOC- CTLTm- 82*0089d489SMartin Mares Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz+ 1.4GHz- 1.6GHz- Vend- 83*0089d489SMartin Mares Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA+ UIDRD- ExtRS- UCnfE- 84*0089d489SMartin Mares00: 22 10 00 16 00 00 10 00 00 00 00 06 00 00 80 00 85*0089d489SMartin Mares10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 86*0089d489SMartin Mares20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 87*0089d489SMartin Mares30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 88*0089d489SMartin Mares40: 01 02 24 00 08 10 04 00 01 02 04 00 01 02 04 00 89*0089d489SMartin Mares50: 01 02 04 00 01 02 04 00 01 02 04 00 01 02 04 00 90*0089d489SMartin Mares60: 10 00 0f 00 e0 03 00 00 00 b8 4e 02 10 0e 80 00 91*0089d489SMartin Mares70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 92*0089d489SMartin Mares80: 08 a0 01 21 c0 00 00 77 60 00 f5 ff 13 00 00 00 93*0089d489SMartin Mares90: 00 00 00 00 00 00 00 00 00 00 00 00 0e 00 00 00 94*0089d489SMartin Maresa0: 08 c0 01 21 c0 00 00 77 60 00 f5 ff 13 00 00 00 95*0089d489SMartin Maresb0: 00 00 00 00 00 00 00 00 00 00 00 00 0e 00 00 00 96*0089d489SMartin Maresc0: 08 e0 01 21 20 20 11 11 60 03 f5 ff 13 00 00 00 97*0089d489SMartin Maresd0: 48 49 8f 80 00 00 01 00 03 00 00 00 0f 00 00 00 98*0089d489SMartin Marese0: 08 00 01 21 20 20 11 11 60 0e f5 ff 13 00 00 00 99*0089d489SMartin Maresf0: ee 02 84 80 00 00 01 00 07 00 00 00 0e 00 00 00 100