13fef2d26SRiver Riddle //===- TestConvertGPUKernelToCubin.cpp - Test gpu kernel cubin lowering ---===//
23fef2d26SRiver Riddle //
33fef2d26SRiver Riddle // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
43fef2d26SRiver Riddle // See https://llvm.org/LICENSE.txt for license information.
53fef2d26SRiver Riddle // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
63fef2d26SRiver Riddle //
73fef2d26SRiver Riddle //===----------------------------------------------------------------------===//
83fef2d26SRiver Riddle 
93fef2d26SRiver Riddle #include "mlir/Dialect/GPU/Passes.h"
103fef2d26SRiver Riddle 
113fef2d26SRiver Riddle #include "mlir/Pass/Pass.h"
123fef2d26SRiver Riddle #include "mlir/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.h"
133fef2d26SRiver Riddle #include "mlir/Target/LLVMIR/Export.h"
143fef2d26SRiver Riddle #include "llvm/Support/TargetSelect.h"
153fef2d26SRiver Riddle 
163fef2d26SRiver Riddle using namespace mlir;
173fef2d26SRiver Riddle 
183fef2d26SRiver Riddle #if MLIR_CUDA_CONVERSIONS_ENABLED
193fef2d26SRiver Riddle namespace {
203fef2d26SRiver Riddle class TestSerializeToCubinPass
213fef2d26SRiver Riddle     : public PassWrapper<TestSerializeToCubinPass, gpu::SerializeToBlobPass> {
223fef2d26SRiver Riddle public:
23*b5e22e6dSMehdi Amini   StringRef getArgument() const final { return "test-gpu-to-cubin"; }
24*b5e22e6dSMehdi Amini   StringRef getDescription() const final {
25*b5e22e6dSMehdi Amini     return "Lower GPU kernel function to CUBIN binary annotations";
26*b5e22e6dSMehdi Amini   }
273fef2d26SRiver Riddle   TestSerializeToCubinPass();
283fef2d26SRiver Riddle 
293fef2d26SRiver Riddle private:
303fef2d26SRiver Riddle   void getDependentDialects(DialectRegistry &registry) const override;
313fef2d26SRiver Riddle 
323fef2d26SRiver Riddle   // Serializes PTX to CUBIN.
333fef2d26SRiver Riddle   std::unique_ptr<std::vector<char>>
343fef2d26SRiver Riddle   serializeISA(const std::string &isa) override;
353fef2d26SRiver Riddle };
363fef2d26SRiver Riddle } // namespace
373fef2d26SRiver Riddle 
383fef2d26SRiver Riddle TestSerializeToCubinPass::TestSerializeToCubinPass() {
393fef2d26SRiver Riddle   this->triple = "nvptx64-nvidia-cuda";
403fef2d26SRiver Riddle   this->chip = "sm_35";
413fef2d26SRiver Riddle   this->features = "+ptx60";
423fef2d26SRiver Riddle }
433fef2d26SRiver Riddle 
443fef2d26SRiver Riddle void TestSerializeToCubinPass::getDependentDialects(
453fef2d26SRiver Riddle     DialectRegistry &registry) const {
463fef2d26SRiver Riddle   registerNVVMDialectTranslation(registry);
473fef2d26SRiver Riddle   gpu::SerializeToBlobPass::getDependentDialects(registry);
483fef2d26SRiver Riddle }
493fef2d26SRiver Riddle 
503fef2d26SRiver Riddle std::unique_ptr<std::vector<char>>
513fef2d26SRiver Riddle TestSerializeToCubinPass::serializeISA(const std::string &) {
523fef2d26SRiver Riddle   std::string data = "CUBIN";
533fef2d26SRiver Riddle   return std::make_unique<std::vector<char>>(data.begin(), data.end());
543fef2d26SRiver Riddle }
553fef2d26SRiver Riddle 
563fef2d26SRiver Riddle namespace mlir {
573fef2d26SRiver Riddle namespace test {
583fef2d26SRiver Riddle // Register test pass to serialize GPU module to a CUBIN binary annotation.
593fef2d26SRiver Riddle void registerTestGpuSerializeToCubinPass() {
60*b5e22e6dSMehdi Amini   PassRegistration<TestSerializeToCubinPass>([] {
613fef2d26SRiver Riddle     // Initialize LLVM NVPTX backend.
623fef2d26SRiver Riddle     LLVMInitializeNVPTXTarget();
633fef2d26SRiver Riddle     LLVMInitializeNVPTXTargetInfo();
643fef2d26SRiver Riddle     LLVMInitializeNVPTXTargetMC();
653fef2d26SRiver Riddle     LLVMInitializeNVPTXAsmPrinter();
663fef2d26SRiver Riddle 
673fef2d26SRiver Riddle     return std::make_unique<TestSerializeToCubinPass>();
683fef2d26SRiver Riddle   });
693fef2d26SRiver Riddle }
703fef2d26SRiver Riddle } // namespace test
713fef2d26SRiver Riddle } // namespace mlir
723fef2d26SRiver Riddle #endif // MLIR_CUDA_CONVERSIONS_ENABLED
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