13fef2d26SRiver Riddle //===- TestConvertGPUKernelToCubin.cpp - Test gpu kernel cubin lowering ---===// 23fef2d26SRiver Riddle // 33fef2d26SRiver Riddle // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 43fef2d26SRiver Riddle // See https://llvm.org/LICENSE.txt for license information. 53fef2d26SRiver Riddle // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 63fef2d26SRiver Riddle // 73fef2d26SRiver Riddle //===----------------------------------------------------------------------===// 83fef2d26SRiver Riddle 93fef2d26SRiver Riddle #include "mlir/Dialect/GPU/Passes.h" 103fef2d26SRiver Riddle 113fef2d26SRiver Riddle #include "mlir/Pass/Pass.h" 123fef2d26SRiver Riddle #include "mlir/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.h" 133fef2d26SRiver Riddle #include "mlir/Target/LLVMIR/Export.h" 143fef2d26SRiver Riddle #include "llvm/Support/TargetSelect.h" 153fef2d26SRiver Riddle 163fef2d26SRiver Riddle using namespace mlir; 173fef2d26SRiver Riddle 183fef2d26SRiver Riddle #if MLIR_CUDA_CONVERSIONS_ENABLED 193fef2d26SRiver Riddle namespace { 203fef2d26SRiver Riddle class TestSerializeToCubinPass 213fef2d26SRiver Riddle : public PassWrapper<TestSerializeToCubinPass, gpu::SerializeToBlobPass> { 223fef2d26SRiver Riddle public: 23*5e50dd04SRiver Riddle MLIR_DEFINE_EXPLICIT_INTERNAL_INLINE_TYPE_ID(TestSerializeToCubinPass) 24*5e50dd04SRiver Riddle 25b5e22e6dSMehdi Amini StringRef getArgument() const final { return "test-gpu-to-cubin"; } 26b5e22e6dSMehdi Amini StringRef getDescription() const final { 27b5e22e6dSMehdi Amini return "Lower GPU kernel function to CUBIN binary annotations"; 28b5e22e6dSMehdi Amini } 293fef2d26SRiver Riddle TestSerializeToCubinPass(); 303fef2d26SRiver Riddle 313fef2d26SRiver Riddle private: 323fef2d26SRiver Riddle void getDependentDialects(DialectRegistry ®istry) const override; 333fef2d26SRiver Riddle 343fef2d26SRiver Riddle // Serializes PTX to CUBIN. 353fef2d26SRiver Riddle std::unique_ptr<std::vector<char>> 363fef2d26SRiver Riddle serializeISA(const std::string &isa) override; 373fef2d26SRiver Riddle }; 383fef2d26SRiver Riddle } // namespace 393fef2d26SRiver Riddle 403fef2d26SRiver Riddle TestSerializeToCubinPass::TestSerializeToCubinPass() { 413fef2d26SRiver Riddle this->triple = "nvptx64-nvidia-cuda"; 423fef2d26SRiver Riddle this->chip = "sm_35"; 433fef2d26SRiver Riddle this->features = "+ptx60"; 443fef2d26SRiver Riddle } 453fef2d26SRiver Riddle 463fef2d26SRiver Riddle void TestSerializeToCubinPass::getDependentDialects( 473fef2d26SRiver Riddle DialectRegistry ®istry) const { 483fef2d26SRiver Riddle registerNVVMDialectTranslation(registry); 493fef2d26SRiver Riddle gpu::SerializeToBlobPass::getDependentDialects(registry); 503fef2d26SRiver Riddle } 513fef2d26SRiver Riddle 523fef2d26SRiver Riddle std::unique_ptr<std::vector<char>> 533fef2d26SRiver Riddle TestSerializeToCubinPass::serializeISA(const std::string &) { 543fef2d26SRiver Riddle std::string data = "CUBIN"; 553fef2d26SRiver Riddle return std::make_unique<std::vector<char>>(data.begin(), data.end()); 563fef2d26SRiver Riddle } 573fef2d26SRiver Riddle 583fef2d26SRiver Riddle namespace mlir { 593fef2d26SRiver Riddle namespace test { 603fef2d26SRiver Riddle // Register test pass to serialize GPU module to a CUBIN binary annotation. 613fef2d26SRiver Riddle void registerTestGpuSerializeToCubinPass() { 62b5e22e6dSMehdi Amini PassRegistration<TestSerializeToCubinPass>([] { 633fef2d26SRiver Riddle // Initialize LLVM NVPTX backend. 643fef2d26SRiver Riddle LLVMInitializeNVPTXTarget(); 653fef2d26SRiver Riddle LLVMInitializeNVPTXTargetInfo(); 663fef2d26SRiver Riddle LLVMInitializeNVPTXTargetMC(); 673fef2d26SRiver Riddle LLVMInitializeNVPTXAsmPrinter(); 683fef2d26SRiver Riddle 693fef2d26SRiver Riddle return std::make_unique<TestSerializeToCubinPass>(); 703fef2d26SRiver Riddle }); 713fef2d26SRiver Riddle } 723fef2d26SRiver Riddle } // namespace test 733fef2d26SRiver Riddle } // namespace mlir 743fef2d26SRiver Riddle #endif // MLIR_CUDA_CONVERSIONS_ENABLED 75