1*3fef2d26SRiver Riddle //===- TestConvertGPUKernelToCubin.cpp - Test gpu kernel cubin lowering ---===// 2*3fef2d26SRiver Riddle // 3*3fef2d26SRiver Riddle // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*3fef2d26SRiver Riddle // See https://llvm.org/LICENSE.txt for license information. 5*3fef2d26SRiver Riddle // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*3fef2d26SRiver Riddle // 7*3fef2d26SRiver Riddle //===----------------------------------------------------------------------===// 8*3fef2d26SRiver Riddle 9*3fef2d26SRiver Riddle #include "mlir/Dialect/GPU/Passes.h" 10*3fef2d26SRiver Riddle 11*3fef2d26SRiver Riddle #include "mlir/Pass/Pass.h" 12*3fef2d26SRiver Riddle #include "mlir/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.h" 13*3fef2d26SRiver Riddle #include "mlir/Target/LLVMIR/Export.h" 14*3fef2d26SRiver Riddle #include "llvm/Support/TargetSelect.h" 15*3fef2d26SRiver Riddle 16*3fef2d26SRiver Riddle using namespace mlir; 17*3fef2d26SRiver Riddle 18*3fef2d26SRiver Riddle #if MLIR_CUDA_CONVERSIONS_ENABLED 19*3fef2d26SRiver Riddle namespace { 20*3fef2d26SRiver Riddle class TestSerializeToCubinPass 21*3fef2d26SRiver Riddle : public PassWrapper<TestSerializeToCubinPass, gpu::SerializeToBlobPass> { 22*3fef2d26SRiver Riddle public: 23*3fef2d26SRiver Riddle TestSerializeToCubinPass(); 24*3fef2d26SRiver Riddle 25*3fef2d26SRiver Riddle private: 26*3fef2d26SRiver Riddle void getDependentDialects(DialectRegistry ®istry) const override; 27*3fef2d26SRiver Riddle 28*3fef2d26SRiver Riddle // Serializes PTX to CUBIN. 29*3fef2d26SRiver Riddle std::unique_ptr<std::vector<char>> 30*3fef2d26SRiver Riddle serializeISA(const std::string &isa) override; 31*3fef2d26SRiver Riddle }; 32*3fef2d26SRiver Riddle } // namespace 33*3fef2d26SRiver Riddle 34*3fef2d26SRiver Riddle TestSerializeToCubinPass::TestSerializeToCubinPass() { 35*3fef2d26SRiver Riddle this->triple = "nvptx64-nvidia-cuda"; 36*3fef2d26SRiver Riddle this->chip = "sm_35"; 37*3fef2d26SRiver Riddle this->features = "+ptx60"; 38*3fef2d26SRiver Riddle } 39*3fef2d26SRiver Riddle 40*3fef2d26SRiver Riddle void TestSerializeToCubinPass::getDependentDialects( 41*3fef2d26SRiver Riddle DialectRegistry ®istry) const { 42*3fef2d26SRiver Riddle registerNVVMDialectTranslation(registry); 43*3fef2d26SRiver Riddle gpu::SerializeToBlobPass::getDependentDialects(registry); 44*3fef2d26SRiver Riddle } 45*3fef2d26SRiver Riddle 46*3fef2d26SRiver Riddle std::unique_ptr<std::vector<char>> 47*3fef2d26SRiver Riddle TestSerializeToCubinPass::serializeISA(const std::string &) { 48*3fef2d26SRiver Riddle std::string data = "CUBIN"; 49*3fef2d26SRiver Riddle return std::make_unique<std::vector<char>>(data.begin(), data.end()); 50*3fef2d26SRiver Riddle } 51*3fef2d26SRiver Riddle 52*3fef2d26SRiver Riddle namespace mlir { 53*3fef2d26SRiver Riddle namespace test { 54*3fef2d26SRiver Riddle // Register test pass to serialize GPU module to a CUBIN binary annotation. 55*3fef2d26SRiver Riddle void registerTestGpuSerializeToCubinPass() { 56*3fef2d26SRiver Riddle PassRegistration<TestSerializeToCubinPass> registerSerializeToCubin( 57*3fef2d26SRiver Riddle "test-gpu-to-cubin", 58*3fef2d26SRiver Riddle "Lower GPU kernel function to CUBIN binary annotations", [] { 59*3fef2d26SRiver Riddle // Initialize LLVM NVPTX backend. 60*3fef2d26SRiver Riddle LLVMInitializeNVPTXTarget(); 61*3fef2d26SRiver Riddle LLVMInitializeNVPTXTargetInfo(); 62*3fef2d26SRiver Riddle LLVMInitializeNVPTXTargetMC(); 63*3fef2d26SRiver Riddle LLVMInitializeNVPTXAsmPrinter(); 64*3fef2d26SRiver Riddle 65*3fef2d26SRiver Riddle return std::make_unique<TestSerializeToCubinPass>(); 66*3fef2d26SRiver Riddle }); 67*3fef2d26SRiver Riddle } 68*3fef2d26SRiver Riddle } // namespace test 69*3fef2d26SRiver Riddle } // namespace mlir 70*3fef2d26SRiver Riddle #endif // MLIR_CUDA_CONVERSIONS_ENABLED 71