16bb7d247SNicolas Vasilache// RUN: mlir-opt -split-input-file -test-linalg-transform-patterns=test-linalg-to-vector-patterns %s | FileCheck %s
26bb7d247SNicolas Vasilache
392d38adbSRiver Riddlefunc.func @conv1d_nwc_4x2x8_memref(%input: memref<4x6x3xf32>, %filter: memref<1x3x8xf32>, %output: memref<4x2x8xf32>) {
46bb7d247SNicolas Vasilache  linalg.conv_1d_nwc_wcf
56bb7d247SNicolas Vasilache    {dilations = dense<1> : tensor<1xi64>, strides = dense<3> : tensor<1xi64>}
66bb7d247SNicolas Vasilache    ins(%input, %filter : memref<4x6x3xf32>, memref<1x3x8xf32>)
76bb7d247SNicolas Vasilache    outs(%output : memref<4x2x8xf32>)
86bb7d247SNicolas Vasilache  return
96bb7d247SNicolas Vasilache}
106bb7d247SNicolas Vasilache
116bb7d247SNicolas Vasilache// CHECK: #[[INPUT_MAP:.+]] = affine_map<(d0, d1, d2, d3) -> (d0, d1, d3)>
12203accf0SNicolas Vasilache// CHECK: #[[FILTER_MAP:.+]] = affine_map<(d0, d1, d2, d3) -> (d3, d2)>
136bb7d247SNicolas Vasilache// CHECK: #[[OUTPUT_MAP:.+]] = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2)>
146bb7d247SNicolas Vasilache
156bb7d247SNicolas Vasilache//      CHECK: func @conv1d_nwc_4x2x8_memref
166bb7d247SNicolas Vasilache// CHECK-SAME: (%[[INPUT:.+]]: memref<4x6x3xf32>, %[[FILTER:.+]]: memref<1x3x8xf32>, %[[OUTPUT:.+]]: memref<4x2x8xf32>)
176bb7d247SNicolas Vasilache
186bb7d247SNicolas Vasilache//  CHECK-DAG:   %[[C0:.+]] = arith.constant 0 : index
196bb7d247SNicolas Vasilache//  CHECK-DAG:   %[[F0:.+]] = arith.constant 0.000000e+00 : f32
206bb7d247SNicolas Vasilache
219c497174SNicolas Vasilache/// Read the whole data in one shot.
229c497174SNicolas Vasilache//  CHECK-DAG:   %[[V_INPUT_R:.+]] = vector.transfer_read %[[INPUT]][%[[C0]], %[[C0]], %[[C0]]], %[[F0]]
239c497174SNicolas Vasilache//  CHECK-DAG:  %[[V_FILTER_R:.+]] = vector.transfer_read %[[FILTER]][%[[C0]], %[[C0]], %[[C0]]], %[[F0]]
249c497174SNicolas Vasilache//  CHECK-DAG:  %[[V_OUTPUT_R:.+]] = vector.transfer_read %[[OUTPUT]][%[[C0]], %[[C0]], %[[C0]]], %[[F0]]
259c497174SNicolas Vasilache
269c497174SNicolas Vasilache//      CHECK:   %[[V_INPUT_0:.+]] = vector.extract_strided_slice %[[V_INPUT_R]]
27f1c86b83SNicolas Vasilache// CHECK-SAME:     {offsets = [0, 0, 0], sizes = [4, 1, 3], strides = [1, 1, 1]} : vector<4x4x3xf32> to vector<4x1x3xf32>
289c497174SNicolas Vasilache//      CHECK:   %[[V_INPUT_1:.+]] = vector.extract_strided_slice %[[V_INPUT_R]]
29f1c86b83SNicolas Vasilache// CHECK-SAME:     {offsets = [0, 3, 0], sizes = [4, 1, 3], strides = [1, 1, 1]} : vector<4x4x3xf32> to vector<4x1x3xf32>
30392e16c2SNicolas Vasilache
31392e16c2SNicolas Vasilache//      CHECK:    %[[V_FILTER:.+]] = vector.extract %[[V_FILTER_R]][0] : vector<1x3x8xf32>
32392e16c2SNicolas Vasilache
33392e16c2SNicolas Vasilache//      CHECK:  %[[V_OUTPUT_0:.+]] = vector.extract_strided_slice %[[V_OUTPUT_R]]
34392e16c2SNicolas Vasilache// CHECK-SAME:     {offsets = [0, 0, 0], sizes = [4, 1, 8], strides = [1, 1, 1]} : vector<4x2x8xf32> to vector<4x1x8xf32>
359c497174SNicolas Vasilache//      CHECK:  %[[V_OUTPUT_1:.+]] = vector.extract_strided_slice %[[V_OUTPUT_R]]
369c497174SNicolas Vasilache// CHECK-SAME:     {offsets = [0, 1, 0], sizes = [4, 1, 8], strides = [1, 1, 1]} : vector<4x2x8xf32> to vector<4x1x8xf32>
377b09f157SNicolas Vasilache
387b09f157SNicolas Vasilache/// w == 0, kw == 0
399c497174SNicolas Vasilache//      CHECK:   %[[CONTRACT_0:.+]] = vector.contract {
406bb7d247SNicolas Vasilache// CHECK-SAME:       indexing_maps = [#[[INPUT_MAP]], #[[FILTER_MAP]], #[[OUTPUT_MAP]]],
416bb7d247SNicolas Vasilache// CHECK-SAME:       iterator_types = ["parallel", "parallel", "parallel", "reduction"]}
429c497174SNicolas Vasilache// CHECK-SAME:     %[[V_INPUT_0]], %[[V_FILTER]], %[[V_OUTPUT_0]]
43203accf0SNicolas Vasilache// CHECK-SAME:     : vector<4x1x3xf32>, vector<3x8xf32> into vector<4x1x8xf32>
449c497174SNicolas Vasilache
456bb7d247SNicolas Vasilache/// w == 1, kw == 0
469c497174SNicolas Vasilache//      CHECK:   %[[CONTRACT_1:.+]] = vector.contract {
476bb7d247SNicolas Vasilache// CHECK-SAME:       indexing_maps = [#[[INPUT_MAP]], #[[FILTER_MAP]], #[[OUTPUT_MAP]]],
486bb7d247SNicolas Vasilache// CHECK-SAME:       iterator_types = ["parallel", "parallel", "parallel", "reduction"]}
499c497174SNicolas Vasilache// CHECK-SAME:     %[[V_INPUT_1]], %[[V_FILTER]], %[[V_OUTPUT_1]]
50203accf0SNicolas Vasilache// CHECK-SAME:     : vector<4x1x3xf32>, vector<3x8xf32> into vector<4x1x8xf32>
517b09f157SNicolas Vasilache
527b09f157SNicolas Vasilache/// w == 0, kw == 0
539c497174SNicolas Vasilache//      CHECK:   %[[RES_0:.+]] = vector.insert_strided_slice %[[CONTRACT_0]], %[[V_OUTPUT_R]]
549c497174SNicolas Vasilache// CHECK-SAME:     {offsets = [0, 0, 0], strides = [1, 1, 1]} : vector<4x1x8xf32> into vector<4x2x8xf32>
557b09f157SNicolas Vasilache/// w == 1, kw == 0
569c497174SNicolas Vasilache//      CHECK:   %[[RES_1:.+]] = vector.insert_strided_slice %[[CONTRACT_1]], %[[RES_0]]
579c497174SNicolas Vasilache// CHECK-SAME:     {offsets = [0, 1, 0], strides = [1, 1, 1]} : vector<4x1x8xf32> into vector<4x2x8xf32>
589c497174SNicolas Vasilache
599c497174SNicolas Vasilache// Write the result back in one shot.
609c497174SNicolas Vasilache//      CHECK:   vector.transfer_write %[[RES_1]], %[[OUTPUT]][%[[C0]], %[[C0]], %[[C0]]]
616bb7d247SNicolas Vasilache
626bb7d247SNicolas Vasilache// -----
636bb7d247SNicolas Vasilache
6492d38adbSRiver Riddlefunc.func @conv1d_nwc_4x2x8_memref(%input: memref<4x6x3xf32>, %filter: memref<2x3x8xf32>, %output: memref<4x2x8xf32>) {
656bb7d247SNicolas Vasilache  linalg.conv_1d_nwc_wcf
666bb7d247SNicolas Vasilache    {dilations = dense<2> : tensor<1xi64>, strides = dense<3> : tensor<1xi64>}
676bb7d247SNicolas Vasilache    ins(%input, %filter : memref<4x6x3xf32>, memref<2x3x8xf32>)
686bb7d247SNicolas Vasilache    outs(%output : memref<4x2x8xf32>)
696bb7d247SNicolas Vasilache  return
706bb7d247SNicolas Vasilache}
716bb7d247SNicolas Vasilache
726bb7d247SNicolas Vasilache// CHECK: #[[INPUT_MAP:.+]] = affine_map<(d0, d1, d2, d3) -> (d0, d1, d3)>
73203accf0SNicolas Vasilache// CHECK: #[[FILTER_MAP:.+]] = affine_map<(d0, d1, d2, d3) -> (d3, d2)>
746bb7d247SNicolas Vasilache// CHECK: #[[OUTPUT_MAP:.+]] = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2)>
756bb7d247SNicolas Vasilache
766bb7d247SNicolas Vasilache//      CHECK: func @conv1d_nwc_4x2x8_memref
776bb7d247SNicolas Vasilache// CHECK-SAME: (%[[INPUT:.+]]: memref<4x6x3xf32>, %[[FILTER:.+]]: memref<2x3x8xf32>, %[[OUTPUT:.+]]: memref<4x2x8xf32>)
786bb7d247SNicolas Vasilache
796bb7d247SNicolas Vasilache//  CHECK-DAG:   %[[C0:.+]] = arith.constant 0 : index
806bb7d247SNicolas Vasilache//  CHECK-DAG:   %[[F0:.+]] = arith.constant 0.000000e+00 : f32
816bb7d247SNicolas Vasilache
829c497174SNicolas Vasilache/// Read the whole data in one shot.
839c497174SNicolas Vasilache//  CHECK-DAG:   %[[V_INPUT_R:.+]] = vector.transfer_read %[[INPUT]][%[[C0]], %[[C0]], %[[C0]]], %[[F0]]
849c497174SNicolas Vasilache//  CHECK-DAG:   %[[V_FILTER_R:.+]] = vector.transfer_read %[[FILTER]][%[[C0]], %[[C0]], %[[C0]]], %[[F0]]
859c497174SNicolas Vasilache//  CHECK-DAG:   %[[V_OUTPUT_R:.+]] = vector.transfer_read %[[OUTPUT]][%[[C0]], %[[C0]], %[[C0]]], %[[F0]]
869c497174SNicolas Vasilache
879c497174SNicolas Vasilache//      CHECK:   %[[V_INPUT_0:.+]] = vector.extract_strided_slice %[[V_INPUT_R]]
88f1c86b83SNicolas Vasilache// CHECK-SAME:     {offsets = [0, 0, 0], sizes = [4, 1, 3], strides = [1, 1, 1]} : vector<4x6x3xf32> to vector<4x1x3xf32>
899c497174SNicolas Vasilache//      CHECK:   %[[V_INPUT_1:.+]] = vector.extract_strided_slice %[[V_INPUT_R]]
90f1c86b83SNicolas Vasilache// CHECK-SAME:     {offsets = [0, 3, 0], sizes = [4, 1, 3], strides = [1, 1, 1]} : vector<4x6x3xf32> to vector<4x1x3xf32>
919c497174SNicolas Vasilache//      CHECK:   %[[V_INPUT_2:.+]] = vector.extract_strided_slice %[[V_INPUT_R]]
92f1c86b83SNicolas Vasilache// CHECK-SAME:     {offsets = [0, 2, 0], sizes = [4, 1, 3], strides = [1, 1, 1]} : vector<4x6x3xf32> to vector<4x1x3xf32>
939c497174SNicolas Vasilache//      CHECK:   %[[V_INPUT_3:.+]] = vector.extract_strided_slice %[[V_INPUT_R]]
94f1c86b83SNicolas Vasilache// CHECK-SAME:     {offsets = [0, 5, 0], sizes = [4, 1, 3], strides = [1, 1, 1]} : vector<4x6x3xf32> to vector<4x1x3xf32>
959c497174SNicolas Vasilache
96392e16c2SNicolas Vasilache//      CHECK:  %[[V_FILTER_0:.+]] = vector.extract %[[V_FILTER_R]][0] : vector<2x3x8xf32>
97392e16c2SNicolas Vasilache//      CHECK:  %[[V_FILTER_1:.+]] = vector.extract %[[V_FILTER_R]][1] : vector<2x3x8xf32>
98392e16c2SNicolas Vasilache
99392e16c2SNicolas Vasilache//      CHECK:  %[[V_OUTPUT_0:.+]] = vector.extract_strided_slice %[[V_OUTPUT_R]]
100392e16c2SNicolas Vasilache// CHECK-SAME:     {offsets = [0, 0, 0], sizes = [4, 1, 8], strides = [1, 1, 1]} : vector<4x2x8xf32> to vector<4x1x8xf32>
101392e16c2SNicolas Vasilache//      CHECK:  %[[V_OUTPUT_1:.+]] = vector.extract_strided_slice %[[V_OUTPUT_R]]
102392e16c2SNicolas Vasilache// CHECK-SAME:     {offsets = [0, 1, 0], sizes = [4, 1, 8], strides = [1, 1, 1]} : vector<4x2x8xf32> to vector<4x1x8xf32>
103392e16c2SNicolas Vasilache
1049c497174SNicolas Vasilache/// w == 0, kw == 0
1059c497174SNicolas Vasilache//      CHECK:   %[[CONTRACT_0:.+]] = vector.contract {
1066bb7d247SNicolas Vasilache// CHECK-SAME:       indexing_maps = [#[[INPUT_MAP]], #[[FILTER_MAP]], #[[OUTPUT_MAP]]],
1076bb7d247SNicolas Vasilache// CHECK-SAME:       iterator_types = ["parallel", "parallel", "parallel", "reduction"]}
1089c497174SNicolas Vasilache// CHECK-SAME:     %[[V_INPUT_0]], %[[V_FILTER_0]], %[[V_OUTPUT_0]]
109203accf0SNicolas Vasilache// CHECK-SAME:     : vector<4x1x3xf32>, vector<3x8xf32> into vector<4x1x8xf32>
1106bb7d247SNicolas Vasilache/// w == 1, kw == 0
1119c497174SNicolas Vasilache//      CHECK:   %[[CONTRACT_1:.+]] = vector.contract {
1126bb7d247SNicolas Vasilache// CHECK-SAME:       indexing_maps = [#[[INPUT_MAP]], #[[FILTER_MAP]], #[[OUTPUT_MAP]]],
1136bb7d247SNicolas Vasilache// CHECK-SAME:       iterator_types = ["parallel", "parallel", "parallel", "reduction"]}
1149c497174SNicolas Vasilache// CHECK-SAME:     %[[V_INPUT_1]], %[[V_FILTER_0]], %[[V_OUTPUT_1]]
115203accf0SNicolas Vasilache// CHECK-SAME:     : vector<4x1x3xf32>, vector<3x8xf32> into vector<4x1x8xf32>
1166bb7d247SNicolas Vasilache/// w == 1, kw == 1
1179c497174SNicolas Vasilache//      CHECK:   %[[CONTRACT_2:.+]] = vector.contract {
1186bb7d247SNicolas Vasilache// CHECK-SAME:       indexing_maps = [#[[INPUT_MAP]], #[[FILTER_MAP]], #[[OUTPUT_MAP]]],
1196bb7d247SNicolas Vasilache// CHECK-SAME:       iterator_types = ["parallel", "parallel", "parallel", "reduction"]}
1209c497174SNicolas Vasilache// CHECK-SAME:     %[[V_INPUT_2]], %[[V_FILTER_1]], %[[CONTRACT_0]]
1219c497174SNicolas Vasilache// CHECK-SAME:     : vector<4x1x3xf32>, vector<3x8xf32> into vector<4x1x8xf32>
1229c497174SNicolas Vasilache/// w == 1, kw == 1
1239c497174SNicolas Vasilache//      CHECK:   %[[CONTRACT_3:.+]] = vector.contract {
1249c497174SNicolas Vasilache// CHECK-SAME:       indexing_maps = [#[[INPUT_MAP]], #[[FILTER_MAP]], #[[OUTPUT_MAP]]],
1259c497174SNicolas Vasilache// CHECK-SAME:       iterator_types = ["parallel", "parallel", "parallel", "reduction"]}
1269c497174SNicolas Vasilache// CHECK-SAME:     %[[V_INPUT_3]], %[[V_FILTER_1]], %[[CONTRACT_1]]
127203accf0SNicolas Vasilache// CHECK-SAME:     : vector<4x1x3xf32>, vector<3x8xf32> into vector<4x1x8xf32>
1287b09f157SNicolas Vasilache
1297b09f157SNicolas Vasilache/// w == 0, kw == 0
1309c497174SNicolas Vasilache//      CHECK:   %[[RES_0:.+]] = vector.insert_strided_slice %[[CONTRACT_2]], %[[V_OUTPUT_R]]
1319c497174SNicolas Vasilache// CHECK-SAME:     {offsets = [0, 0, 0], strides = [1, 1, 1]} : vector<4x1x8xf32> into vector<4x2x8xf32>
1327b09f157SNicolas Vasilache/// w == 1, kw == 0
1339c497174SNicolas Vasilache//      CHECK:   %[[RES_1:.+]] = vector.insert_strided_slice %[[CONTRACT_3]], %[[RES_0]]
1349c497174SNicolas Vasilache// CHECK-SAME:     {offsets = [0, 1, 0], strides = [1, 1, 1]} : vector<4x1x8xf32> into vector<4x2x8xf32>
1359c497174SNicolas Vasilache
1369c497174SNicolas Vasilache// Write the result back in one shot.
1379c497174SNicolas Vasilache//      CHECK:   vector.transfer_write %[[RES_1]], %[[OUTPUT]][%[[C0]], %[[C0]], %[[C0]]]
138203accf0SNicolas Vasilache
139203accf0SNicolas Vasilache// -----
140203accf0SNicolas Vasilache
14192d38adbSRiver Riddlefunc.func @conv1d_nwc_4x2x8_memref(%input: memref<4x6x3xf32>, %filter: memref<2x3x8xf32>, %output: memref<4x2x8xf32>) {
1429c497174SNicolas Vasilache  linalg.conv_1d_nwc_wcf
1439c497174SNicolas Vasilache    {dilations = dense<2> : tensor<1xi64>, strides = dense<1> : tensor<1xi64>}
1449c497174SNicolas Vasilache    ins(%input, %filter : memref<4x6x3xf32>, memref<2x3x8xf32>)
1459c497174SNicolas Vasilache    outs(%output : memref<4x2x8xf32>)
1469c497174SNicolas Vasilache  return
1479c497174SNicolas Vasilache}
1489c497174SNicolas Vasilache
149203accf0SNicolas Vasilache// CHECK: #[[INPUT_MAP:.+]] = affine_map<(d0, d1, d2, d3) -> (d0, d1, d3)>
150203accf0SNicolas Vasilache// CHECK: #[[FILTER_MAP:.+]] = affine_map<(d0, d1, d2, d3) -> (d3, d2)>
151203accf0SNicolas Vasilache// CHECK: #[[OUTPUT_MAP:.+]] = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2)>
152203accf0SNicolas Vasilache
153203accf0SNicolas Vasilache//      CHECK: func @conv1d_nwc_4x2x8_memref
154203accf0SNicolas Vasilache// CHECK-SAME: (%[[INPUT:.+]]: memref<4x6x3xf32>, %[[FILTER:.+]]: memref<2x3x8xf32>, %[[OUTPUT:.+]]: memref<4x2x8xf32>)
1559c497174SNicolas Vasilache
156203accf0SNicolas Vasilache//  CHECK-DAG:   %[[C0:.+]] = arith.constant 0 : index
157203accf0SNicolas Vasilache//  CHECK-DAG:   %[[F0:.+]] = arith.constant 0.000000e+00 : f32
158203accf0SNicolas Vasilache
1599c497174SNicolas Vasilache/// Read the whole data in one shot.
1609c497174SNicolas Vasilache//  CHECK-DAG:   %[[V_INPUT_R:.+]] = vector.transfer_read %[[INPUT]][%[[C0]], %[[C0]], %[[C0]]], %[[F0]]
1619c497174SNicolas Vasilache//  CHECK-DAG:  %[[V_FILTER_R:.+]] = vector.transfer_read %[[FILTER]][%[[C0]], %[[C0]], %[[C0]]], %[[F0]]
1629c497174SNicolas Vasilache//  CHECK-DAG:  %[[V_OUTPUT_R:.+]] = vector.transfer_read %[[OUTPUT]][%[[C0]], %[[C0]], %[[C0]]], %[[F0]]
1637b09f157SNicolas Vasilache
1649c497174SNicolas Vasilache//      CHECK:   %[[V_INPUT_0:.+]] = vector.extract_strided_slice %[[V_INPUT_R]]
165f1c86b83SNicolas Vasilache// CHECK-SAME:     {offsets = [0, 0, 0], sizes = [4, 2, 3], strides = [1, 1, 1]} : vector<4x4x3xf32> to vector<4x2x3xf32>
1669c497174SNicolas Vasilache//      CHECK:   %[[V_INPUT_1:.+]] = vector.extract_strided_slice %[[V_INPUT_R]]
167f1c86b83SNicolas Vasilache// CHECK-SAME:     {offsets = [0, 2, 0], sizes = [4, 2, 3], strides = [1, 1, 1]} : vector<4x4x3xf32> to vector<4x2x3xf32>
1687b09f157SNicolas Vasilache
169392e16c2SNicolas Vasilache//      CHECK:  %[[V_FILTER_0:.+]] = vector.extract %[[V_FILTER_R]][0] : vector<2x3x8xf32>
170392e16c2SNicolas Vasilache//      CHECK:  %[[V_FILTER_1:.+]] = vector.extract %[[V_FILTER_R]][1] : vector<2x3x8xf32>
171392e16c2SNicolas Vasilache
1727b09f157SNicolas Vasilache/// w == 0, kw == 0
1739c497174SNicolas Vasilache//      CHECK:   %[[CONTRACT_0:.+]] = vector.contract {
1749c497174SNicolas Vasilache// CHECK-SAME:       indexing_maps = [#[[INPUT_MAP]], #[[FILTER_MAP]], #[[OUTPUT_MAP]]],
1759c497174SNicolas Vasilache// CHECK-SAME:       iterator_types = ["parallel", "parallel", "parallel", "reduction"]}
1769c497174SNicolas Vasilache// CHECK-SAME:     %[[V_INPUT_0]], %[[V_FILTER_0]], %[[V_OUTPUT_R]]
1779c497174SNicolas Vasilache// CHECK-SAME:     : vector<4x2x3xf32>, vector<3x8xf32> into vector<4x2x8xf32>
17899ff697bSNicolas Vasilache/// w == 0, kw == 1
1799c497174SNicolas Vasilache//      CHECK:   %[[CONTRACT_1:.+]] = vector.contract {
1809c497174SNicolas Vasilache// CHECK-SAME:       indexing_maps = [#[[INPUT_MAP]], #[[FILTER_MAP]], #[[OUTPUT_MAP]]],
1819c497174SNicolas Vasilache// CHECK-SAME:       iterator_types = ["parallel", "parallel", "parallel", "reduction"]}
1829c497174SNicolas Vasilache// CHECK-SAME:     %[[V_INPUT_1]], %[[V_FILTER_1]], %[[CONTRACT_0]]
1839c497174SNicolas Vasilache// CHECK-SAME:     : vector<4x2x3xf32>, vector<3x8xf32> into vector<4x2x8xf32>
1849c497174SNicolas Vasilache
1859c497174SNicolas Vasilache// Write the result back in one shot.
1869c497174SNicolas Vasilache//      CHECK:   vector.transfer_write %[[CONTRACT_1]], %[[OUTPUT]][%[[C0]], %[[C0]], %[[C0]]]
18799ff697bSNicolas Vasilache
18899ff697bSNicolas Vasilache// -----
18999ff697bSNicolas Vasilache
19092d38adbSRiver Riddlefunc.func @depthwise_conv1d_nwc_wc_3x5x4_memref(%input: memref<3x5x4xf32>, %filter: memref<2x4xf32>, %output: memref<3x2x4xf32>) {
191f67171acSNicolas Vasilache  linalg.depthwise_conv_1d_nwc_wc
19299ff697bSNicolas Vasilache    {dilations = dense<2> : tensor<1xi64>, strides = dense<1> : tensor<1xi64>}
19399ff697bSNicolas Vasilache    ins(%input, %filter : memref<3x5x4xf32>, memref<2x4xf32>)
19499ff697bSNicolas Vasilache    outs(%output : memref<3x2x4xf32>)
19599ff697bSNicolas Vasilache  return
19699ff697bSNicolas Vasilache}
19799ff697bSNicolas Vasilache
198f67171acSNicolas Vasilache//       CHECK: func @depthwise_conv1d_nwc_wc_3x5x4_memref
19999ff697bSNicolas Vasilache//  CHECK-SAME:   (%[[INPUT:[0-9a-z]+]]: memref<3x5x4xf32>, %[[FILTER:[0-9a-z]+]]: memref<2x4xf32>, %[[OUTPUT:[0-9a-z]+]]: memref<3x2x4xf32>)
20099ff697bSNicolas Vasilache
20199ff697bSNicolas Vasilache//   CHECK-DAG:   %[[C0:.+]] = arith.constant 0 : index
20299ff697bSNicolas Vasilache//   CHECK-DAG:   %[[F0:.+]] = arith.constant 0.000000e+00 : f32
20399ff697bSNicolas Vasilache
20499ff697bSNicolas Vasilache/// Read the whole data in one shot.
20599ff697bSNicolas Vasilache//      CHECK:   %[[V_INPUT_R:.+]] = vector.transfer_read %[[INPUT]][%[[C0]], %[[C0]], %[[C0]]]
20699ff697bSNicolas Vasilache//      CHECK:  %[[V_FILTER_R:.+]] = vector.transfer_read %[[FILTER]][%[[C0]], %[[C0]]]
20799ff697bSNicolas Vasilache//      CHECK:  %[[V_OUTPUT_R:.+]] = vector.transfer_read %[[OUTPUT]][%[[C0]], %[[C0]], %[[C0]]]
20899ff697bSNicolas Vasilache
20999ff697bSNicolas Vasilache//      CHECK:   %[[V_INPUT_0:.+]] = vector.extract_strided_slice %[[V_INPUT_R]]
210641fe707SNicolas Vasilache// CHECK-SAME:     {offsets = [0, 0, 0], sizes = [3, 2, 4], strides = [1, 1, 1]} : vector<3x4x4xf32> to vector<3x2x4xf32>
21199ff697bSNicolas Vasilache//      CHECK:   %[[V_INPUT_1:.+]] = vector.extract_strided_slice %[[V_INPUT_R]]
212641fe707SNicolas Vasilache// CHECK-SAME:     {offsets = [0, 2, 0], sizes = [3, 2, 4], strides = [1, 1, 1]} : vector<3x4x4xf32> to vector<3x2x4xf32>
21399ff697bSNicolas Vasilache
214392e16c2SNicolas Vasilache//      CHECK:  %[[V_FILTER_0:.+]] = vector.extract %[[V_FILTER_R]][0] : vector<2x4xf32>
215392e16c2SNicolas Vasilache//      CHECK:  %[[V_FILTER_1:.+]] = vector.extract %[[V_FILTER_R]][1] : vector<2x4xf32>
216392e16c2SNicolas Vasilache
217641fe707SNicolas Vasilache/// w == 0, kw = 0
218641fe707SNicolas Vasilache//      CHECK:  %[[B_FILTER_0:.*]] = vector.broadcast %[[V_FILTER_0]] : vector<4xf32> to vector<3x2x4xf32>
219641fe707SNicolas Vasilache//      CHECK:  %[[FMA_0:.*]] = vector.fma %[[V_INPUT_0]], %[[B_FILTER_0]], %[[V_OUTPUT_R]] : vector<3x2x4xf32>
220641fe707SNicolas Vasilache
221641fe707SNicolas Vasilache/// w == 0, kw = 1
222641fe707SNicolas Vasilache//      CHECK:  %[[B_FILTER_1:.*]] = vector.broadcast %[[V_FILTER_1]] : vector<4xf32> to vector<3x2x4xf32>
223641fe707SNicolas Vasilache//      CHECK:  %[[FMA_1:.*]] = vector.fma %[[V_INPUT_1]], %[[B_FILTER_1]], %[[FMA_0]] : vector<3x2x4xf32>
22499ff697bSNicolas Vasilache
22599ff697bSNicolas Vasilache// Write the result back in one shot.
226641fe707SNicolas Vasilache//      CHECK:   vector.transfer_write %[[FMA_1]], %[[OUTPUT]][%[[C0]], %[[C0]], %[[C0]]]
227*046ebeb6SThomas Raoux
228*046ebeb6SThomas Raoux
229*046ebeb6SThomas Raoux// -----
230*046ebeb6SThomas Raoux
231*046ebeb6SThomas Raouxfunc.func @conv_1d_nwc_wcf_mixed_type_memref(%input: memref<1x2x3xf16>, %filter: memref<1x3x2xf16>, %output: memref<1x2x2xf32>) {
232*046ebeb6SThomas Raoux  linalg.conv_1d_nwc_wcf
233*046ebeb6SThomas Raoux  {dilations = dense<1> : vector<1xi64>, strides = dense<1> : vector<1xi64>}
234*046ebeb6SThomas Raoux   ins(%input, %filter : memref<1x2x3xf16>, memref<1x3x2xf16>)
235*046ebeb6SThomas Raoux   outs(%output : memref<1x2x2xf32>)
236*046ebeb6SThomas Raoux  return
237*046ebeb6SThomas Raoux}
238*046ebeb6SThomas Raoux
239*046ebeb6SThomas Raoux//       CHECK: func @conv_1d_nwc_wcf_mixed_type_memref
240*046ebeb6SThomas Raoux//  CHECK-SAME:   (%[[INPUT:[0-9a-z]+]]: memref<1x2x3xf16>, %[[FILTER:[0-9a-z]+]]: memref<1x3x2xf16>, %[[OUTPUT:[0-9a-z]+]]: memref<1x2x2xf32>)
241*046ebeb6SThomas Raoux
242*046ebeb6SThomas Raoux//   CHECK-DAG:   %[[C0:.+]] = arith.constant 0 : index
243*046ebeb6SThomas Raoux//   CHECK-DAG:   %[[F0:.+]] = arith.constant 0.000000e+00 : f32
244*046ebeb6SThomas Raoux
245*046ebeb6SThomas Raoux/// Read the whole data in one shot.
246*046ebeb6SThomas Raoux//      CHECK:   %[[V_INPUT_R:.+]] = vector.transfer_read %[[INPUT]][%[[C0]], %[[C0]], %[[C0]]]
247*046ebeb6SThomas Raoux//      CHECK:   %[[V_FILTER_R:.+]] = vector.transfer_read %[[FILTER]][%[[C0]], %[[C0]], %[[C0]]]
248*046ebeb6SThomas Raoux//      CHECK:   %[[V_OUTPUT_R:.+]] = vector.transfer_read %[[OUTPUT]][%[[C0]], %[[C0]], %[[C0]]]
249*046ebeb6SThomas Raoux//      CHECK:   %[[V_FILTER_1:.+]] = vector.extract %[[V_FILTER_R]][0] : vector<1x3x2xf16>
250*046ebeb6SThomas Raoux//      CHECK:   %[[CONT:.*]] = vector.contract
251*046ebeb6SThomas Raoux//        {{.*}} %[[V_INPUT_R]], %[[V_FILTER_1]], %[[V_OUTPUT_R]] : vector<1x2x3xf16>, vector<3x2xf16> into vector<1x2x2xf32>
252*046ebeb6SThomas Raoux//      CHECK:   vector.transfer_write %[[CONT]], %[[OUTPUT]][%[[C0]], %[[C0]], %[[C0]]]
253