1 //===- LowerGpuOpsToROCDLOps.cpp - MLIR GPU to ROCDL lowering passes ------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements a pass to generate ROCDLIR operations for higher-level 10 // GPU operations. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "mlir/Conversion/ControlFlowToLLVM/ControlFlowToLLVM.h" 15 #include "mlir/Conversion/GPUToROCDL/GPUToROCDLPass.h" 16 17 #include "mlir/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.h" 18 #include "mlir/Conversion/ArithmeticToLLVM/ArithmeticToLLVM.h" 19 #include "mlir/Conversion/FuncToLLVM/ConvertFuncToLLVM.h" 20 #include "mlir/Conversion/LLVMCommon/ConversionTarget.h" 21 #include "mlir/Conversion/LLVMCommon/LoweringOptions.h" 22 #include "mlir/Conversion/LLVMCommon/Pattern.h" 23 #include "mlir/Conversion/LLVMCommon/TypeConverter.h" 24 #include "mlir/Conversion/MemRefToLLVM/MemRefToLLVM.h" 25 #include "mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h" 26 #include "mlir/Conversion/VectorToROCDL/VectorToROCDL.h" 27 #include "mlir/Dialect/Func/IR/FuncOps.h" 28 #include "mlir/Dialect/GPU/IR/GPUDialect.h" 29 #include "mlir/Dialect/GPU/Transforms/Passes.h" 30 #include "mlir/Dialect/LLVMIR/ROCDLDialect.h" 31 #include "mlir/Dialect/Math/IR/Math.h" 32 #include "mlir/Dialect/Vector/IR/VectorOps.h" 33 #include "mlir/Pass/Pass.h" 34 #include "mlir/Transforms/DialectConversion.h" 35 #include "mlir/Transforms/GreedyPatternRewriteDriver.h" 36 #include "llvm/Support/FormatVariadic.h" 37 38 #include "../GPUCommon/GPUOpsLowering.h" 39 #include "../GPUCommon/IndexIntrinsicsOpLowering.h" 40 #include "../GPUCommon/OpToFuncCallLowering.h" 41 #include "../PassDetail.h" 42 43 using namespace mlir; 44 45 namespace { 46 47 /// Import the GPU Ops to ROCDL Patterns. 48 #include "GPUToROCDL.cpp.inc" 49 50 // A pass that replaces all occurrences of GPU device operations with their 51 // corresponding ROCDL equivalent. 52 // 53 // This pass only handles device code and is not meant to be run on GPU host 54 // code. 55 struct LowerGpuOpsToROCDLOpsPass 56 : public ConvertGpuOpsToROCDLOpsBase<LowerGpuOpsToROCDLOpsPass> { 57 LowerGpuOpsToROCDLOpsPass() = default; 58 LowerGpuOpsToROCDLOpsPass(const std::string &chipset, unsigned indexBitwidth, 59 gpu::amd::Runtime runtime) { 60 this->chipset = chipset; 61 this->indexBitwidth = indexBitwidth; 62 this->runtime = runtime; 63 } 64 65 void runOnOperation() override { 66 gpu::GPUModuleOp m = getOperation(); 67 MLIRContext *ctx = m.getContext(); 68 69 // Request C wrapper emission. 70 for (auto func : m.getOps<func::FuncOp>()) { 71 func->setAttr(LLVM::LLVMDialect::getEmitCWrapperAttrName(), 72 UnitAttr::get(ctx)); 73 } 74 75 FailureOr<amdgpu::Chipset> maybeChipset = amdgpu::Chipset::parse(chipset); 76 if (failed(maybeChipset)) { 77 emitError(UnknownLoc::get(ctx), "Invalid chipset name: " + chipset); 78 return signalPassFailure(); 79 } 80 81 /// Customize the bitwidth used for the device side index computations. 82 LowerToLLVMOptions options( 83 ctx, DataLayout(cast<DataLayoutOpInterface>(m.getOperation()))); 84 if (indexBitwidth != kDeriveIndexBitwidthFromDataLayout) 85 options.overrideIndexBitwidth(indexBitwidth); 86 LLVMTypeConverter converter(ctx, options); 87 88 RewritePatternSet patterns(ctx); 89 RewritePatternSet llvmPatterns(ctx); 90 91 populateGpuRewritePatterns(patterns); 92 (void)applyPatternsAndFoldGreedily(m, std::move(patterns)); 93 94 mlir::arith::populateArithmeticToLLVMConversionPatterns(converter, 95 llvmPatterns); 96 populateAMDGPUToROCDLConversionPatterns(converter, llvmPatterns, 97 *maybeChipset); 98 populateVectorToLLVMConversionPatterns(converter, llvmPatterns); 99 populateVectorToROCDLConversionPatterns(converter, llvmPatterns); 100 cf::populateControlFlowToLLVMConversionPatterns(converter, llvmPatterns); 101 populateFuncToLLVMConversionPatterns(converter, llvmPatterns); 102 populateMemRefToLLVMConversionPatterns(converter, llvmPatterns); 103 populateGpuToROCDLConversionPatterns(converter, llvmPatterns, runtime); 104 LLVMConversionTarget target(getContext()); 105 configureGpuToROCDLConversionLegality(target); 106 if (failed(applyPartialConversion(m, target, std::move(llvmPatterns)))) 107 signalPassFailure(); 108 } 109 }; 110 111 } // namespace 112 113 void mlir::configureGpuToROCDLConversionLegality(ConversionTarget &target) { 114 target.addIllegalOp<func::FuncOp>(); 115 target.addLegalDialect<::mlir::LLVM::LLVMDialect>(); 116 target.addLegalDialect<ROCDL::ROCDLDialect>(); 117 target.addIllegalDialect<gpu::GPUDialect>(); 118 target.addIllegalOp<LLVM::CosOp, LLVM::ExpOp, LLVM::Exp2Op, LLVM::FAbsOp, 119 LLVM::FCeilOp, LLVM::FFloorOp, LLVM::LogOp, LLVM::Log10Op, 120 LLVM::Log2Op, LLVM::PowOp, LLVM::SinOp, LLVM::SqrtOp>(); 121 122 // TODO: Remove once we support replacing non-root ops. 123 target.addLegalOp<gpu::YieldOp, gpu::GPUModuleOp, gpu::ModuleEndOp>(); 124 } 125 126 void mlir::populateGpuToROCDLConversionPatterns( 127 LLVMTypeConverter &converter, RewritePatternSet &patterns, 128 mlir::gpu::amd::Runtime runtime) { 129 using mlir::gpu::amd::Runtime; 130 131 populateWithGenerated(patterns); 132 patterns 133 .add<GPUIndexIntrinsicOpLowering<gpu::ThreadIdOp, ROCDL::ThreadIdXOp, 134 ROCDL::ThreadIdYOp, ROCDL::ThreadIdZOp>, 135 GPUIndexIntrinsicOpLowering<gpu::BlockDimOp, ROCDL::BlockDimXOp, 136 ROCDL::BlockDimYOp, ROCDL::BlockDimZOp>, 137 GPUIndexIntrinsicOpLowering<gpu::BlockIdOp, ROCDL::BlockIdXOp, 138 ROCDL::BlockIdYOp, ROCDL::BlockIdZOp>, 139 GPUIndexIntrinsicOpLowering<gpu::GridDimOp, ROCDL::GridDimXOp, 140 ROCDL::GridDimYOp, ROCDL::GridDimZOp>, 141 GPUReturnOpLowering>(converter); 142 patterns.add<GPUFuncOpLowering>( 143 converter, /*allocaAddrSpace=*/5, 144 StringAttr::get(&converter.getContext(), 145 ROCDL::ROCDLDialect::getKernelFuncAttrName())); 146 if (Runtime::HIP == runtime) { 147 patterns.add<GPUPrintfOpToHIPLowering>(converter); 148 } else if (Runtime::OpenCL == runtime) { 149 // Use address space = 4 to match the OpenCL definition of printf() 150 patterns.add<GPUPrintfOpToLLVMCallLowering>(converter, /*addressSpace=*/4); 151 } 152 153 patterns.add<OpToFuncCallLowering<math::AbsOp>>(converter, "__ocml_fabs_f32", 154 "__ocml_fabs_f64"); 155 patterns.add<OpToFuncCallLowering<math::AtanOp>>(converter, "__ocml_atan_f32", 156 "__ocml_atan_f64"); 157 patterns.add<OpToFuncCallLowering<math::Atan2Op>>( 158 converter, "__ocml_atan2_f32", "__ocml_atan2_f64"); 159 patterns.add<OpToFuncCallLowering<math::CeilOp>>(converter, "__ocml_ceil_f32", 160 "__ocml_ceil_f64"); 161 patterns.add<OpToFuncCallLowering<math::CosOp>>(converter, "__ocml_cos_f32", 162 "__ocml_cos_f64"); 163 patterns.add<OpToFuncCallLowering<math::ExpOp>>(converter, "__ocml_exp_f32", 164 "__ocml_exp_f64"); 165 patterns.add<OpToFuncCallLowering<math::Exp2Op>>(converter, "__ocml_exp2_f32", 166 "__ocml_exp2_f64"); 167 patterns.add<OpToFuncCallLowering<math::ExpM1Op>>( 168 converter, "__ocml_expm1_f32", "__ocml_expm1_f64"); 169 patterns.add<OpToFuncCallLowering<math::FloorOp>>( 170 converter, "__ocml_floor_f32", "__ocml_floor_f64"); 171 patterns.add<OpToFuncCallLowering<math::LogOp>>(converter, "__ocml_log_f32", 172 "__ocml_log_f64"); 173 patterns.add<OpToFuncCallLowering<math::Log10Op>>( 174 converter, "__ocml_log10_f32", "__ocml_log10_f64"); 175 patterns.add<OpToFuncCallLowering<math::Log1pOp>>( 176 converter, "__ocml_log1p_f32", "__ocml_log1p_f64"); 177 patterns.add<OpToFuncCallLowering<math::Log2Op>>(converter, "__ocml_log2_f32", 178 "__ocml_log2_f64"); 179 patterns.add<OpToFuncCallLowering<math::PowFOp>>(converter, "__ocml_pow_f32", 180 "__ocml_pow_f64"); 181 patterns.add<OpToFuncCallLowering<math::RsqrtOp>>( 182 converter, "__ocml_rsqrt_f32", "__ocml_rsqrt_f64"); 183 patterns.add<OpToFuncCallLowering<math::SinOp>>(converter, "__ocml_sin_f32", 184 "__ocml_sin_f64"); 185 patterns.add<OpToFuncCallLowering<math::SqrtOp>>(converter, "__ocml_sqrt_f32", 186 "__ocml_sqrt_f64"); 187 patterns.add<OpToFuncCallLowering<math::TanhOp>>(converter, "__ocml_tanh_f32", 188 "__ocml_tanh_f64"); 189 } 190 191 std::unique_ptr<OperationPass<gpu::GPUModuleOp>> 192 mlir::createLowerGpuOpsToROCDLOpsPass(const std::string &chipset, 193 unsigned indexBitwidth, 194 gpu::amd::Runtime runtime) { 195 return std::make_unique<LowerGpuOpsToROCDLOpsPass>(chipset, indexBitwidth, 196 runtime); 197 } 198