1 //===- LowerGpuOpsToROCDLOps.cpp - MLIR GPU to ROCDL lowering passes ------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements a pass to generate ROCDLIR operations for higher-level 10 // GPU operations. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "mlir/Conversion/ControlFlowToLLVM/ControlFlowToLLVM.h" 15 #include "mlir/Conversion/GPUToROCDL/GPUToROCDLPass.h" 16 17 #include "mlir/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.h" 18 #include "mlir/Conversion/ArithmeticToLLVM/ArithmeticToLLVM.h" 19 #include "mlir/Conversion/FuncToLLVM/ConvertFuncToLLVM.h" 20 #include "mlir/Conversion/LLVMCommon/ConversionTarget.h" 21 #include "mlir/Conversion/LLVMCommon/LoweringOptions.h" 22 #include "mlir/Conversion/LLVMCommon/Pattern.h" 23 #include "mlir/Conversion/LLVMCommon/TypeConverter.h" 24 #include "mlir/Conversion/MemRefToLLVM/MemRefToLLVM.h" 25 #include "mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h" 26 #include "mlir/Conversion/VectorToROCDL/VectorToROCDL.h" 27 #include "mlir/Dialect/Func/IR/FuncOps.h" 28 #include "mlir/Dialect/GPU/IR/GPUDialect.h" 29 #include "mlir/Dialect/GPU/Transforms/Passes.h" 30 #include "mlir/Dialect/LLVMIR/ROCDLDialect.h" 31 #include "mlir/Dialect/Math/IR/Math.h" 32 #include "mlir/Dialect/Vector/IR/VectorOps.h" 33 #include "mlir/Pass/Pass.h" 34 #include "mlir/Transforms/DialectConversion.h" 35 #include "mlir/Transforms/GreedyPatternRewriteDriver.h" 36 #include "llvm/Support/FormatVariadic.h" 37 38 #include "../GPUCommon/GPUOpsLowering.h" 39 #include "../GPUCommon/IndexIntrinsicsOpLowering.h" 40 #include "../GPUCommon/OpToFuncCallLowering.h" 41 #include "../PassDetail.h" 42 43 using namespace mlir; 44 45 namespace { 46 47 /// Import the GPU Ops to ROCDL Patterns. 48 #include "GPUToROCDL.cpp.inc" 49 50 // A pass that replaces all occurrences of GPU device operations with their 51 // corresponding ROCDL equivalent. 52 // 53 // This pass only handles device code and is not meant to be run on GPU host 54 // code. 55 struct LowerGpuOpsToROCDLOpsPass 56 : public ConvertGpuOpsToROCDLOpsBase<LowerGpuOpsToROCDLOpsPass> { 57 LowerGpuOpsToROCDLOpsPass() = default; 58 LowerGpuOpsToROCDLOpsPass(unsigned indexBitwidth, gpu::amd::Runtime runtime) { 59 this->indexBitwidth = indexBitwidth; 60 this->runtime = runtime; 61 } 62 63 void runOnOperation() override { 64 gpu::GPUModuleOp m = getOperation(); 65 66 /// Customize the bitwidth used for the device side index computations. 67 LowerToLLVMOptions options( 68 m.getContext(), 69 DataLayout(cast<DataLayoutOpInterface>(m.getOperation()))); 70 options.emitCWrappers = true; 71 if (indexBitwidth != kDeriveIndexBitwidthFromDataLayout) 72 options.overrideIndexBitwidth(indexBitwidth); 73 LLVMTypeConverter converter(m.getContext(), options); 74 75 RewritePatternSet patterns(m.getContext()); 76 RewritePatternSet llvmPatterns(m.getContext()); 77 78 populateGpuRewritePatterns(patterns); 79 (void)applyPatternsAndFoldGreedily(m, std::move(patterns)); 80 81 mlir::arith::populateArithmeticToLLVMConversionPatterns(converter, 82 llvmPatterns); 83 populateAMDGPUToROCDLConversionPatterns(converter, llvmPatterns); 84 populateVectorToLLVMConversionPatterns(converter, llvmPatterns); 85 populateVectorToROCDLConversionPatterns(converter, llvmPatterns); 86 cf::populateControlFlowToLLVMConversionPatterns(converter, llvmPatterns); 87 populateFuncToLLVMConversionPatterns(converter, llvmPatterns); 88 populateMemRefToLLVMConversionPatterns(converter, llvmPatterns); 89 populateGpuToROCDLConversionPatterns(converter, llvmPatterns, runtime); 90 LLVMConversionTarget target(getContext()); 91 configureGpuToROCDLConversionLegality(target); 92 if (failed(applyPartialConversion(m, target, std::move(llvmPatterns)))) 93 signalPassFailure(); 94 } 95 }; 96 97 } // namespace 98 99 void mlir::configureGpuToROCDLConversionLegality(ConversionTarget &target) { 100 target.addIllegalOp<func::FuncOp>(); 101 target.addLegalDialect<::mlir::LLVM::LLVMDialect>(); 102 target.addLegalDialect<ROCDL::ROCDLDialect>(); 103 target.addIllegalDialect<gpu::GPUDialect>(); 104 target.addIllegalOp<LLVM::CosOp, LLVM::ExpOp, LLVM::Exp2Op, LLVM::FAbsOp, 105 LLVM::FCeilOp, LLVM::FFloorOp, LLVM::LogOp, LLVM::Log10Op, 106 LLVM::Log2Op, LLVM::PowOp, LLVM::SinOp, LLVM::SqrtOp>(); 107 108 // TODO: Remove once we support replacing non-root ops. 109 target.addLegalOp<gpu::YieldOp, gpu::GPUModuleOp, gpu::ModuleEndOp>(); 110 } 111 112 void mlir::populateGpuToROCDLConversionPatterns( 113 LLVMTypeConverter &converter, RewritePatternSet &patterns, 114 mlir::gpu::amd::Runtime runtime) { 115 using mlir::gpu::amd::Runtime; 116 117 populateWithGenerated(patterns); 118 patterns 119 .add<GPUIndexIntrinsicOpLowering<gpu::ThreadIdOp, ROCDL::ThreadIdXOp, 120 ROCDL::ThreadIdYOp, ROCDL::ThreadIdZOp>, 121 GPUIndexIntrinsicOpLowering<gpu::BlockDimOp, ROCDL::BlockDimXOp, 122 ROCDL::BlockDimYOp, ROCDL::BlockDimZOp>, 123 GPUIndexIntrinsicOpLowering<gpu::BlockIdOp, ROCDL::BlockIdXOp, 124 ROCDL::BlockIdYOp, ROCDL::BlockIdZOp>, 125 GPUIndexIntrinsicOpLowering<gpu::GridDimOp, ROCDL::GridDimXOp, 126 ROCDL::GridDimYOp, ROCDL::GridDimZOp>, 127 GPUReturnOpLowering>(converter); 128 patterns.add<GPUFuncOpLowering>( 129 converter, /*allocaAddrSpace=*/5, 130 StringAttr::get(&converter.getContext(), 131 ROCDL::ROCDLDialect::getKernelFuncAttrName())); 132 if (Runtime::HIP == runtime) { 133 patterns.add<GPUPrintfOpToHIPLowering>(converter); 134 } else if (Runtime::OpenCL == runtime) { 135 // Use address space = 4 to match the OpenCL definition of printf() 136 patterns.add<GPUPrintfOpToLLVMCallLowering>(converter, /*addressSpace=*/4); 137 } 138 139 patterns.add<OpToFuncCallLowering<math::AbsOp>>(converter, "__ocml_fabs_f32", 140 "__ocml_fabs_f64"); 141 patterns.add<OpToFuncCallLowering<math::AtanOp>>(converter, "__ocml_atan_f32", 142 "__ocml_atan_f64"); 143 patterns.add<OpToFuncCallLowering<math::Atan2Op>>( 144 converter, "__ocml_atan2_f32", "__ocml_atan2_f64"); 145 patterns.add<OpToFuncCallLowering<math::CeilOp>>(converter, "__ocml_ceil_f32", 146 "__ocml_ceil_f64"); 147 patterns.add<OpToFuncCallLowering<math::CosOp>>(converter, "__ocml_cos_f32", 148 "__ocml_cos_f64"); 149 patterns.add<OpToFuncCallLowering<math::ExpOp>>(converter, "__ocml_exp_f32", 150 "__ocml_exp_f64"); 151 patterns.add<OpToFuncCallLowering<math::Exp2Op>>(converter, "__ocml_exp2_f32", 152 "__ocml_exp2_f64"); 153 patterns.add<OpToFuncCallLowering<math::ExpM1Op>>( 154 converter, "__ocml_expm1_f32", "__ocml_expm1_f64"); 155 patterns.add<OpToFuncCallLowering<math::FloorOp>>( 156 converter, "__ocml_floor_f32", "__ocml_floor_f64"); 157 patterns.add<OpToFuncCallLowering<math::LogOp>>(converter, "__ocml_log_f32", 158 "__ocml_log_f64"); 159 patterns.add<OpToFuncCallLowering<math::Log10Op>>( 160 converter, "__ocml_log10_f32", "__ocml_log10_f64"); 161 patterns.add<OpToFuncCallLowering<math::Log1pOp>>( 162 converter, "__ocml_log1p_f32", "__ocml_log1p_f64"); 163 patterns.add<OpToFuncCallLowering<math::Log2Op>>(converter, "__ocml_log2_f32", 164 "__ocml_log2_f64"); 165 patterns.add<OpToFuncCallLowering<math::PowFOp>>(converter, "__ocml_pow_f32", 166 "__ocml_pow_f64"); 167 patterns.add<OpToFuncCallLowering<math::RsqrtOp>>( 168 converter, "__ocml_rsqrt_f32", "__ocml_rsqrt_f64"); 169 patterns.add<OpToFuncCallLowering<math::SinOp>>(converter, "__ocml_sin_f32", 170 "__ocml_sin_f64"); 171 patterns.add<OpToFuncCallLowering<math::SqrtOp>>(converter, "__ocml_sqrt_f32", 172 "__ocml_sqrt_f64"); 173 patterns.add<OpToFuncCallLowering<math::TanhOp>>(converter, "__ocml_tanh_f32", 174 "__ocml_tanh_f64"); 175 } 176 177 std::unique_ptr<OperationPass<gpu::GPUModuleOp>> 178 mlir::createLowerGpuOpsToROCDLOpsPass(unsigned indexBitwidth, 179 gpu::amd::Runtime runtime) { 180 return std::make_unique<LowerGpuOpsToROCDLOpsPass>(indexBitwidth, runtime); 181 } 182