1 //===- LowerGpuOpsToROCDLOps.cpp - MLIR GPU to ROCDL lowering passes ------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements a pass to generate ROCDLIR operations for higher-level
10 // GPU operations.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "mlir/Conversion/GPUToROCDL/GPUToROCDLPass.h"
15 
16 #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h"
17 #include "mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h"
18 #include "mlir/Conversion/VectorToROCDL/VectorToROCDL.h"
19 #include "mlir/Dialect/GPU/GPUDialect.h"
20 #include "mlir/Dialect/GPU/Passes.h"
21 #include "mlir/Dialect/LLVMIR/ROCDLDialect.h"
22 #include "mlir/Dialect/Vector/VectorOps.h"
23 #include "mlir/Pass/Pass.h"
24 #include "mlir/Transforms/DialectConversion.h"
25 #include "llvm/Support/FormatVariadic.h"
26 
27 #include "../GPUCommon/GPUOpsLowering.h"
28 #include "../GPUCommon/IndexIntrinsicsOpLowering.h"
29 #include "../GPUCommon/OpToFuncCallLowering.h"
30 #include "../PassDetail.h"
31 
32 using namespace mlir;
33 
34 namespace {
35 
36 /// Import the GPU Ops to ROCDL Patterns.
37 #include "GPUToROCDL.cpp.inc"
38 
39 // A pass that replaces all occurrences of GPU device operations with their
40 // corresponding ROCDL equivalent.
41 //
42 // This pass only handles device code and is not meant to be run on GPU host
43 // code.
44 class LowerGpuOpsToROCDLOpsPass
45     : public ConvertGpuOpsToROCDLOpsBase<LowerGpuOpsToROCDLOpsPass> {
46 public:
47   void runOnOperation() override {
48     gpu::GPUModuleOp m = getOperation();
49 
50     LLVMTypeConverter converter(m.getContext());
51 
52     OwningRewritePatternList patterns;
53 
54     populateGpuRewritePatterns(m.getContext(), patterns);
55     applyPatternsAndFoldGreedily(m, patterns);
56     patterns.clear();
57 
58     populateVectorToLLVMConversionPatterns(converter, patterns);
59     populateVectorToROCDLConversionPatterns(converter, patterns);
60     populateStdToLLVMConversionPatterns(converter, patterns);
61     populateGpuToROCDLConversionPatterns(converter, patterns);
62     LLVMConversionTarget target(getContext());
63     target.addIllegalDialect<gpu::GPUDialect>();
64     target.addIllegalOp<LLVM::CosOp, LLVM::ExpOp, LLVM::FAbsOp, LLVM::FCeilOp,
65                         LLVM::LogOp, LLVM::Log10Op, LLVM::Log2Op>();
66     target.addIllegalOp<FuncOp>();
67     target.addLegalDialect<ROCDL::ROCDLDialect>();
68     // TODO(whchung): Remove once we support replacing non-root ops.
69     target.addLegalOp<gpu::YieldOp, gpu::GPUModuleOp, gpu::ModuleEndOp>();
70     if (failed(applyPartialConversion(m, target, patterns)))
71       signalPassFailure();
72   }
73 };
74 
75 } // anonymous namespace
76 
77 void mlir::populateGpuToROCDLConversionPatterns(
78     LLVMTypeConverter &converter, OwningRewritePatternList &patterns) {
79   populateWithGenerated(converter.getDialect()->getContext(), &patterns);
80   patterns.insert<
81       GPUIndexIntrinsicOpLowering<gpu::ThreadIdOp, ROCDL::ThreadIdXOp,
82                                   ROCDL::ThreadIdYOp, ROCDL::ThreadIdZOp>,
83       GPUIndexIntrinsicOpLowering<gpu::BlockDimOp, ROCDL::BlockDimXOp,
84                                   ROCDL::BlockDimYOp, ROCDL::BlockDimZOp>,
85       GPUIndexIntrinsicOpLowering<gpu::BlockIdOp, ROCDL::BlockIdXOp,
86                                   ROCDL::BlockIdYOp, ROCDL::BlockIdZOp>,
87       GPUIndexIntrinsicOpLowering<gpu::GridDimOp, ROCDL::GridDimXOp,
88                                   ROCDL::GridDimYOp, ROCDL::GridDimZOp>,
89       GPUFuncOpLowering<5>, GPUReturnOpLowering>(converter);
90   patterns.insert<OpToFuncCallLowering<AbsFOp>>(converter, "__ocml_fabs_f32",
91                                                 "__ocml_fabs_f64");
92   patterns.insert<OpToFuncCallLowering<CeilFOp>>(converter, "__ocml_ceil_f32",
93                                                  "__ocml_ceil_f64");
94   patterns.insert<OpToFuncCallLowering<CosOp>>(converter, "__ocml_cos_f32",
95                                                "__ocml_cos_f64");
96   patterns.insert<OpToFuncCallLowering<ExpOp>>(converter, "__ocml_exp_f32",
97                                                "__ocml_exp_f64");
98   patterns.insert<OpToFuncCallLowering<LogOp>>(converter, "__ocml_log_f32",
99                                                "__ocml_log_f64");
100   patterns.insert<OpToFuncCallLowering<Log10Op>>(converter, "__ocml_log10_f32",
101                                                  "__ocml_log10_f64");
102   patterns.insert<OpToFuncCallLowering<Log2Op>>(converter, "__ocml_log2_f32",
103                                                 "__ocml_log2_f64");
104   patterns.insert<OpToFuncCallLowering<TanhOp>>(converter, "__ocml_tanh_f32",
105                                                 "__ocml_tanh_f64");
106 }
107 
108 std::unique_ptr<OperationPass<gpu::GPUModuleOp>>
109 mlir::createLowerGpuOpsToROCDLOpsPass() {
110   return std::make_unique<LowerGpuOpsToROCDLOpsPass>();
111 }
112