1 //===- LowerGpuOpsToROCDLOps.cpp - MLIR GPU to ROCDL lowering passes ------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements a pass to generate ROCDLIR operations for higher-level 10 // GPU operations. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "mlir/Conversion/GPUToROCDL/GPUToROCDLPass.h" 15 16 #include "mlir/Conversion/LLVMCommon/LoweringOptions.h" 17 #include "mlir/Conversion/LLVMCommon/TypeConverter.h" 18 #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h" 19 #include "mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h" 20 #include "mlir/Conversion/VectorToROCDL/VectorToROCDL.h" 21 #include "mlir/Dialect/GPU/GPUDialect.h" 22 #include "mlir/Dialect/GPU/Passes.h" 23 #include "mlir/Dialect/LLVMIR/ROCDLDialect.h" 24 #include "mlir/Dialect/Math/IR/Math.h" 25 #include "mlir/Dialect/Vector/VectorOps.h" 26 #include "mlir/Pass/Pass.h" 27 #include "mlir/Transforms/DialectConversion.h" 28 #include "mlir/Transforms/GreedyPatternRewriteDriver.h" 29 #include "llvm/Support/FormatVariadic.h" 30 31 #include "../GPUCommon/GPUOpsLowering.h" 32 #include "../GPUCommon/IndexIntrinsicsOpLowering.h" 33 #include "../GPUCommon/OpToFuncCallLowering.h" 34 #include "../PassDetail.h" 35 36 using namespace mlir; 37 38 namespace { 39 40 /// Import the GPU Ops to ROCDL Patterns. 41 #include "GPUToROCDL.cpp.inc" 42 43 // A pass that replaces all occurrences of GPU device operations with their 44 // corresponding ROCDL equivalent. 45 // 46 // This pass only handles device code and is not meant to be run on GPU host 47 // code. 48 struct LowerGpuOpsToROCDLOpsPass 49 : public ConvertGpuOpsToROCDLOpsBase<LowerGpuOpsToROCDLOpsPass> { 50 LowerGpuOpsToROCDLOpsPass() = default; 51 LowerGpuOpsToROCDLOpsPass(unsigned indexBitwidth) { 52 this->indexBitwidth = indexBitwidth; 53 } 54 55 void runOnOperation() override { 56 gpu::GPUModuleOp m = getOperation(); 57 58 /// Customize the bitwidth used for the device side index computations. 59 LowerToLLVMOptions options( 60 m.getContext(), 61 DataLayout(cast<DataLayoutOpInterface>(m.getOperation()))); 62 options.emitCWrappers = true; 63 if (indexBitwidth != kDeriveIndexBitwidthFromDataLayout) 64 options.overrideIndexBitwidth(indexBitwidth); 65 LLVMTypeConverter converter(m.getContext(), options); 66 67 RewritePatternSet patterns(m.getContext()); 68 RewritePatternSet llvmPatterns(m.getContext()); 69 70 populateGpuRewritePatterns(patterns); 71 (void)applyPatternsAndFoldGreedily(m, std::move(patterns)); 72 73 populateVectorToLLVMConversionPatterns(converter, llvmPatterns); 74 populateVectorToROCDLConversionPatterns(converter, llvmPatterns); 75 populateStdToLLVMConversionPatterns(converter, llvmPatterns); 76 populateGpuToROCDLConversionPatterns(converter, llvmPatterns); 77 LLVMConversionTarget target(getContext()); 78 configureGpuToROCDLConversionLegality(target); 79 if (failed(applyPartialConversion(m, target, std::move(llvmPatterns)))) 80 signalPassFailure(); 81 } 82 }; 83 84 } // anonymous namespace 85 86 void mlir::configureGpuToROCDLConversionLegality(ConversionTarget &target) { 87 target.addIllegalOp<FuncOp>(); 88 target.addLegalDialect<::mlir::LLVM::LLVMDialect>(); 89 target.addLegalDialect<ROCDL::ROCDLDialect>(); 90 target.addIllegalDialect<gpu::GPUDialect>(); 91 target.addIllegalOp<LLVM::CosOp, LLVM::ExpOp, LLVM::FAbsOp, LLVM::FCeilOp, 92 LLVM::FFloorOp, LLVM::LogOp, LLVM::Log10Op, LLVM::Log2Op, 93 LLVM::PowOp, LLVM::SinOp, LLVM::SqrtOp>(); 94 95 // TODO: Remove once we support replacing non-root ops. 96 target.addLegalOp<gpu::YieldOp, gpu::GPUModuleOp, gpu::ModuleEndOp>(); 97 } 98 99 void mlir::populateGpuToROCDLConversionPatterns(LLVMTypeConverter &converter, 100 RewritePatternSet &patterns) { 101 populateWithGenerated(patterns); 102 patterns 103 .add<GPUIndexIntrinsicOpLowering<gpu::ThreadIdOp, ROCDL::ThreadIdXOp, 104 ROCDL::ThreadIdYOp, ROCDL::ThreadIdZOp>, 105 GPUIndexIntrinsicOpLowering<gpu::BlockDimOp, ROCDL::BlockDimXOp, 106 ROCDL::BlockDimYOp, ROCDL::BlockDimZOp>, 107 GPUIndexIntrinsicOpLowering<gpu::BlockIdOp, ROCDL::BlockIdXOp, 108 ROCDL::BlockIdYOp, ROCDL::BlockIdZOp>, 109 GPUIndexIntrinsicOpLowering<gpu::GridDimOp, ROCDL::GridDimXOp, 110 ROCDL::GridDimYOp, ROCDL::GridDimZOp>, 111 GPUReturnOpLowering>(converter); 112 patterns.add<GPUFuncOpLowering>( 113 converter, /*allocaAddrSpace=*/5, 114 Identifier::get(ROCDL::ROCDLDialect::getKernelFuncAttrName(), 115 &converter.getContext())); 116 patterns.add<OpToFuncCallLowering<AbsFOp>>(converter, "__ocml_fabs_f32", 117 "__ocml_fabs_f64"); 118 patterns.add<OpToFuncCallLowering<math::AtanOp>>(converter, "__ocml_atan_f32", 119 "__ocml_atan_f64"); 120 patterns.add<OpToFuncCallLowering<math::Atan2Op>>( 121 converter, "__ocml_atan2_f32", "__ocml_atan2_f64"); 122 patterns.add<OpToFuncCallLowering<CeilFOp>>(converter, "__ocml_ceil_f32", 123 "__ocml_ceil_f64"); 124 patterns.add<OpToFuncCallLowering<math::CosOp>>(converter, "__ocml_cos_f32", 125 "__ocml_cos_f64"); 126 patterns.add<OpToFuncCallLowering<math::ExpOp>>(converter, "__ocml_exp_f32", 127 "__ocml_exp_f64"); 128 patterns.add<OpToFuncCallLowering<math::ExpM1Op>>( 129 converter, "__ocml_expm1_f32", "__ocml_expm1_f64"); 130 patterns.add<OpToFuncCallLowering<FloorFOp>>(converter, "__ocml_floor_f32", 131 "__ocml_floor_f64"); 132 patterns.add<OpToFuncCallLowering<math::LogOp>>(converter, "__ocml_log_f32", 133 "__ocml_log_f64"); 134 patterns.add<OpToFuncCallLowering<math::Log10Op>>( 135 converter, "__ocml_log10_f32", "__ocml_log10_f64"); 136 patterns.add<OpToFuncCallLowering<math::Log1pOp>>( 137 converter, "__ocml_log1p_f32", "__ocml_log1p_f64"); 138 patterns.add<OpToFuncCallLowering<math::Log2Op>>(converter, "__ocml_log2_f32", 139 "__ocml_log2_f64"); 140 patterns.add<OpToFuncCallLowering<math::PowFOp>>(converter, "__ocml_pow_f32", 141 "__ocml_pow_f64"); 142 patterns.add<OpToFuncCallLowering<math::RsqrtOp>>( 143 converter, "__ocml_rsqrt_f32", "__ocml_rsqrt_f64"); 144 patterns.add<OpToFuncCallLowering<math::SinOp>>(converter, "__ocml_sin_f32", 145 "__ocml_sin_f64"); 146 patterns.add<OpToFuncCallLowering<math::SqrtOp>>(converter, "__ocml_sqrt_f32", 147 "__ocml_sqrt_f64"); 148 patterns.add<OpToFuncCallLowering<math::TanhOp>>(converter, "__ocml_tanh_f32", 149 "__ocml_tanh_f64"); 150 } 151 152 std::unique_ptr<OperationPass<gpu::GPUModuleOp>> 153 mlir::createLowerGpuOpsToROCDLOpsPass(unsigned indexBitwidth) { 154 return std::make_unique<LowerGpuOpsToROCDLOpsPass>(indexBitwidth); 155 } 156