1 //===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler Emitter. 11 // It contains the interface of a single recognizable instruction. 12 // Documentation for the disassembler emitter in general can be found in 13 // X86DisasemblerEmitter.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #ifndef LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H 18 #define LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H 19 20 #include "CodeGenTarget.h" 21 #include "X86DisassemblerTables.h" 22 #include "llvm/ADT/SmallVector.h" 23 #include "llvm/Support/DataTypes.h" 24 #include "llvm/TableGen/Record.h" 25 26 namespace llvm { 27 28 namespace X86Disassembler { 29 30 /// RecognizableInstr - Encapsulates all information required to decode a single 31 /// instruction, as extracted from the LLVM instruction tables. Has methods 32 /// to interpret the information available in the LLVM tables, and to emit the 33 /// instruction into DisassemblerTables. 34 class RecognizableInstr { 35 private: 36 /// The opcode of the instruction, as used in an MCInst 37 InstrUID UID; 38 /// The record from the .td files corresponding to this instruction 39 const Record* Rec; 40 /// The OpPrefix field from the record 41 uint8_t OpPrefix; 42 /// The OpMap field from the record 43 uint8_t OpMap; 44 /// The opcode field from the record; this is the opcode used in the Intel 45 /// encoding and therefore distinct from the UID 46 uint8_t Opcode; 47 /// The form field from the record 48 uint8_t Form; 49 // The encoding field from the record 50 uint8_t Encoding; 51 /// The OpSize field from the record 52 uint8_t OpSize; 53 /// The AdSize field from the record 54 uint8_t AdSize; 55 /// The hasREX_WPrefix field from the record 56 bool HasREX_WPrefix; 57 /// The hasVEX_4V field from the record 58 bool HasVEX_4V; 59 /// The hasVEX_4VOp3 field from the record 60 bool HasVEX_4VOp3; 61 /// The hasVEX_WPrefix field from the record 62 bool HasVEX_WPrefix; 63 /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set 64 bool HasVEX_LPrefix; 65 /// The hasMemOp4Prefix field from the record 66 bool HasMemOp4Prefix; 67 /// The ignoreVEX_L field from the record 68 bool IgnoresVEX_L; 69 /// The hasEVEX_L2Prefix field from the record 70 bool HasEVEX_L2Prefix; 71 /// The hasEVEX_K field from the record 72 bool HasEVEX_K; 73 /// The hasEVEX_KZ field from the record 74 bool HasEVEX_KZ; 75 /// The hasEVEX_B field from the record 76 bool HasEVEX_B; 77 /// The isCodeGenOnly field from the record 78 bool IsCodeGenOnly; 79 /// The ForceDisassemble field from the record 80 bool ForceDisassemble; 81 // The CD8_Scale field from the record 82 uint8_t CD8_Scale; 83 // Whether the instruction has the predicate "In64BitMode" 84 bool Is64Bit; 85 // Whether the instruction has the predicate "In32BitMode" 86 bool Is32Bit; 87 88 /// The instruction name as listed in the tables 89 std::string Name; 90 91 /// Indicates whether the instruction should be emitted into the decode 92 /// tables; regardless, it will be emitted into the instruction info table 93 bool ShouldBeEmitted; 94 95 /// The operands of the instruction, as listed in the CodeGenInstruction. 96 /// They are not one-to-one with operands listed in the MCInst; for example, 97 /// memory operands expand to 5 operands in the MCInst 98 const std::vector<CGIOperandList::OperandInfo>* Operands; 99 100 /// The description of the instruction that is emitted into the instruction 101 /// info table 102 InstructionSpecifier* Spec; 103 104 /// insnContext - Returns the primary context in which the instruction is 105 /// valid. 106 /// 107 /// @return - The context in which the instruction is valid. 108 InstructionContext insnContext() const; 109 110 /// typeFromString - Translates an operand type from the string provided in 111 /// the LLVM tables to an OperandType for use in the operand specifier. 112 /// 113 /// @param s - The string, as extracted by calling Rec->getName() 114 /// on a CodeGenInstruction::OperandInfo. 115 /// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W 116 /// prefix. If it does, 32-bit register operands stay 117 /// 32-bit regardless of the operand size. 118 /// @param OpSize Indicates the operand size of the instruction. 119 /// If register size does not match OpSize, then 120 /// register sizes keep their size. 121 /// @return - The operand's type. 122 static OperandType typeFromString(const std::string& s, 123 bool hasREX_WPrefix, uint8_t OpSize); 124 125 /// immediateEncodingFromString - Translates an immediate encoding from the 126 /// string provided in the LLVM tables to an OperandEncoding for use in 127 /// the operand specifier. 128 /// 129 /// @param s - See typeFromString(). 130 /// @param OpSize - Indicates whether this is an OpSize16 instruction. 131 /// If it is not, then 16-bit immediate operands stay 16-bit. 132 /// @return - The operand's encoding. 133 static OperandEncoding immediateEncodingFromString(const std::string &s, 134 uint8_t OpSize); 135 136 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but 137 /// handles operands that are in the REG field of the ModR/M byte. 138 static OperandEncoding rmRegisterEncodingFromString(const std::string &s, 139 uint8_t OpSize); 140 141 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but 142 /// handles operands that are in the REG field of the ModR/M byte. 143 static OperandEncoding roRegisterEncodingFromString(const std::string &s, 144 uint8_t OpSize); 145 static OperandEncoding memoryEncodingFromString(const std::string &s, 146 uint8_t OpSize); 147 static OperandEncoding relocationEncodingFromString(const std::string &s, 148 uint8_t OpSize); 149 static OperandEncoding opcodeModifierEncodingFromString(const std::string &s, 150 uint8_t OpSize); 151 static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s, 152 uint8_t OpSize); 153 static OperandEncoding writemaskRegisterEncodingFromString(const std::string &s, 154 uint8_t OpSize); 155 156 /// \brief Adjust the encoding type for an operand based on the instruction. 157 void adjustOperandEncoding(OperandEncoding &encoding); 158 159 /// handleOperand - Converts a single operand from the LLVM table format to 160 /// the emitted table format, handling any duplicate operands it encounters 161 /// and then one non-duplicate. 162 /// 163 /// @param optional - Determines whether to assert that the 164 /// operand exists. 165 /// @param operandIndex - The index into the generated operand table. 166 /// Incremented by this function one or more 167 /// times to reflect possible duplicate 168 /// operands). 169 /// @param physicalOperandIndex - The index of the current operand into the 170 /// set of non-duplicate ('physical') operands. 171 /// Incremented by this function once. 172 /// @param numPhysicalOperands - The number of non-duplicate operands in the 173 /// instructions. 174 /// @param operandMapping - The operand mapping, which has an entry for 175 /// each operand that indicates whether it is a 176 /// duplicate, and of what. 177 void handleOperand(bool optional, 178 unsigned &operandIndex, 179 unsigned &physicalOperandIndex, 180 unsigned numPhysicalOperands, 181 const unsigned *operandMapping, 182 OperandEncoding (*encodingFromString) 183 (const std::string&, 184 uint8_t OpSize)); 185 186 /// shouldBeEmitted - Returns the shouldBeEmitted field. Although filter() 187 /// filters out many instructions, at various points in decoding we 188 /// determine that the instruction should not actually be decodable. In 189 /// particular, MMX MOV instructions aren't emitted, but they're only 190 /// identified during operand parsing. 191 /// 192 /// @return - true if at this point we believe the instruction should be 193 /// emitted; false if not. This will return false if filter() returns false 194 /// once emitInstructionSpecifier() has been called. 195 bool shouldBeEmitted() const { 196 return ShouldBeEmitted; 197 } 198 199 /// emitInstructionSpecifier - Loads the instruction specifier for the current 200 /// instruction into a DisassemblerTables. 201 /// 202 void emitInstructionSpecifier(); 203 204 /// emitDecodePath - Populates the proper fields in the decode tables 205 /// corresponding to the decode paths for this instruction. 206 /// 207 /// \param tables The DisassemblerTables to populate with the decode 208 /// decode information for the current instruction. 209 void emitDecodePath(DisassemblerTables &tables) const; 210 211 /// Constructor - Initializes a RecognizableInstr with the appropriate fields 212 /// from a CodeGenInstruction. 213 /// 214 /// \param tables The DisassemblerTables that the specifier will be added to. 215 /// \param insn The CodeGenInstruction to extract information from. 216 /// \param uid The unique ID of the current instruction. 217 RecognizableInstr(DisassemblerTables &tables, 218 const CodeGenInstruction &insn, 219 InstrUID uid); 220 public: 221 /// processInstr - Accepts a CodeGenInstruction and loads decode information 222 /// for it into a DisassemblerTables if appropriate. 223 /// 224 /// \param tables The DiassemblerTables to be populated with decode 225 /// information. 226 /// \param insn The CodeGenInstruction to be used as a source for this 227 /// information. 228 /// \param uid The unique ID of the instruction. 229 static void processInstr(DisassemblerTables &tables, 230 const CodeGenInstruction &insn, 231 InstrUID uid); 232 }; 233 234 } // namespace X86Disassembler 235 236 } // namespace llvm 237 238 #endif 239