1 //===- utils/TableGen/X86FoldTablesEmitter.cpp - X86 backend-*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This tablegen backend is responsible for emitting the memory fold tables of 10 // the X86 backend instructions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "CodeGenTarget.h" 15 #include "X86RecognizableInstr.h" 16 #include "llvm/Support/FormattedStream.h" 17 #include "llvm/TableGen/Error.h" 18 #include "llvm/TableGen/TableGenBackend.h" 19 20 using namespace llvm; 21 using namespace X86Disassembler; 22 23 namespace { 24 25 // 3 possible strategies for the unfolding flag (TB_NO_REVERSE) of the 26 // manual added entries. 27 enum UnfoldStrategy { 28 UNFOLD, // Allow unfolding 29 NO_UNFOLD, // Prevent unfolding 30 NO_STRATEGY // Make decision according to operands' sizes 31 }; 32 33 // Represents an entry in the manual mapped instructions set. 34 struct ManualMapEntry { 35 const char *RegInstStr; 36 const char *MemInstStr; 37 UnfoldStrategy Strategy; 38 39 ManualMapEntry(const char *RegInstStr, const char *MemInstStr, 40 UnfoldStrategy Strategy = NO_STRATEGY) 41 : RegInstStr(RegInstStr), MemInstStr(MemInstStr), Strategy(Strategy) {} 42 }; 43 44 // List of instructions requiring explicitly aligned memory. 45 const char *ExplicitAlign[] = {"MOVDQA", "MOVAPS", "MOVAPD", "MOVNTPS", 46 "MOVNTPD", "MOVNTDQ", "MOVNTDQA"}; 47 48 // List of instructions NOT requiring explicit memory alignment. 49 const char *ExplicitUnalign[] = {"MOVDQU", "MOVUPS", "MOVUPD", 50 "PCMPESTRM", "PCMPESTRI", 51 "PCMPISTRM", "PCMPISTRI" }; 52 53 // For manually mapping instructions that do not match by their encoding. 54 const ManualMapEntry ManualMapSet[] = { 55 { "ADD16ri_DB", "ADD16mi", NO_UNFOLD }, 56 { "ADD16ri8_DB", "ADD16mi8", NO_UNFOLD }, 57 { "ADD16rr_DB", "ADD16mr", NO_UNFOLD }, 58 { "ADD32ri_DB", "ADD32mi", NO_UNFOLD }, 59 { "ADD32ri8_DB", "ADD32mi8", NO_UNFOLD }, 60 { "ADD32rr_DB", "ADD32mr", NO_UNFOLD }, 61 { "ADD64ri32_DB", "ADD64mi32", NO_UNFOLD }, 62 { "ADD64ri8_DB", "ADD64mi8", NO_UNFOLD }, 63 { "ADD64rr_DB", "ADD64mr", NO_UNFOLD }, 64 { "ADD8ri_DB", "ADD8mi", NO_UNFOLD }, 65 { "ADD8rr_DB", "ADD8mr", NO_UNFOLD }, 66 { "ADD16rr_DB", "ADD16rm", NO_UNFOLD }, 67 { "ADD32rr_DB", "ADD32rm", NO_UNFOLD }, 68 { "ADD64rr_DB", "ADD64rm", NO_UNFOLD }, 69 { "ADD8rr_DB", "ADD8rm", NO_UNFOLD }, 70 { "PUSH16r", "PUSH16rmm", UNFOLD }, 71 { "PUSH32r", "PUSH32rmm", UNFOLD }, 72 { "PUSH64r", "PUSH64rmm", UNFOLD }, 73 { "TAILJMPr", "TAILJMPm", UNFOLD }, 74 { "TAILJMPr64", "TAILJMPm64", UNFOLD }, 75 { "TAILJMPr64_REX", "TAILJMPm64_REX", UNFOLD }, 76 }; 77 78 79 static bool isExplicitAlign(const CodeGenInstruction *Inst) { 80 return any_of(ExplicitAlign, [Inst](const char *InstStr) { 81 return Inst->TheDef->getName().contains(InstStr); 82 }); 83 } 84 85 static bool isExplicitUnalign(const CodeGenInstruction *Inst) { 86 return any_of(ExplicitUnalign, [Inst](const char *InstStr) { 87 return Inst->TheDef->getName().contains(InstStr); 88 }); 89 } 90 91 class X86FoldTablesEmitter { 92 RecordKeeper &Records; 93 CodeGenTarget Target; 94 95 // Represents an entry in the folding table 96 class X86FoldTableEntry { 97 const CodeGenInstruction *RegInst; 98 const CodeGenInstruction *MemInst; 99 100 public: 101 bool CannotUnfold = false; 102 bool IsLoad = false; 103 bool IsStore = false; 104 bool IsAligned = false; 105 unsigned int Alignment = 0; 106 107 X86FoldTableEntry(const CodeGenInstruction *RegInst, 108 const CodeGenInstruction *MemInst) 109 : RegInst(RegInst), MemInst(MemInst) {} 110 111 void print(formatted_raw_ostream &OS) const { 112 OS.indent(2); 113 OS << "{ X86::" << RegInst->TheDef->getName() << ","; 114 OS.PadToColumn(40); 115 OS << "X86::" << MemInst->TheDef->getName() << ","; 116 OS.PadToColumn(75); 117 118 std::string Attrs; 119 if (IsLoad) 120 Attrs += "TB_FOLDED_LOAD | "; 121 if (IsStore) 122 Attrs += "TB_FOLDED_STORE | "; 123 if (CannotUnfold) 124 Attrs += "TB_NO_REVERSE | "; 125 if (IsAligned) 126 Attrs += "TB_ALIGN_" + std::to_string(Alignment) + " | "; 127 128 StringRef SimplifiedAttrs = StringRef(Attrs).rtrim("| "); 129 if (SimplifiedAttrs.empty()) 130 SimplifiedAttrs = "0"; 131 132 OS << SimplifiedAttrs << " },\n"; 133 } 134 135 bool operator<(const X86FoldTableEntry &RHS) const { 136 bool LHSpseudo = RegInst->TheDef->getValueAsBit("isPseudo"); 137 bool RHSpseudo = RHS.RegInst->TheDef->getValueAsBit("isPseudo"); 138 if (LHSpseudo != RHSpseudo) 139 return LHSpseudo; 140 141 return RegInst->TheDef->getName() < RHS.RegInst->TheDef->getName(); 142 } 143 }; 144 145 typedef std::vector<X86FoldTableEntry> FoldTable; 146 // std::vector for each folding table. 147 // Table2Addr - Holds instructions which their memory form performs load+store 148 // Table#i - Holds instructions which the their memory form perform a load OR 149 // a store, and their #i'th operand is folded. 150 FoldTable Table2Addr; 151 FoldTable Table0; 152 FoldTable Table1; 153 FoldTable Table2; 154 FoldTable Table3; 155 FoldTable Table4; 156 157 public: 158 X86FoldTablesEmitter(RecordKeeper &R) : Records(R), Target(R) {} 159 160 // run - Generate the 6 X86 memory fold tables. 161 void run(formatted_raw_ostream &OS); 162 163 private: 164 // Decides to which table to add the entry with the given instructions. 165 // S sets the strategy of adding the TB_NO_REVERSE flag. 166 void updateTables(const CodeGenInstruction *RegInstr, 167 const CodeGenInstruction *MemInstr, 168 const UnfoldStrategy S = NO_STRATEGY); 169 170 // Generates X86FoldTableEntry with the given instructions and fill it with 171 // the appropriate flags - then adds it to Table. 172 void addEntryWithFlags(FoldTable &Table, const CodeGenInstruction *RegInstr, 173 const CodeGenInstruction *MemInstr, 174 const UnfoldStrategy S, const unsigned int FoldedInd); 175 176 // Print the given table as a static const C++ array of type 177 // X86MemoryFoldTableEntry. 178 void printTable(const FoldTable &Table, StringRef TableName, 179 formatted_raw_ostream &OS) { 180 OS << "static const X86MemoryFoldTableEntry MemoryFold" << TableName 181 << "[] = {\n"; 182 183 for (const X86FoldTableEntry &E : Table) 184 E.print(OS); 185 186 OS << "};\n\n"; 187 } 188 }; 189 190 // Return true if one of the instruction's operands is a RST register class 191 static bool hasRSTRegClass(const CodeGenInstruction *Inst) { 192 return any_of(Inst->Operands, [](const CGIOperandList::OperandInfo &OpIn) { 193 return OpIn.Rec->getName() == "RST" || OpIn.Rec->getName() == "RSTi"; 194 }); 195 } 196 197 // Return true if one of the instruction's operands is a ptr_rc_tailcall 198 static bool hasPtrTailcallRegClass(const CodeGenInstruction *Inst) { 199 return any_of(Inst->Operands, [](const CGIOperandList::OperandInfo &OpIn) { 200 return OpIn.Rec->getName() == "ptr_rc_tailcall"; 201 }); 202 } 203 204 // Calculates the integer value representing the BitsInit object 205 static inline uint64_t getValueFromBitsInit(const BitsInit *B) { 206 assert(B->getNumBits() <= sizeof(uint64_t) * 8 && "BitInits' too long!"); 207 208 uint64_t Value = 0; 209 for (unsigned i = 0, e = B->getNumBits(); i != e; ++i) { 210 BitInit *Bit = cast<BitInit>(B->getBit(i)); 211 Value |= uint64_t(Bit->getValue()) << i; 212 } 213 return Value; 214 } 215 216 // Return true if the instruction defined as a register flavor. 217 static inline bool hasRegisterFormat(const Record *Inst) { 218 const BitsInit *FormBits = Inst->getValueAsBitsInit("FormBits"); 219 uint64_t FormBitsNum = getValueFromBitsInit(FormBits); 220 221 // Values from X86Local namespace defined in X86RecognizableInstr.cpp 222 return FormBitsNum >= X86Local::MRMDestReg && FormBitsNum <= X86Local::MRM7r; 223 } 224 225 // Return true if the instruction defined as a memory flavor. 226 static inline bool hasMemoryFormat(const Record *Inst) { 227 const BitsInit *FormBits = Inst->getValueAsBitsInit("FormBits"); 228 uint64_t FormBitsNum = getValueFromBitsInit(FormBits); 229 230 // Values from X86Local namespace defined in X86RecognizableInstr.cpp 231 return FormBitsNum >= X86Local::MRMDestMem && FormBitsNum <= X86Local::MRM7m; 232 } 233 234 static inline bool isNOREXRegClass(const Record *Op) { 235 return Op->getName().contains("_NOREX"); 236 } 237 238 // Get the alternative instruction pointed by "FoldGenRegForm" field. 239 static inline const CodeGenInstruction * 240 getAltRegInst(const CodeGenInstruction *I, const RecordKeeper &Records, 241 const CodeGenTarget &Target) { 242 243 StringRef AltRegInstStr = I->TheDef->getValueAsString("FoldGenRegForm"); 244 Record *AltRegInstRec = Records.getDef(AltRegInstStr); 245 assert(AltRegInstRec && 246 "Alternative register form instruction def not found"); 247 CodeGenInstruction &AltRegInst = Target.getInstruction(AltRegInstRec); 248 return &AltRegInst; 249 } 250 251 // Function object - Operator() returns true if the given VEX instruction 252 // matches the EVEX instruction of this object. 253 class IsMatch { 254 const CodeGenInstruction *MemInst; 255 256 public: 257 IsMatch(const CodeGenInstruction *Inst, const RecordKeeper &Records) 258 : MemInst(Inst) {} 259 260 bool operator()(const CodeGenInstruction *RegInst) { 261 X86Disassembler::RecognizableInstrBase RegRI(*RegInst); 262 X86Disassembler::RecognizableInstrBase MemRI(*MemInst); 263 const Record *RegRec = RegInst->TheDef; 264 const Record *MemRec = MemInst->TheDef; 265 266 // EVEX_B means different things for memory and register forms. 267 if (RegRI.HasEVEX_B != 0 || MemRI.HasEVEX_B != 0) 268 return false; 269 270 // Instruction's format - The register form's "Form" field should be 271 // the opposite of the memory form's "Form" field. 272 if (!areOppositeForms(RegRI.Form, MemRI.Form)) 273 return false; 274 275 // Return false if one (at least) of the encoding fields of both 276 // instructions do not match. 277 if (RegRI.Encoding != MemRI.Encoding || RegRI.Opcode != MemRI.Opcode || 278 RegRI.OpPrefix != MemRI.OpPrefix || RegRI.OpMap != MemRI.OpMap || 279 RegRI.OpSize != MemRI.OpSize || RegRI.AdSize != MemRI.AdSize || 280 RegRI.HasREX_W != MemRI.HasREX_W || 281 RegRI.HasVEX_4V != MemRI.HasVEX_4V || 282 RegRI.HasVEX_L != MemRI.HasVEX_L || 283 RegRI.HasVEX_W != MemRI.HasVEX_W || 284 RegRI.IgnoresVEX_L != MemRI.IgnoresVEX_L || 285 RegRI.IgnoresVEX_W != MemRI.IgnoresVEX_W || 286 RegRI.HasEVEX_K != MemRI.HasEVEX_K || 287 RegRI.HasEVEX_KZ != MemRI.HasEVEX_KZ || 288 RegRI.HasEVEX_L2 != MemRI.HasEVEX_L2 || 289 RegRec->getValueAsBit("hasEVEX_RC") != 290 MemRec->getValueAsBit("hasEVEX_RC") || 291 RegRec->getValueAsBit("hasLockPrefix") != 292 MemRec->getValueAsBit("hasLockPrefix") || 293 RegRec->getValueAsBit("hasNoTrackPrefix") != 294 MemRec->getValueAsBit("hasNoTrackPrefix") || 295 RegRec->getValueAsBit("EVEX_W1_VEX_W0") != 296 MemRec->getValueAsBit("EVEX_W1_VEX_W0")) 297 return false; 298 299 // Make sure the sizes of the operands of both instructions suit each other. 300 // This is needed for instructions with intrinsic version (_Int). 301 // Where the only difference is the size of the operands. 302 // For example: VUCOMISDZrm and Int_VUCOMISDrm 303 // Also for instructions that their EVEX version was upgraded to work with 304 // k-registers. For example VPCMPEQBrm (xmm output register) and 305 // VPCMPEQBZ128rm (k register output register). 306 bool ArgFolded = false; 307 unsigned MemOutSize = MemRec->getValueAsDag("OutOperandList")->getNumArgs(); 308 unsigned RegOutSize = RegRec->getValueAsDag("OutOperandList")->getNumArgs(); 309 unsigned MemInSize = MemRec->getValueAsDag("InOperandList")->getNumArgs(); 310 unsigned RegInSize = RegRec->getValueAsDag("InOperandList")->getNumArgs(); 311 312 // Instructions with one output in their memory form use the memory folded 313 // operand as source and destination (Read-Modify-Write). 314 unsigned RegStartIdx = 315 (MemOutSize + 1 == RegOutSize) && (MemInSize == RegInSize) ? 1 : 0; 316 317 for (unsigned i = 0, e = MemInst->Operands.size(); i < e; i++) { 318 Record *MemOpRec = MemInst->Operands[i].Rec; 319 Record *RegOpRec = RegInst->Operands[i + RegStartIdx].Rec; 320 321 if (MemOpRec == RegOpRec) 322 continue; 323 324 if (isRegisterOperand(MemOpRec) && isRegisterOperand(RegOpRec)) { 325 if (getRegOperandSize(MemOpRec) != getRegOperandSize(RegOpRec) || 326 isNOREXRegClass(MemOpRec) != isNOREXRegClass(RegOpRec)) 327 return false; 328 } else if (isMemoryOperand(MemOpRec) && isMemoryOperand(RegOpRec)) { 329 if (getMemOperandSize(MemOpRec) != getMemOperandSize(RegOpRec)) 330 return false; 331 } else if (isImmediateOperand(MemOpRec) && isImmediateOperand(RegOpRec)) { 332 if (MemOpRec->getValueAsDef("Type") != RegOpRec->getValueAsDef("Type")) 333 return false; 334 } else { 335 // Only one operand can be folded. 336 if (ArgFolded) 337 return false; 338 339 assert(isRegisterOperand(RegOpRec) && isMemoryOperand(MemOpRec)); 340 ArgFolded = true; 341 } 342 } 343 344 return true; 345 } 346 347 private: 348 // Return true of the 2 given forms are the opposite of each other. 349 bool areOppositeForms(unsigned RegForm, unsigned MemForm) { 350 if ((MemForm == X86Local::MRM0m && RegForm == X86Local::MRM0r) || 351 (MemForm == X86Local::MRM1m && RegForm == X86Local::MRM1r) || 352 (MemForm == X86Local::MRM2m && RegForm == X86Local::MRM2r) || 353 (MemForm == X86Local::MRM3m && RegForm == X86Local::MRM3r) || 354 (MemForm == X86Local::MRM4m && RegForm == X86Local::MRM4r) || 355 (MemForm == X86Local::MRM5m && RegForm == X86Local::MRM5r) || 356 (MemForm == X86Local::MRM6m && RegForm == X86Local::MRM6r) || 357 (MemForm == X86Local::MRM7m && RegForm == X86Local::MRM7r) || 358 (MemForm == X86Local::MRMXm && RegForm == X86Local::MRMXr) || 359 (MemForm == X86Local::MRMXmCC && RegForm == X86Local::MRMXrCC) || 360 (MemForm == X86Local::MRMDestMem && RegForm == X86Local::MRMDestReg) || 361 (MemForm == X86Local::MRMSrcMem && RegForm == X86Local::MRMSrcReg) || 362 (MemForm == X86Local::MRMSrcMem4VOp3 && 363 RegForm == X86Local::MRMSrcReg4VOp3) || 364 (MemForm == X86Local::MRMSrcMemOp4 && 365 RegForm == X86Local::MRMSrcRegOp4) || 366 (MemForm == X86Local::MRMSrcMemCC && RegForm == X86Local::MRMSrcRegCC)) 367 return true; 368 369 return false; 370 } 371 }; 372 373 } // end anonymous namespace 374 375 void X86FoldTablesEmitter::addEntryWithFlags(FoldTable &Table, 376 const CodeGenInstruction *RegInstr, 377 const CodeGenInstruction *MemInstr, 378 const UnfoldStrategy S, 379 const unsigned int FoldedInd) { 380 381 X86FoldTableEntry Result = X86FoldTableEntry(RegInstr, MemInstr); 382 Record *RegRec = RegInstr->TheDef; 383 Record *MemRec = MemInstr->TheDef; 384 385 // Only table0 entries should explicitly specify a load or store flag. 386 if (&Table == &Table0) { 387 unsigned MemInOpsNum = MemRec->getValueAsDag("InOperandList")->getNumArgs(); 388 unsigned RegInOpsNum = RegRec->getValueAsDag("InOperandList")->getNumArgs(); 389 // If the instruction writes to the folded operand, it will appear as an 390 // output in the register form instruction and as an input in the memory 391 // form instruction. 392 // If the instruction reads from the folded operand, it well appear as in 393 // input in both forms. 394 if (MemInOpsNum == RegInOpsNum) 395 Result.IsLoad = true; 396 else 397 Result.IsStore = true; 398 } 399 400 Record *RegOpRec = RegInstr->Operands[FoldedInd].Rec; 401 Record *MemOpRec = MemInstr->Operands[FoldedInd].Rec; 402 403 // Unfolding code generates a load/store instruction according to the size of 404 // the register in the register form instruction. 405 // If the register's size is greater than the memory's operand size, do not 406 // allow unfolding. 407 if (S == UNFOLD) 408 Result.CannotUnfold = false; 409 else if (S == NO_UNFOLD) 410 Result.CannotUnfold = true; 411 else if (getRegOperandSize(RegOpRec) > getMemOperandSize(MemOpRec)) 412 Result.CannotUnfold = true; // S == NO_STRATEGY 413 414 uint64_t Enc = getValueFromBitsInit(RegRec->getValueAsBitsInit("OpEncBits")); 415 if (isExplicitAlign(RegInstr)) { 416 // The instruction require explicitly aligned memory. 417 BitsInit *VectSize = RegRec->getValueAsBitsInit("VectSize"); 418 uint64_t Value = getValueFromBitsInit(VectSize); 419 Result.IsAligned = true; 420 Result.Alignment = Value; 421 } else if (Enc != X86Local::XOP && Enc != X86Local::VEX && 422 Enc != X86Local::EVEX) { 423 // Instructions with VEX encoding do not require alignment. 424 if (!isExplicitUnalign(RegInstr) && getMemOperandSize(MemOpRec) > 64) { 425 // SSE packed vector instructions require a 16 byte alignment. 426 Result.IsAligned = true; 427 Result.Alignment = 16; 428 } 429 } 430 431 Table.push_back(Result); 432 } 433 434 void X86FoldTablesEmitter::updateTables(const CodeGenInstruction *RegInstr, 435 const CodeGenInstruction *MemInstr, 436 const UnfoldStrategy S) { 437 438 Record *RegRec = RegInstr->TheDef; 439 Record *MemRec = MemInstr->TheDef; 440 unsigned MemOutSize = MemRec->getValueAsDag("OutOperandList")->getNumArgs(); 441 unsigned RegOutSize = RegRec->getValueAsDag("OutOperandList")->getNumArgs(); 442 unsigned MemInSize = MemRec->getValueAsDag("InOperandList")->getNumArgs(); 443 unsigned RegInSize = RegRec->getValueAsDag("InOperandList")->getNumArgs(); 444 445 // Instructions which Read-Modify-Write should be added to Table2Addr. 446 if (MemOutSize != RegOutSize && MemInSize == RegInSize) { 447 addEntryWithFlags(Table2Addr, RegInstr, MemInstr, S, 0); 448 return; 449 } 450 451 if (MemInSize == RegInSize && MemOutSize == RegOutSize) { 452 // Load-Folding cases. 453 // If the i'th register form operand is a register and the i'th memory form 454 // operand is a memory operand, add instructions to Table#i. 455 for (unsigned i = RegOutSize, e = RegInstr->Operands.size(); i < e; i++) { 456 Record *RegOpRec = RegInstr->Operands[i].Rec; 457 Record *MemOpRec = MemInstr->Operands[i].Rec; 458 // PointerLikeRegClass: For instructions like TAILJMPr, TAILJMPr64, TAILJMPr64_REX 459 if ((isRegisterOperand(RegOpRec) || 460 RegOpRec->isSubClassOf("PointerLikeRegClass")) && 461 isMemoryOperand(MemOpRec)) { 462 switch (i) { 463 case 0: 464 addEntryWithFlags(Table0, RegInstr, MemInstr, S, 0); 465 return; 466 case 1: 467 addEntryWithFlags(Table1, RegInstr, MemInstr, S, 1); 468 return; 469 case 2: 470 addEntryWithFlags(Table2, RegInstr, MemInstr, S, 2); 471 return; 472 case 3: 473 addEntryWithFlags(Table3, RegInstr, MemInstr, S, 3); 474 return; 475 case 4: 476 addEntryWithFlags(Table4, RegInstr, MemInstr, S, 4); 477 return; 478 } 479 } 480 } 481 } else if (MemInSize == RegInSize + 1 && MemOutSize + 1 == RegOutSize) { 482 // Store-Folding cases. 483 // If the memory form instruction performs a store, the *output* 484 // register of the register form instructions disappear and instead a 485 // memory *input* operand appears in the memory form instruction. 486 // For example: 487 // MOVAPSrr => (outs VR128:$dst), (ins VR128:$src) 488 // MOVAPSmr => (outs), (ins f128mem:$dst, VR128:$src) 489 Record *RegOpRec = RegInstr->Operands[RegOutSize - 1].Rec; 490 Record *MemOpRec = MemInstr->Operands[RegOutSize - 1].Rec; 491 if (isRegisterOperand(RegOpRec) && isMemoryOperand(MemOpRec) && 492 getRegOperandSize(RegOpRec) == getMemOperandSize(MemOpRec)) 493 addEntryWithFlags(Table0, RegInstr, MemInstr, S, 0); 494 } 495 } 496 497 void X86FoldTablesEmitter::run(formatted_raw_ostream &OS) { 498 emitSourceFileHeader("X86 fold tables", OS); 499 500 // Holds all memory instructions 501 std::vector<const CodeGenInstruction *> MemInsts; 502 // Holds all register instructions - divided according to opcode. 503 std::map<uint8_t, std::vector<const CodeGenInstruction *>> RegInsts; 504 505 ArrayRef<const CodeGenInstruction *> NumberedInstructions = 506 Target.getInstructionsByEnumValue(); 507 508 for (const CodeGenInstruction *Inst : NumberedInstructions) { 509 const Record *Rec = Inst->TheDef; 510 if (!Rec->isSubClassOf("X86Inst") || Rec->getValueAsBit("isAsmParserOnly")) 511 continue; 512 513 // - Do not proceed if the instruction is marked as notMemoryFoldable. 514 // - Instructions including RST register class operands are not relevant 515 // for memory folding (for further details check the explanation in 516 // lib/Target/X86/X86InstrFPStack.td file). 517 // - Some instructions (listed in the manual map above) use the register 518 // class ptr_rc_tailcall, which can be of a size 32 or 64, to ensure 519 // safe mapping of these instruction we manually map them and exclude 520 // them from the automation. 521 if (Rec->getValueAsBit("isMemoryFoldable") == false || 522 hasRSTRegClass(Inst) || hasPtrTailcallRegClass(Inst)) 523 continue; 524 525 // Add all the memory form instructions to MemInsts, and all the register 526 // form instructions to RegInsts[Opc], where Opc in the opcode of each 527 // instructions. this helps reducing the runtime of the backend. 528 if (hasMemoryFormat(Rec)) 529 MemInsts.push_back(Inst); 530 else if (hasRegisterFormat(Rec)) { 531 uint8_t Opc = getValueFromBitsInit(Rec->getValueAsBitsInit("Opcode")); 532 RegInsts[Opc].push_back(Inst); 533 } 534 } 535 536 // For each memory form instruction, try to find its register form 537 // instruction. 538 for (const CodeGenInstruction *MemInst : MemInsts) { 539 uint8_t Opc = 540 getValueFromBitsInit(MemInst->TheDef->getValueAsBitsInit("Opcode")); 541 542 auto RegInstsIt = RegInsts.find(Opc); 543 if (RegInstsIt == RegInsts.end()) 544 continue; 545 546 // Two forms (memory & register) of the same instruction must have the same 547 // opcode. try matching only with register form instructions with the same 548 // opcode. 549 std::vector<const CodeGenInstruction *> &OpcRegInsts = RegInstsIt->second; 550 551 auto Match = find_if(OpcRegInsts, IsMatch(MemInst, Records)); 552 if (Match != OpcRegInsts.end()) { 553 const CodeGenInstruction *RegInst = *Match; 554 // If the matched instruction has it's "FoldGenRegForm" set, map the 555 // memory form instruction to the register form instruction pointed by 556 // this field 557 if (RegInst->TheDef->isValueUnset("FoldGenRegForm")) { 558 updateTables(RegInst, MemInst); 559 } else { 560 const CodeGenInstruction *AltRegInst = 561 getAltRegInst(RegInst, Records, Target); 562 updateTables(AltRegInst, MemInst); 563 } 564 OpcRegInsts.erase(Match); 565 } 566 } 567 568 // Add the manually mapped instructions listed above. 569 for (const ManualMapEntry &Entry : ManualMapSet) { 570 Record *RegInstIter = Records.getDef(Entry.RegInstStr); 571 Record *MemInstIter = Records.getDef(Entry.MemInstStr); 572 573 updateTables(&(Target.getInstruction(RegInstIter)), 574 &(Target.getInstruction(MemInstIter)), Entry.Strategy); 575 } 576 577 // Sort the tables before printing. 578 llvm::sort(Table2Addr); 579 llvm::sort(Table0); 580 llvm::sort(Table1); 581 llvm::sort(Table2); 582 llvm::sort(Table3); 583 llvm::sort(Table4); 584 585 // Print all tables. 586 printTable(Table2Addr, "Table2Addr", OS); 587 printTable(Table0, "Table0", OS); 588 printTable(Table1, "Table1", OS); 589 printTable(Table2, "Table2", OS); 590 printTable(Table3, "Table3", OS); 591 printTable(Table4, "Table4", OS); 592 } 593 594 namespace llvm { 595 596 void EmitX86FoldTables(RecordKeeper &RK, raw_ostream &o) { 597 formatted_raw_ostream OS(o); 598 X86FoldTablesEmitter(RK).run(OS); 599 } 600 } // namespace llvm 601