1 //===- utils/TableGen/X86EVEX2VEXTablesEmitter.cpp - X86 backend-*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// This tablegen backend is responsible for emitting the X86 backend EVEX2VEX
10 /// compression tables.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #include "CodeGenInstruction.h"
15 #include "CodeGenTarget.h"
16 #include "llvm/TableGen/Error.h"
17 #include "llvm/TableGen/TableGenBackend.h"
18 
19 using namespace llvm;
20 
21 namespace {
22 
23 class X86EVEX2VEXTablesEmitter {
24   RecordKeeper &Records;
25   CodeGenTarget Target;
26 
27   // Hold all non-masked & non-broadcasted EVEX encoded instructions
28   std::vector<const CodeGenInstruction *> EVEXInsts;
29   // Hold all VEX encoded instructions. Divided into groups with same opcodes
30   // to make the search more efficient
31   std::map<uint64_t, std::vector<const CodeGenInstruction *>> VEXInsts;
32 
33   typedef std::pair<const CodeGenInstruction *, const CodeGenInstruction *> Entry;
34   typedef std::pair<StringRef, StringRef> Predicate;
35 
36   // Represent both compress tables
37   std::vector<Entry> EVEX2VEX128;
38   std::vector<Entry> EVEX2VEX256;
39   // Represent predicates of VEX instructions.
40   std::vector<Predicate> EVEX2VEXPredicates;
41 
42 public:
43   X86EVEX2VEXTablesEmitter(RecordKeeper &R) : Records(R), Target(R) {}
44 
45   // run - Output X86 EVEX2VEX tables.
46   void run(raw_ostream &OS);
47 
48 private:
49   // Prints the given table as a C++ array of type
50   // X86EvexToVexCompressTableEntry
51   void printTable(const std::vector<Entry> &Table, raw_ostream &OS);
52   // Prints function which checks target feature specific predicate.
53   void printCheckPredicate(const std::vector<Predicate> &Predicates,
54                            raw_ostream &OS);
55 };
56 
57 void X86EVEX2VEXTablesEmitter::printTable(const std::vector<Entry> &Table,
58                                           raw_ostream &OS) {
59   StringRef Size = (Table == EVEX2VEX128) ? "128" : "256";
60 
61   OS << "// X86 EVEX encoded instructions that have a VEX " << Size
62      << " encoding\n"
63      << "// (table format: <EVEX opcode, VEX-" << Size << " opcode>).\n"
64      << "static const X86EvexToVexCompressTableEntry X86EvexToVex" << Size
65      << "CompressTable[] = {\n"
66      << "  // EVEX scalar with corresponding VEX.\n";
67 
68   // Print all entries added to the table
69   for (const auto &Pair : Table) {
70     OS << "  { X86::" << Pair.first->TheDef->getName()
71        << ", X86::" << Pair.second->TheDef->getName() << " },\n";
72   }
73 
74   OS << "};\n\n";
75 }
76 
77 void X86EVEX2VEXTablesEmitter::printCheckPredicate(
78     const std::vector<Predicate> &Predicates, raw_ostream &OS) {
79   OS << "static bool CheckVEXInstPredicate"
80      << "(MachineInstr &MI, const X86Subtarget *Subtarget) {\n"
81      << "  unsigned Opc = MI.getOpcode();\n"
82      << "  switch (Opc) {\n"
83      << "    default: return true;\n";
84   for (const auto &Pair : Predicates)
85     OS << "    case X86::" << Pair.first << ": return " << Pair.second << ";\n";
86   OS << "  }\n"
87      << "}\n\n";
88 }
89 
90 // Return true if the 2 BitsInits are equal
91 // Calculates the integer value residing BitsInit object
92 static inline uint64_t getValueFromBitsInit(const BitsInit *B) {
93   uint64_t Value = 0;
94   for (unsigned i = 0, e = B->getNumBits(); i != e; ++i) {
95     if (BitInit *Bit = dyn_cast<BitInit>(B->getBit(i)))
96       Value |= uint64_t(Bit->getValue()) << i;
97     else
98       PrintFatalError("Invalid VectSize bit");
99   }
100   return Value;
101 }
102 
103 // Function object - Operator() returns true if the given VEX instruction
104 // matches the EVEX instruction of this object.
105 class IsMatch {
106   const CodeGenInstruction *EVEXInst;
107 
108 public:
109   IsMatch(const CodeGenInstruction *EVEXInst) : EVEXInst(EVEXInst) {}
110 
111   bool operator()(const CodeGenInstruction *VEXInst) {
112     Record *RecE = EVEXInst->TheDef;
113     Record *RecV = VEXInst->TheDef;
114     bool EVEX_W = RecE->getValueAsBit("HasVEX_W");
115     bool VEX_W  = RecV->getValueAsBit("HasVEX_W");
116     bool VEX_WIG  = RecV->getValueAsBit("IgnoresVEX_W");
117     bool EVEX_WIG = RecE->getValueAsBit("IgnoresVEX_W");
118     bool EVEX_W1_VEX_W0 = RecE->getValueAsBit("EVEX_W1_VEX_W0");
119 
120     if (RecV->getValueAsDef("OpEnc")->getName().str() != "EncVEX" ||
121         RecV->getValueAsBit("isCodeGenOnly") != RecE->getValueAsBit("isCodeGenOnly") ||
122         // VEX/EVEX fields
123         RecV->getValueAsDef("OpPrefix") != RecE->getValueAsDef("OpPrefix") ||
124         RecV->getValueAsDef("OpMap") != RecE->getValueAsDef("OpMap") ||
125         RecV->getValueAsBit("hasVEX_4V") != RecE->getValueAsBit("hasVEX_4V") ||
126         RecV->getValueAsBit("hasEVEX_L2") != RecE->getValueAsBit("hasEVEX_L2") ||
127         RecV->getValueAsBit("hasVEX_L") != RecE->getValueAsBit("hasVEX_L") ||
128         // Match is allowed if either is VEX_WIG, or they match, or EVEX
129         // is VEX_W1X and VEX is VEX_W0.
130         (!(VEX_WIG || (!EVEX_WIG && EVEX_W == VEX_W) ||
131            (EVEX_W1_VEX_W0 && EVEX_W && !VEX_W))) ||
132         // Instruction's format
133         RecV->getValueAsDef("Form") != RecE->getValueAsDef("Form"))
134       return false;
135 
136     // This is needed for instructions with intrinsic version (_Int).
137     // Where the only difference is the size of the operands.
138     // For example: VUCOMISDZrm and Int_VUCOMISDrm
139     // Also for instructions that their EVEX version was upgraded to work with
140     // k-registers. For example VPCMPEQBrm (xmm output register) and
141     // VPCMPEQBZ128rm (k register output register).
142     for (unsigned i = 0, e = EVEXInst->Operands.size(); i < e; i++) {
143       Record *OpRec1 = EVEXInst->Operands[i].Rec;
144       Record *OpRec2 = VEXInst->Operands[i].Rec;
145 
146       if (OpRec1 == OpRec2)
147         continue;
148 
149       if (isRegisterOperand(OpRec1) && isRegisterOperand(OpRec2)) {
150         if (getRegOperandSize(OpRec1) != getRegOperandSize(OpRec2))
151           return false;
152       } else if (isMemoryOperand(OpRec1) && isMemoryOperand(OpRec2)) {
153         return false;
154       } else if (isImmediateOperand(OpRec1) && isImmediateOperand(OpRec2)) {
155         if (OpRec1->getValueAsDef("Type") != OpRec2->getValueAsDef("Type")) {
156           return false;
157         }
158       } else
159         return false;
160     }
161 
162     return true;
163   }
164 
165 private:
166   static inline bool isRegisterOperand(const Record *Rec) {
167     return Rec->isSubClassOf("RegisterClass") ||
168            Rec->isSubClassOf("RegisterOperand");
169   }
170 
171   static inline bool isMemoryOperand(const Record *Rec) {
172     return Rec->isSubClassOf("Operand") &&
173            Rec->getValueAsString("OperandType") == "OPERAND_MEMORY";
174   }
175 
176   static inline bool isImmediateOperand(const Record *Rec) {
177     return Rec->isSubClassOf("Operand") &&
178            Rec->getValueAsString("OperandType") == "OPERAND_IMMEDIATE";
179   }
180 
181   static inline unsigned int getRegOperandSize(const Record *RegRec) {
182     if (RegRec->isSubClassOf("RegisterClass"))
183       return RegRec->getValueAsInt("Alignment");
184     if (RegRec->isSubClassOf("RegisterOperand"))
185       return RegRec->getValueAsDef("RegClass")->getValueAsInt("Alignment");
186 
187     llvm_unreachable("Register operand's size not known!");
188   }
189 };
190 
191 void X86EVEX2VEXTablesEmitter::run(raw_ostream &OS) {
192   auto getPredicates = [&](const CodeGenInstruction *Inst) {
193     std::vector<Record *> PredicatesRecords =
194         Inst->TheDef->getValueAsListOfDefs("Predicates");
195     // Currently we only do AVX related checks and assume each instruction
196     // has one and only one AVX related predicates.
197     for (unsigned i = 0, e = PredicatesRecords.size(); i != e; ++i)
198       if (PredicatesRecords[i]->getName().startswith("HasAVX"))
199         return PredicatesRecords[i]->getValueAsString("CondString");
200     llvm_unreachable(
201         "Instruction with checkPredicate set must have one predicate!");
202   };
203 
204   emitSourceFileHeader("X86 EVEX2VEX tables", OS);
205 
206   ArrayRef<const CodeGenInstruction *> NumberedInstructions =
207       Target.getInstructionsByEnumValue();
208 
209   for (const CodeGenInstruction *Inst : NumberedInstructions) {
210     // Filter non-X86 instructions.
211     if (!Inst->TheDef->isSubClassOf("X86Inst"))
212       continue;
213 
214     // Add VEX encoded instructions to one of VEXInsts vectors according to
215     // it's opcode.
216     if (Inst->TheDef->getValueAsDef("OpEnc")->getName() == "EncVEX") {
217       uint64_t Opcode = getValueFromBitsInit(Inst->TheDef->
218                                              getValueAsBitsInit("Opcode"));
219       VEXInsts[Opcode].push_back(Inst);
220     }
221     // Add relevant EVEX encoded instructions to EVEXInsts
222     else if (Inst->TheDef->getValueAsDef("OpEnc")->getName() == "EncEVEX" &&
223              !Inst->TheDef->getValueAsBit("hasEVEX_K") &&
224              !Inst->TheDef->getValueAsBit("hasEVEX_B") &&
225              !Inst->TheDef->getValueAsBit("hasEVEX_L2") &&
226              !Inst->TheDef->getValueAsBit("notEVEX2VEXConvertible"))
227       EVEXInsts.push_back(Inst);
228   }
229 
230   for (const CodeGenInstruction *EVEXInst : EVEXInsts) {
231     uint64_t Opcode = getValueFromBitsInit(EVEXInst->TheDef->
232                                            getValueAsBitsInit("Opcode"));
233     // For each EVEX instruction look for a VEX match in the appropriate vector
234     // (instructions with the same opcode) using function object IsMatch.
235     // Allow EVEX2VEXOverride to explicitly specify a match.
236     const CodeGenInstruction *VEXInst = nullptr;
237     if (!EVEXInst->TheDef->isValueUnset("EVEX2VEXOverride")) {
238       StringRef AltInstStr =
239         EVEXInst->TheDef->getValueAsString("EVEX2VEXOverride");
240       Record *AltInstRec = Records.getDef(AltInstStr);
241       assert(AltInstRec && "EVEX2VEXOverride instruction not found!");
242       VEXInst = &Target.getInstruction(AltInstRec);
243     } else {
244       auto Match = llvm::find_if(VEXInsts[Opcode], IsMatch(EVEXInst));
245       if (Match != VEXInsts[Opcode].end())
246         VEXInst = *Match;
247     }
248 
249     if (!VEXInst)
250       continue;
251 
252     // In case a match is found add new entry to the appropriate table
253     if (EVEXInst->TheDef->getValueAsBit("hasVEX_L"))
254       EVEX2VEX256.push_back(std::make_pair(EVEXInst, VEXInst)); // {0,1}
255     else
256       EVEX2VEX128.push_back(std::make_pair(EVEXInst, VEXInst)); // {0,0}
257 
258     // Adding predicate check to EVEX2VEXPredicates table when needed.
259     if (VEXInst->TheDef->getValueAsBit("checkVEXPredicate"))
260       EVEX2VEXPredicates.push_back(
261           std::make_pair(EVEXInst->TheDef->getName(), getPredicates(VEXInst)));
262   }
263 
264   // Print both tables
265   printTable(EVEX2VEX128, OS);
266   printTable(EVEX2VEX256, OS);
267   // Print CheckVEXInstPredicate function.
268   printCheckPredicate(EVEX2VEXPredicates, OS);
269 }
270 }
271 
272 namespace llvm {
273 void EmitX86EVEX2VEXTables(RecordKeeper &RK, raw_ostream &OS) {
274   X86EVEX2VEXTablesEmitter(RK).run(OS);
275 }
276 }
277