1 //===- utils/TableGen/X86EVEX2VEXTablesEmitter.cpp - X86 backend-*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// This tablegen backend is responsible for emitting the X86 backend EVEX2VEX
11 /// compression tables.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "CodeGenDAGPatterns.h"
16 #include "CodeGenTarget.h"
17 #include "llvm/TableGen/Error.h"
18 #include "llvm/TableGen/TableGenBackend.h"
19 
20 using namespace llvm;
21 
22 namespace {
23 
24 class X86EVEX2VEXTablesEmitter {
25   CodeGenTarget Target;
26 
27   // Hold all non-masked & non-broadcasted EVEX encoded instructions
28   std::vector<const CodeGenInstruction *> EVEXInsts;
29   // Hold all VEX encoded instructions. Divided into groups with same opcodes
30   // to make the search more efficient
31   std::map<uint64_t, std::vector<const CodeGenInstruction *>> VEXInsts;
32 
33   typedef std::pair<const CodeGenInstruction *, const CodeGenInstruction *> Entry;
34 
35   // Represent both compress tables
36   std::vector<Entry> EVEX2VEX128;
37   std::vector<Entry> EVEX2VEX256;
38 
39   // Represents a manually added entry to the tables
40   struct ManualEntry {
41     const char *EVEXInstStr;
42     const char *VEXInstStr;
43     bool Is128Bit;
44   };
45 
46 public:
47   X86EVEX2VEXTablesEmitter(RecordKeeper &R) : Target(R) {}
48 
49   // run - Output X86 EVEX2VEX tables.
50   void run(raw_ostream &OS);
51 
52 private:
53   // Prints the given table as a C++ array of type
54   // X86EvexToVexCompressTableEntry
55   void printTable(const std::vector<Entry> &Table, raw_ostream &OS);
56 
57   bool inExceptionList(const CodeGenInstruction *Inst) {
58     // List of EVEX instructions that match VEX instructions by the encoding
59     // but do not perform the same operation.
60     static constexpr const char *ExceptionList[] = {
61         "VCVTQQ2PD",
62         "VCVTQQ2PS",
63         "VPMAXSQ",
64         "VPMAXUQ",
65         "VPMINSQ",
66         "VPMINUQ",
67         "VPMULLQ",
68         "VPSRAQ",
69         "VDBPSADBW",
70         "VRNDSCALE",
71         "VSCALEFPS"
72     };
73     // Instruction's name starts with one of the entries in the exception list
74     for (StringRef InstStr : ExceptionList) {
75       if (Inst->TheDef->getName().startswith(InstStr))
76         return true;
77     }
78     return false;
79   }
80 
81 };
82 
83 void X86EVEX2VEXTablesEmitter::printTable(const std::vector<Entry> &Table,
84                                           raw_ostream &OS) {
85   std::string Size = (Table == EVEX2VEX128) ? "128" : "256";
86 
87   OS << "// X86 EVEX encoded instructions that have a VEX " << Size
88      << " encoding\n"
89      << "// (table format: <EVEX opcode, VEX-" << Size << " opcode>).\n"
90      << "static const X86EvexToVexCompressTableEntry X86EvexToVex" << Size
91      << "CompressTable[] = {\n"
92      << "  // EVEX scalar with corresponding VEX.\n";
93 
94   // Print all entries added to the table
95   for (auto Pair : Table) {
96     OS << "  { X86::" << Pair.first->TheDef->getName()
97        << ", X86::" << Pair.second->TheDef->getName() << " },\n";
98   }
99 
100   // Some VEX instructions were duplicated to multiple EVEX versions due the
101   // introduction of mask variants, and thus some of the EVEX versions have
102   // different encoding than the VEX instruction. In order to maximize the
103   // compression we add these entries manually.
104   static constexpr ManualEntry ManuallyAddedEntries[] = {
105       // EVEX-Inst            VEX-Inst           Is128-bit
106       {"VMOVDQU8Z128mr",      "VMOVDQUmr",       true},
107       {"VMOVDQU8Z128rm",      "VMOVDQUrm",       true},
108       {"VMOVDQU8Z128rr",      "VMOVDQUrr",       true},
109       {"VMOVDQU8Z128rr_REV",  "VMOVDQUrr_REV",   true},
110       {"VMOVDQU16Z128mr",     "VMOVDQUmr",       true},
111       {"VMOVDQU16Z128rm",     "VMOVDQUrm",       true},
112       {"VMOVDQU16Z128rr",     "VMOVDQUrr",       true},
113       {"VMOVDQU16Z128rr_REV", "VMOVDQUrr_REV",   true},
114       {"VMOVDQU8Z256mr",      "VMOVDQUYmr",      false},
115       {"VMOVDQU8Z256rm",      "VMOVDQUYrm",      false},
116       {"VMOVDQU8Z256rr",      "VMOVDQUYrr",      false},
117       {"VMOVDQU8Z256rr_REV",  "VMOVDQUYrr_REV",  false},
118       {"VMOVDQU16Z256mr",     "VMOVDQUYmr",      false},
119       {"VMOVDQU16Z256rm",     "VMOVDQUYrm",      false},
120       {"VMOVDQU16Z256rr",     "VMOVDQUYrr",      false},
121       {"VMOVDQU16Z256rr_REV", "VMOVDQUYrr_REV",  false},
122 
123       {"VPERMILPDZ128mi",     "VPERMILPDmi",     true},
124       {"VPERMILPDZ128ri",     "VPERMILPDri",     true},
125       {"VPERMILPDZ128rm",     "VPERMILPDrm",     true},
126       {"VPERMILPDZ128rr",     "VPERMILPDrr",     true},
127       {"VPERMILPDZ256mi",     "VPERMILPDYmi",    false},
128       {"VPERMILPDZ256ri",     "VPERMILPDYri",    false},
129       {"VPERMILPDZ256rm",     "VPERMILPDYrm",    false},
130       {"VPERMILPDZ256rr",     "VPERMILPDYrr",    false},
131 
132       {"VPBROADCASTQZ128m",   "VPBROADCASTQrm",  true},
133       {"VPBROADCASTQZ128r",   "VPBROADCASTQrr",  true},
134       {"VPBROADCASTQZ256m",   "VPBROADCASTQYrm", false},
135       {"VPBROADCASTQZ256r",   "VPBROADCASTQYrr", false},
136 
137       {"VBROADCASTSDZ256m",   "VBROADCASTSDYrm", false},
138       {"VBROADCASTSDZ256r",   "VBROADCASTSDYrr", false},
139 
140       {"VBROADCASTF64X2Z128rm", "VBROADCASTF128", false},
141       {"VBROADCASTI64X2Z128rm", "VBROADCASTI128", false},
142 
143       {"VEXTRACTF64x2Z256mr", "VEXTRACTF128mr",  false},
144       {"VEXTRACTF64x2Z256rr", "VEXTRACTF128rr",  false},
145       {"VEXTRACTI64x2Z256mr", "VEXTRACTI128mr",  false},
146       {"VEXTRACTI64x2Z256rr", "VEXTRACTI128rr",  false},
147 
148       {"VINSERTF64x2Z256rm",  "VINSERTF128rm",   false},
149       {"VINSERTF64x2Z256rr",  "VINSERTF128rr",   false},
150       {"VINSERTI64x2Z256rm",  "VINSERTI128rm",   false},
151       {"VINSERTI64x2Z256rr",  "VINSERTI128rr",   false},
152 
153       // These will require some custom adjustment in the conversion pass.
154       {"VALIGNDZ128rri",      "VPALIGNRrri",     true},
155       {"VALIGNQZ128rri",      "VPALIGNRrri",     true},
156       {"VALIGNDZ128rmi",      "VPALIGNRrmi",     true},
157       {"VALIGNQZ128rmi",      "VPALIGNRrmi",     true},
158       {"VSHUFF32X4Z256rmi",   "VPERM2F128rm",    false},
159       {"VSHUFF32X4Z256rri",   "VPERM2F128rr",    false},
160       {"VSHUFF64X2Z256rmi",   "VPERM2F128rm",    false},
161       {"VSHUFF64X2Z256rri",   "VPERM2F128rr",    false},
162       {"VSHUFI32X4Z256rmi",   "VPERM2I128rm",    false},
163       {"VSHUFI32X4Z256rri",   "VPERM2I128rr",    false},
164       {"VSHUFI64X2Z256rmi",   "VPERM2I128rm",    false},
165       {"VSHUFI64X2Z256rri",   "VPERM2I128rr",    false},
166   };
167 
168   // Print the manually added entries
169   for (const ManualEntry &Entry : ManuallyAddedEntries) {
170     if ((Table == EVEX2VEX128 && Entry.Is128Bit) ||
171         (Table == EVEX2VEX256 && !Entry.Is128Bit)) {
172       OS << "  { X86::" << Entry.EVEXInstStr << ", X86::" << Entry.VEXInstStr
173          << " },\n";
174     }
175   }
176 
177   OS << "};\n\n";
178 }
179 
180 // Return true if the 2 BitsInits are equal
181 static inline bool equalBitsInits(const BitsInit *B1, const BitsInit *B2) {
182   if (B1->getNumBits() != B2->getNumBits())
183     PrintFatalError("Comparing two BitsInits with different sizes!");
184 
185   for (unsigned i = 0, e = B1->getNumBits(); i != e; ++i) {
186     if (BitInit *Bit1 = dyn_cast<BitInit>(B1->getBit(i))) {
187       if (BitInit *Bit2 = dyn_cast<BitInit>(B2->getBit(i))) {
188         if (Bit1->getValue() != Bit2->getValue())
189           return false;
190       } else
191         PrintFatalError("Invalid BitsInit bit");
192     } else
193       PrintFatalError("Invalid BitsInit bit");
194   }
195   return true;
196 }
197 
198 // Calculates the integer value residing BitsInit object
199 static inline uint64_t getValueFromBitsInit(const BitsInit *B) {
200   uint64_t Value = 0;
201   for (unsigned i = 0, e = B->getNumBits(); i != e; ++i) {
202     if (BitInit *Bit = dyn_cast<BitInit>(B->getBit(i)))
203       Value |= uint64_t(Bit->getValue()) << i;
204     else
205       PrintFatalError("Invalid VectSize bit");
206   }
207   return Value;
208 }
209 
210 // Function object - Operator() returns true if the given VEX instruction
211 // matches the EVEX instruction of this object.
212 class IsMatch {
213   const CodeGenInstruction *Inst;
214 
215 public:
216   IsMatch(const CodeGenInstruction *Inst) : Inst(Inst) {}
217 
218   bool operator()(const CodeGenInstruction *Inst2) {
219     Record *Rec1 = Inst->TheDef;
220     Record *Rec2 = Inst2->TheDef;
221     uint64_t Rec1WVEX =
222         getValueFromBitsInit(Rec1->getValueAsBitsInit("VEX_WPrefix"));
223     uint64_t Rec2WVEX =
224         getValueFromBitsInit(Rec2->getValueAsBitsInit("VEX_WPrefix"));
225 
226     if (Rec2->getValueAsDef("OpEnc")->getName().str() != "EncVEX" ||
227         // VEX/EVEX fields
228         Rec2->getValueAsDef("OpPrefix") != Rec1->getValueAsDef("OpPrefix") ||
229         Rec2->getValueAsDef("OpMap") != Rec1->getValueAsDef("OpMap") ||
230         Rec2->getValueAsBit("hasVEX_4V") != Rec1->getValueAsBit("hasVEX_4V") ||
231         !equalBitsInits(Rec2->getValueAsBitsInit("EVEX_LL"),
232                         Rec1->getValueAsBitsInit("EVEX_LL")) ||
233         (Rec1WVEX != 2 && Rec2WVEX != 2 && Rec1WVEX != Rec2WVEX) ||
234         // Instruction's format
235         Rec2->getValueAsDef("Form") != Rec1->getValueAsDef("Form") ||
236         Rec2->getValueAsBit("isAsmParserOnly") !=
237             Rec1->getValueAsBit("isAsmParserOnly"))
238       return false;
239 
240     // This is needed for instructions with intrinsic version (_Int).
241     // Where the only difference is the size of the operands.
242     // For example: VUCOMISDZrm and Int_VUCOMISDrm
243     // Also for instructions that their EVEX version was upgraded to work with
244     // k-registers. For example VPCMPEQBrm (xmm output register) and
245     // VPCMPEQBZ128rm (k register output register).
246     for (unsigned i = 0; i < Inst->Operands.size(); i++) {
247       Record *OpRec1 = Inst->Operands[i].Rec;
248       Record *OpRec2 = Inst2->Operands[i].Rec;
249 
250       if (OpRec1 == OpRec2)
251         continue;
252 
253       if (isRegisterOperand(OpRec1) && isRegisterOperand(OpRec2)) {
254         if (getRegOperandSize(OpRec1) != getRegOperandSize(OpRec2))
255           return false;
256       } else if (isMemoryOperand(OpRec1) && isMemoryOperand(OpRec2)) {
257         return false;
258       } else if (isImmediateOperand(OpRec1) && isImmediateOperand(OpRec2)) {
259         if (OpRec1->getValueAsDef("Type") != OpRec2->getValueAsDef("Type"))
260           return false;
261       } else
262         return false;
263     }
264 
265     return true;
266   }
267 
268 private:
269   static inline bool isRegisterOperand(const Record *Rec) {
270     return Rec->isSubClassOf("RegisterClass") ||
271            Rec->isSubClassOf("RegisterOperand");
272   }
273 
274   static inline bool isMemoryOperand(const Record *Rec) {
275     return Rec->isSubClassOf("Operand") &&
276            Rec->getValueAsString("OperandType") == "OPERAND_MEMORY";
277   }
278 
279   static inline bool isImmediateOperand(const Record *Rec) {
280     return Rec->isSubClassOf("Operand") &&
281            Rec->getValueAsString("OperandType") == "OPERAND_IMMEDIATE";
282   }
283 
284   static inline unsigned int getRegOperandSize(const Record *RegRec) {
285     if (RegRec->isSubClassOf("RegisterClass"))
286       return RegRec->getValueAsInt("Alignment");
287     if (RegRec->isSubClassOf("RegisterOperand"))
288       return RegRec->getValueAsDef("RegClass")->getValueAsInt("Alignment");
289 
290     llvm_unreachable("Register operand's size not known!");
291   }
292 };
293 
294 void X86EVEX2VEXTablesEmitter::run(raw_ostream &OS) {
295   emitSourceFileHeader("X86 EVEX2VEX tables", OS);
296 
297   ArrayRef<const CodeGenInstruction *> NumberedInstructions =
298       Target.getInstructionsByEnumValue();
299 
300   for (const CodeGenInstruction *Inst : NumberedInstructions) {
301     // Filter non-X86 instructions.
302     if (!Inst->TheDef->isSubClassOf("X86Inst"))
303       continue;
304 
305     // Add VEX encoded instructions to one of VEXInsts vectors according to
306     // it's opcode.
307     if (Inst->TheDef->getValueAsDef("OpEnc")->getName() == "EncVEX") {
308       uint64_t Opcode = getValueFromBitsInit(Inst->TheDef->
309                                              getValueAsBitsInit("Opcode"));
310       VEXInsts[Opcode].push_back(Inst);
311     }
312     // Add relevant EVEX encoded instructions to EVEXInsts
313     else if (Inst->TheDef->getValueAsDef("OpEnc")->getName() == "EncEVEX" &&
314              !Inst->TheDef->getValueAsBit("hasEVEX_K") &&
315              !Inst->TheDef->getValueAsBit("hasEVEX_B") &&
316              getValueFromBitsInit(Inst->TheDef->
317                                         getValueAsBitsInit("EVEX_LL")) != 2 &&
318              !inExceptionList(Inst))
319       EVEXInsts.push_back(Inst);
320   }
321 
322   for (const CodeGenInstruction *EVEXInst : EVEXInsts) {
323     uint64_t Opcode = getValueFromBitsInit(EVEXInst->TheDef->
324                                            getValueAsBitsInit("Opcode"));
325     // For each EVEX instruction look for a VEX match in the appropriate vector
326     // (instructions with the same opcode) using function object IsMatch.
327     auto Match = llvm::find_if(VEXInsts[Opcode], IsMatch(EVEXInst));
328     if (Match != VEXInsts[Opcode].end()) {
329       const CodeGenInstruction *VEXInst = *Match;
330 
331       // In case a match is found add new entry to the appropriate table
332       switch (getValueFromBitsInit(
333           EVEXInst->TheDef->getValueAsBitsInit("EVEX_LL"))) {
334       case 0:
335         EVEX2VEX128.push_back(std::make_pair(EVEXInst, VEXInst)); // {0,0}
336         break;
337       case 1:
338         EVEX2VEX256.push_back(std::make_pair(EVEXInst, VEXInst)); // {0,1}
339         break;
340       default:
341         llvm_unreachable("Instruction's size not fit for the mapping!");
342       }
343     }
344   }
345 
346   // Print both tables
347   printTable(EVEX2VEX128, OS);
348   printTable(EVEX2VEX256, OS);
349 }
350 }
351 
352 namespace llvm {
353 void EmitX86EVEX2VEXTables(RecordKeeper &RK, raw_ostream &OS) {
354   X86EVEX2VEXTablesEmitter(RK).run(OS);
355 }
356 }
357