1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler Emitter. 11 // It contains the implementation of the disassembler tables. 12 // Documentation for the disassembler emitter in general can be found in 13 // X86DisasemblerEmitter.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "X86DisassemblerTables.h" 18 #include "X86DisassemblerShared.h" 19 #include "llvm/ADT/STLExtras.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include "llvm/Support/Format.h" 22 #include <map> 23 24 using namespace llvm; 25 using namespace X86Disassembler; 26 27 /// stringForContext - Returns a string containing the name of a particular 28 /// InstructionContext, usually for diagnostic purposes. 29 /// 30 /// @param insnContext - The instruction class to transform to a string. 31 /// @return - A statically-allocated string constant that contains the 32 /// name of the instruction class. 33 static inline const char* stringForContext(InstructionContext insnContext) { 34 switch (insnContext) { 35 default: 36 llvm_unreachable("Unhandled instruction class"); 37 #define ENUM_ENTRY(n, r, d) case n: return #n; break; 38 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\ 39 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)\ 40 ENUM_ENTRY(n##_KZ_B, r, d) 41 INSTRUCTION_CONTEXTS 42 #undef ENUM_ENTRY 43 #undef ENUM_ENTRY_K_B 44 } 45 } 46 47 /// stringForOperandType - Like stringForContext, but for OperandTypes. 48 static inline const char* stringForOperandType(OperandType type) { 49 switch (type) { 50 default: 51 llvm_unreachable("Unhandled type"); 52 #define ENUM_ENTRY(i, d) case i: return #i; 53 TYPES 54 #undef ENUM_ENTRY 55 } 56 } 57 58 /// stringForOperandEncoding - like stringForContext, but for 59 /// OperandEncodings. 60 static inline const char* stringForOperandEncoding(OperandEncoding encoding) { 61 switch (encoding) { 62 default: 63 llvm_unreachable("Unhandled encoding"); 64 #define ENUM_ENTRY(i, d) case i: return #i; 65 ENCODINGS 66 #undef ENUM_ENTRY 67 } 68 } 69 70 /// inheritsFrom - Indicates whether all instructions in one class also belong 71 /// to another class. 72 /// 73 /// @param child - The class that may be the subset 74 /// @param parent - The class that may be the superset 75 /// @return - True if child is a subset of parent, false otherwise. 76 static inline bool inheritsFrom(InstructionContext child, 77 InstructionContext parent, 78 bool VEX_LIG = false) { 79 if (child == parent) 80 return true; 81 82 switch (parent) { 83 case IC: 84 return(inheritsFrom(child, IC_64BIT) || 85 inheritsFrom(child, IC_OPSIZE) || 86 inheritsFrom(child, IC_ADSIZE) || 87 inheritsFrom(child, IC_XD) || 88 inheritsFrom(child, IC_XS)); 89 case IC_64BIT: 90 return(inheritsFrom(child, IC_64BIT_REXW) || 91 inheritsFrom(child, IC_64BIT_OPSIZE) || 92 inheritsFrom(child, IC_64BIT_ADSIZE) || 93 inheritsFrom(child, IC_64BIT_XD) || 94 inheritsFrom(child, IC_64BIT_XS)); 95 case IC_OPSIZE: 96 return inheritsFrom(child, IC_64BIT_OPSIZE); 97 case IC_ADSIZE: 98 case IC_64BIT_ADSIZE: 99 return false; 100 case IC_XD: 101 return inheritsFrom(child, IC_64BIT_XD); 102 case IC_XS: 103 return inheritsFrom(child, IC_64BIT_XS); 104 case IC_XD_OPSIZE: 105 return inheritsFrom(child, IC_64BIT_XD_OPSIZE); 106 case IC_XS_OPSIZE: 107 return inheritsFrom(child, IC_64BIT_XS_OPSIZE); 108 case IC_64BIT_REXW: 109 return(inheritsFrom(child, IC_64BIT_REXW_XS) || 110 inheritsFrom(child, IC_64BIT_REXW_XD) || 111 inheritsFrom(child, IC_64BIT_REXW_OPSIZE)); 112 case IC_64BIT_OPSIZE: 113 return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE)); 114 case IC_64BIT_XD: 115 return(inheritsFrom(child, IC_64BIT_REXW_XD)); 116 case IC_64BIT_XS: 117 return(inheritsFrom(child, IC_64BIT_REXW_XS)); 118 case IC_64BIT_XD_OPSIZE: 119 case IC_64BIT_XS_OPSIZE: 120 return false; 121 case IC_64BIT_REXW_XD: 122 case IC_64BIT_REXW_XS: 123 case IC_64BIT_REXW_OPSIZE: 124 return false; 125 case IC_VEX: 126 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W)) || 127 inheritsFrom(child, IC_VEX_W) || 128 (VEX_LIG && inheritsFrom(child, IC_VEX_L)); 129 case IC_VEX_XS: 130 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS)) || 131 inheritsFrom(child, IC_VEX_W_XS) || 132 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS)); 133 case IC_VEX_XD: 134 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD)) || 135 inheritsFrom(child, IC_VEX_W_XD) || 136 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD)); 137 case IC_VEX_OPSIZE: 138 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE)) || 139 inheritsFrom(child, IC_VEX_W_OPSIZE) || 140 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE)); 141 case IC_VEX_W: 142 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W); 143 case IC_VEX_W_XS: 144 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS); 145 case IC_VEX_W_XD: 146 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD); 147 case IC_VEX_W_OPSIZE: 148 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE); 149 case IC_VEX_L: 150 return inheritsFrom(child, IC_VEX_L_W); 151 case IC_VEX_L_XS: 152 return inheritsFrom(child, IC_VEX_L_W_XS); 153 case IC_VEX_L_XD: 154 return inheritsFrom(child, IC_VEX_L_W_XD); 155 case IC_VEX_L_OPSIZE: 156 return inheritsFrom(child, IC_VEX_L_W_OPSIZE); 157 case IC_VEX_L_W: 158 case IC_VEX_L_W_XS: 159 case IC_VEX_L_W_XD: 160 case IC_VEX_L_W_OPSIZE: 161 return false; 162 case IC_EVEX: 163 return inheritsFrom(child, IC_EVEX_W) || 164 inheritsFrom(child, IC_EVEX_L_W); 165 case IC_EVEX_XS: 166 return inheritsFrom(child, IC_EVEX_W_XS) || 167 inheritsFrom(child, IC_EVEX_L_W_XS); 168 case IC_EVEX_XD: 169 return inheritsFrom(child, IC_EVEX_W_XD) || 170 inheritsFrom(child, IC_EVEX_L_W_XD); 171 case IC_EVEX_OPSIZE: 172 return inheritsFrom(child, IC_EVEX_W_OPSIZE) || 173 inheritsFrom(child, IC_EVEX_L_W_OPSIZE); 174 case IC_EVEX_W: 175 case IC_EVEX_W_XS: 176 case IC_EVEX_W_XD: 177 case IC_EVEX_W_OPSIZE: 178 return false; 179 case IC_EVEX_L: 180 case IC_EVEX_L_XS: 181 case IC_EVEX_L_XD: 182 case IC_EVEX_L_OPSIZE: 183 return false; 184 case IC_EVEX_L_W: 185 case IC_EVEX_L_W_XS: 186 case IC_EVEX_L_W_XD: 187 case IC_EVEX_L_W_OPSIZE: 188 return false; 189 case IC_EVEX_L2: 190 case IC_EVEX_L2_XS: 191 case IC_EVEX_L2_XD: 192 case IC_EVEX_L2_OPSIZE: 193 return false; 194 case IC_EVEX_L2_W: 195 case IC_EVEX_L2_W_XS: 196 case IC_EVEX_L2_W_XD: 197 case IC_EVEX_L2_W_OPSIZE: 198 return false; 199 case IC_EVEX_K: 200 return inheritsFrom(child, IC_EVEX_W_K) || 201 inheritsFrom(child, IC_EVEX_L_W_K); 202 case IC_EVEX_XS_K: 203 return inheritsFrom(child, IC_EVEX_W_XS_K) || 204 inheritsFrom(child, IC_EVEX_L_W_XS_K); 205 case IC_EVEX_XD_K: 206 return inheritsFrom(child, IC_EVEX_W_XD_K) || 207 inheritsFrom(child, IC_EVEX_L_W_XD_K); 208 case IC_EVEX_K_B: 209 case IC_EVEX_KZ: 210 return false; 211 case IC_EVEX_XS_KZ: 212 return inheritsFrom(child, IC_EVEX_W_XS_KZ) || 213 inheritsFrom(child, IC_EVEX_L_W_XS_KZ); 214 case IC_EVEX_XD_KZ: 215 return inheritsFrom(child, IC_EVEX_W_XD_KZ) || 216 inheritsFrom(child, IC_EVEX_L_W_XD_KZ); 217 case IC_EVEX_KZ_B: 218 case IC_EVEX_OPSIZE_K: 219 case IC_EVEX_OPSIZE_B: 220 case IC_EVEX_OPSIZE_K_B: 221 case IC_EVEX_OPSIZE_KZ: 222 return false; 223 case IC_EVEX_W_K: 224 case IC_EVEX_W_XS_K: 225 case IC_EVEX_W_XD_K: 226 case IC_EVEX_W_OPSIZE_K: 227 case IC_EVEX_W_OPSIZE_B: 228 case IC_EVEX_W_OPSIZE_K_B: 229 return false; 230 case IC_EVEX_L_K: 231 case IC_EVEX_L_XS_K: 232 case IC_EVEX_L_XD_K: 233 case IC_EVEX_L_OPSIZE_K: 234 case IC_EVEX_L_OPSIZE_B: 235 case IC_EVEX_L_OPSIZE_K_B: 236 return false; 237 case IC_EVEX_W_KZ: 238 case IC_EVEX_W_XS_KZ: 239 case IC_EVEX_W_XD_KZ: 240 case IC_EVEX_W_OPSIZE_KZ: 241 return false; 242 case IC_EVEX_L_KZ: 243 case IC_EVEX_L_XS_KZ: 244 case IC_EVEX_L_XD_KZ: 245 case IC_EVEX_L_OPSIZE_KZ: 246 return false; 247 case IC_EVEX_L_W_K: 248 case IC_EVEX_L_W_XS_K: 249 case IC_EVEX_L_W_XD_K: 250 case IC_EVEX_L_W_OPSIZE_K: 251 case IC_EVEX_L_W_OPSIZE_B: 252 case IC_EVEX_L_W_OPSIZE_K_B: 253 case IC_EVEX_L_W_KZ: 254 case IC_EVEX_L_W_XS_KZ: 255 case IC_EVEX_L_W_XD_KZ: 256 case IC_EVEX_L_W_OPSIZE_KZ: 257 return false; 258 case IC_EVEX_L2_K: 259 case IC_EVEX_L2_B: 260 case IC_EVEX_L2_K_B: 261 case IC_EVEX_L2_KZ_B: 262 case IC_EVEX_L2_XS_K: 263 case IC_EVEX_L2_XS_B: 264 case IC_EVEX_L2_XD_B: 265 case IC_EVEX_L2_XD_K: 266 case IC_EVEX_L2_OPSIZE_K: 267 case IC_EVEX_L2_OPSIZE_B: 268 case IC_EVEX_L2_OPSIZE_K_B: 269 case IC_EVEX_L2_KZ: 270 case IC_EVEX_L2_XS_KZ: 271 case IC_EVEX_L2_XD_KZ: 272 case IC_EVEX_L2_OPSIZE_KZ: 273 case IC_EVEX_L2_OPSIZE_KZ_B: 274 return false; 275 case IC_EVEX_L2_W_K: 276 case IC_EVEX_L2_W_B: 277 case IC_EVEX_L2_W_XS_K: 278 case IC_EVEX_L2_W_XD_K: 279 case IC_EVEX_L2_W_XD_B: 280 case IC_EVEX_L2_W_OPSIZE_K: 281 case IC_EVEX_L2_W_OPSIZE_B: 282 case IC_EVEX_L2_W_OPSIZE_K_B: 283 case IC_EVEX_L2_W_KZ: 284 case IC_EVEX_L2_W_XS_KZ: 285 case IC_EVEX_L2_W_XD_KZ: 286 case IC_EVEX_L2_W_OPSIZE_KZ: 287 case IC_EVEX_L2_W_OPSIZE_KZ_B: 288 return false; 289 default: 290 errs() << "Unknown instruction class: " << 291 stringForContext((InstructionContext)parent) << "\n"; 292 llvm_unreachable("Unknown instruction class"); 293 } 294 } 295 296 /// outranks - Indicates whether, if an instruction has two different applicable 297 /// classes, which class should be preferred when performing decode. This 298 /// imposes a total ordering (ties are resolved toward "lower") 299 /// 300 /// @param upper - The class that may be preferable 301 /// @param lower - The class that may be less preferable 302 /// @return - True if upper is to be preferred, false otherwise. 303 static inline bool outranks(InstructionContext upper, 304 InstructionContext lower) { 305 assert(upper < IC_max); 306 assert(lower < IC_max); 307 308 #define ENUM_ENTRY(n, r, d) r, 309 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) \ 310 ENUM_ENTRY(n##_K_B, r, d) ENUM_ENTRY(n##_KZ_B, r, d) \ 311 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d) 312 static int ranks[IC_max] = { 313 INSTRUCTION_CONTEXTS 314 }; 315 #undef ENUM_ENTRY 316 #undef ENUM_ENTRY_K_B 317 318 return (ranks[upper] > ranks[lower]); 319 } 320 321 /// getDecisionType - Determines whether a ModRM decision with 255 entries can 322 /// be compacted by eliminating redundant information. 323 /// 324 /// @param decision - The decision to be compacted. 325 /// @return - The compactest available representation for the decision. 326 static ModRMDecisionType getDecisionType(ModRMDecision &decision) { 327 bool satisfiesOneEntry = true; 328 bool satisfiesSplitRM = true; 329 bool satisfiesSplitReg = true; 330 bool satisfiesSplitMisc = true; 331 332 for (unsigned index = 0; index < 256; ++index) { 333 if (decision.instructionIDs[index] != decision.instructionIDs[0]) 334 satisfiesOneEntry = false; 335 336 if (((index & 0xc0) == 0xc0) && 337 (decision.instructionIDs[index] != decision.instructionIDs[0xc0])) 338 satisfiesSplitRM = false; 339 340 if (((index & 0xc0) != 0xc0) && 341 (decision.instructionIDs[index] != decision.instructionIDs[0x00])) 342 satisfiesSplitRM = false; 343 344 if (((index & 0xc0) == 0xc0) && 345 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8])) 346 satisfiesSplitReg = false; 347 348 if (((index & 0xc0) != 0xc0) && 349 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38])) 350 satisfiesSplitMisc = false; 351 } 352 353 if (satisfiesOneEntry) 354 return MODRM_ONEENTRY; 355 356 if (satisfiesSplitRM) 357 return MODRM_SPLITRM; 358 359 if (satisfiesSplitReg && satisfiesSplitMisc) 360 return MODRM_SPLITREG; 361 362 if (satisfiesSplitMisc) 363 return MODRM_SPLITMISC; 364 365 return MODRM_FULL; 366 } 367 368 /// stringForDecisionType - Returns a statically-allocated string corresponding 369 /// to a particular decision type. 370 /// 371 /// @param dt - The decision type. 372 /// @return - A pointer to the statically-allocated string (e.g., 373 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY). 374 static const char* stringForDecisionType(ModRMDecisionType dt) { 375 #define ENUM_ENTRY(n) case n: return #n; 376 switch (dt) { 377 default: 378 llvm_unreachable("Unknown decision type"); 379 MODRMTYPES 380 }; 381 #undef ENUM_ENTRY 382 } 383 384 DisassemblerTables::DisassemblerTables() { 385 unsigned i; 386 387 for (i = 0; i < array_lengthof(Tables); i++) { 388 Tables[i] = new ContextDecision; 389 memset(Tables[i], 0, sizeof(ContextDecision)); 390 } 391 392 HasConflicts = false; 393 } 394 395 DisassemblerTables::~DisassemblerTables() { 396 unsigned i; 397 398 for (i = 0; i < array_lengthof(Tables); i++) 399 delete Tables[i]; 400 } 401 402 void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2, 403 unsigned &i1, unsigned &i2, 404 unsigned &ModRMTableNum, 405 ModRMDecision &decision) const { 406 static uint32_t sTableNumber = 0; 407 static uint32_t sEntryNumber = 1; 408 ModRMDecisionType dt = getDecisionType(decision); 409 410 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0) 411 { 412 o2.indent(i2) << "{ /* ModRMDecision */" << "\n"; 413 i2++; 414 415 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n"; 416 o2.indent(i2) << 0 << " /* EmptyTable */\n"; 417 418 i2--; 419 o2.indent(i2) << "}"; 420 return; 421 } 422 423 std::vector<unsigned> ModRMDecision; 424 425 switch (dt) { 426 default: 427 llvm_unreachable("Unknown decision type"); 428 case MODRM_ONEENTRY: 429 ModRMDecision.push_back(decision.instructionIDs[0]); 430 break; 431 case MODRM_SPLITRM: 432 ModRMDecision.push_back(decision.instructionIDs[0x00]); 433 ModRMDecision.push_back(decision.instructionIDs[0xc0]); 434 break; 435 case MODRM_SPLITREG: 436 for (unsigned index = 0; index < 64; index += 8) 437 ModRMDecision.push_back(decision.instructionIDs[index]); 438 for (unsigned index = 0xc0; index < 256; index += 8) 439 ModRMDecision.push_back(decision.instructionIDs[index]); 440 break; 441 case MODRM_SPLITMISC: 442 for (unsigned index = 0; index < 64; index += 8) 443 ModRMDecision.push_back(decision.instructionIDs[index]); 444 for (unsigned index = 0xc0; index < 256; ++index) 445 ModRMDecision.push_back(decision.instructionIDs[index]); 446 break; 447 case MODRM_FULL: 448 for (unsigned index = 0; index < 256; ++index) 449 ModRMDecision.push_back(decision.instructionIDs[index]); 450 break; 451 } 452 453 unsigned &EntryNumber = ModRMTable[ModRMDecision]; 454 if (EntryNumber == 0) { 455 EntryNumber = ModRMTableNum; 456 457 ModRMTableNum += ModRMDecision.size(); 458 o1 << "/* Table" << EntryNumber << " */\n"; 459 i1++; 460 for (std::vector<unsigned>::const_iterator I = ModRMDecision.begin(), 461 E = ModRMDecision.end(); I != E; ++I) { 462 o1.indent(i1 * 2) << format("0x%hx", *I) << ", /* " 463 << InstructionSpecifiers[*I].name << " */\n"; 464 } 465 i1--; 466 } 467 468 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n"; 469 i2++; 470 471 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n"; 472 o2.indent(i2) << EntryNumber << " /* Table" << EntryNumber << " */\n"; 473 474 i2--; 475 o2.indent(i2) << "}"; 476 477 switch (dt) { 478 default: 479 llvm_unreachable("Unknown decision type"); 480 case MODRM_ONEENTRY: 481 sEntryNumber += 1; 482 break; 483 case MODRM_SPLITRM: 484 sEntryNumber += 2; 485 break; 486 case MODRM_SPLITREG: 487 sEntryNumber += 16; 488 break; 489 case MODRM_SPLITMISC: 490 sEntryNumber += 8 + 64; 491 break; 492 case MODRM_FULL: 493 sEntryNumber += 256; 494 break; 495 } 496 497 // We assume that the index can fit into uint16_t. 498 assert(sEntryNumber < 65536U && 499 "Index into ModRMDecision is too large for uint16_t!"); 500 501 ++sTableNumber; 502 } 503 504 void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2, 505 unsigned &i1, unsigned &i2, 506 unsigned &ModRMTableNum, 507 OpcodeDecision &decision) const { 508 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n"; 509 i2++; 510 o2.indent(i2) << "{" << "\n"; 511 i2++; 512 513 for (unsigned index = 0; index < 256; ++index) { 514 o2.indent(i2); 515 516 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n"; 517 518 emitModRMDecision(o1, o2, i1, i2, ModRMTableNum, 519 decision.modRMDecisions[index]); 520 521 if (index < 255) 522 o2 << ","; 523 524 o2 << "\n"; 525 } 526 527 i2--; 528 o2.indent(i2) << "}" << "\n"; 529 i2--; 530 o2.indent(i2) << "}" << "\n"; 531 } 532 533 void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2, 534 unsigned &i1, unsigned &i2, 535 unsigned &ModRMTableNum, 536 ContextDecision &decision, 537 const char* name) const { 538 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n"; 539 i2++; 540 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n"; 541 i2++; 542 543 for (unsigned index = 0; index < IC_max; ++index) { 544 o2.indent(i2) << "/* "; 545 o2 << stringForContext((InstructionContext)index); 546 o2 << " */"; 547 o2 << "\n"; 548 549 emitOpcodeDecision(o1, o2, i1, i2, ModRMTableNum, 550 decision.opcodeDecisions[index]); 551 552 if (index + 1 < IC_max) 553 o2 << ", "; 554 } 555 556 i2--; 557 o2.indent(i2) << "}" << "\n"; 558 i2--; 559 o2.indent(i2) << "};" << "\n"; 560 } 561 562 void DisassemblerTables::emitInstructionInfo(raw_ostream &o, 563 unsigned &i) const { 564 unsigned NumInstructions = InstructionSpecifiers.size(); 565 566 o << "static const struct OperandSpecifier x86OperandSets[][" 567 << X86_MAX_OPERANDS << "] = {\n"; 568 569 typedef std::vector<std::pair<const char *, const char *> > OperandListTy; 570 std::map<OperandListTy, unsigned> OperandSets; 571 572 unsigned OperandSetNum = 0; 573 for (unsigned Index = 0; Index < NumInstructions; ++Index) { 574 OperandListTy OperandList; 575 576 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS; 577 ++OperandIndex) { 578 const char *Encoding = 579 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[Index] 580 .operands[OperandIndex].encoding); 581 const char *Type = 582 stringForOperandType((OperandType)InstructionSpecifiers[Index] 583 .operands[OperandIndex].type); 584 OperandList.push_back(std::make_pair(Encoding, Type)); 585 } 586 unsigned &N = OperandSets[OperandList]; 587 if (N != 0) continue; 588 589 N = ++OperandSetNum; 590 591 o << " { /* " << (OperandSetNum - 1) << " */\n"; 592 for (unsigned i = 0, e = OperandList.size(); i != e; ++i) { 593 o << " { " << OperandList[i].first << ", " 594 << OperandList[i].second << " },\n"; 595 } 596 o << " },\n"; 597 } 598 o << "};" << "\n\n"; 599 600 o.indent(i * 2) << "static const struct InstructionSpecifier "; 601 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n"; 602 603 i++; 604 605 for (unsigned index = 0; index < NumInstructions; ++index) { 606 o.indent(i * 2) << "{ /* " << index << " */" << "\n"; 607 i++; 608 609 OperandListTy OperandList; 610 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS; 611 ++OperandIndex) { 612 const char *Encoding = 613 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[index] 614 .operands[OperandIndex].encoding); 615 const char *Type = 616 stringForOperandType((OperandType)InstructionSpecifiers[index] 617 .operands[OperandIndex].type); 618 OperandList.push_back(std::make_pair(Encoding, Type)); 619 } 620 o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n"; 621 622 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */"; 623 o << "\n"; 624 625 i--; 626 o.indent(i * 2) << "}"; 627 628 if (index + 1 < NumInstructions) 629 o << ","; 630 631 o << "\n"; 632 } 633 634 i--; 635 o.indent(i * 2) << "};" << "\n"; 636 } 637 638 void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const { 639 const unsigned int tableSize = 16384; 640 o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR 641 "[" << tableSize << "] = {\n"; 642 i++; 643 644 for (unsigned index = 0; index < tableSize; ++index) { 645 o.indent(i * 2); 646 647 if (index & ATTR_EVEX) { 648 o << "IC_EVEX"; 649 if (index & ATTR_EVEXL2) 650 o << "_L2"; 651 else if (index & ATTR_EVEXL) 652 o << "_L"; 653 if (index & ATTR_REXW) 654 o << "_W"; 655 if (index & ATTR_OPSIZE) 656 o << "_OPSIZE"; 657 else if (index & ATTR_XD) 658 o << "_XD"; 659 else if (index & ATTR_XS) 660 o << "_XS"; 661 if (index & ATTR_EVEXKZ) 662 o << "_KZ"; 663 else if (index & ATTR_EVEXK) 664 o << "_K"; 665 if (index & ATTR_EVEXB) 666 o << "_B"; 667 } 668 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE)) 669 o << "IC_VEX_L_W_OPSIZE"; 670 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XD)) 671 o << "IC_VEX_L_W_XD"; 672 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XS)) 673 o << "IC_VEX_L_W_XS"; 674 else if ((index & ATTR_VEXL) && (index & ATTR_REXW)) 675 o << "IC_VEX_L_W"; 676 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE)) 677 o << "IC_VEX_L_OPSIZE"; 678 else if ((index & ATTR_VEXL) && (index & ATTR_XD)) 679 o << "IC_VEX_L_XD"; 680 else if ((index & ATTR_VEXL) && (index & ATTR_XS)) 681 o << "IC_VEX_L_XS"; 682 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE)) 683 o << "IC_VEX_W_OPSIZE"; 684 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD)) 685 o << "IC_VEX_W_XD"; 686 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS)) 687 o << "IC_VEX_W_XS"; 688 else if (index & ATTR_VEXL) 689 o << "IC_VEX_L"; 690 else if ((index & ATTR_VEX) && (index & ATTR_REXW)) 691 o << "IC_VEX_W"; 692 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE)) 693 o << "IC_VEX_OPSIZE"; 694 else if ((index & ATTR_VEX) && (index & ATTR_XD)) 695 o << "IC_VEX_XD"; 696 else if ((index & ATTR_VEX) && (index & ATTR_XS)) 697 o << "IC_VEX_XS"; 698 else if (index & ATTR_VEX) 699 o << "IC_VEX"; 700 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS)) 701 o << "IC_64BIT_REXW_XS"; 702 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD)) 703 o << "IC_64BIT_REXW_XD"; 704 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && 705 (index & ATTR_OPSIZE)) 706 o << "IC_64BIT_REXW_OPSIZE"; 707 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE)) 708 o << "IC_64BIT_XD_OPSIZE"; 709 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE)) 710 o << "IC_64BIT_XS_OPSIZE"; 711 else if ((index & ATTR_64BIT) && (index & ATTR_XS)) 712 o << "IC_64BIT_XS"; 713 else if ((index & ATTR_64BIT) && (index & ATTR_XD)) 714 o << "IC_64BIT_XD"; 715 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE)) 716 o << "IC_64BIT_OPSIZE"; 717 else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE)) 718 o << "IC_64BIT_ADSIZE"; 719 else if ((index & ATTR_64BIT) && (index & ATTR_REXW)) 720 o << "IC_64BIT_REXW"; 721 else if ((index & ATTR_64BIT)) 722 o << "IC_64BIT"; 723 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE)) 724 o << "IC_XS_OPSIZE"; 725 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE)) 726 o << "IC_XD_OPSIZE"; 727 else if (index & ATTR_XS) 728 o << "IC_XS"; 729 else if (index & ATTR_XD) 730 o << "IC_XD"; 731 else if (index & ATTR_OPSIZE) 732 o << "IC_OPSIZE"; 733 else if (index & ATTR_ADSIZE) 734 o << "IC_ADSIZE"; 735 else 736 o << "IC"; 737 738 if (index < tableSize - 1) 739 o << ","; 740 else 741 o << " "; 742 743 o << " /* " << index << " */"; 744 745 o << "\n"; 746 } 747 748 i--; 749 o.indent(i * 2) << "};" << "\n"; 750 } 751 752 void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2, 753 unsigned &i1, unsigned &i2, 754 unsigned &ModRMTableNum) const { 755 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[0], ONEBYTE_STR); 756 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[1], TWOBYTE_STR); 757 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[2], THREEBYTE38_STR); 758 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[3], THREEBYTE3A_STR); 759 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[4], XOP8_MAP_STR); 760 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[5], XOP9_MAP_STR); 761 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[6], XOPA_MAP_STR); 762 } 763 764 void DisassemblerTables::emit(raw_ostream &o) const { 765 unsigned i1 = 0; 766 unsigned i2 = 0; 767 768 std::string s1; 769 std::string s2; 770 771 raw_string_ostream o1(s1); 772 raw_string_ostream o2(s2); 773 774 emitInstructionInfo(o, i2); 775 o << "\n"; 776 777 emitContextTable(o, i2); 778 o << "\n"; 779 780 unsigned ModRMTableNum = 0; 781 782 o << "static const InstrUID modRMTable[] = {\n"; 783 i1++; 784 std::vector<unsigned> EmptyTable(1, 0); 785 ModRMTable[EmptyTable] = ModRMTableNum; 786 ModRMTableNum += EmptyTable.size(); 787 o1 << "/* EmptyTable */\n"; 788 o1.indent(i1 * 2) << "0x0,\n"; 789 i1--; 790 emitContextDecisions(o1, o2, i1, i2, ModRMTableNum); 791 792 o << o1.str(); 793 o << " 0x0\n"; 794 o << "};\n"; 795 o << "\n"; 796 o << o2.str(); 797 o << "\n"; 798 o << "\n"; 799 } 800 801 void DisassemblerTables::setTableFields(ModRMDecision &decision, 802 const ModRMFilter &filter, 803 InstrUID uid, 804 uint8_t opcode) { 805 for (unsigned index = 0; index < 256; ++index) { 806 if (filter.accepts(index)) { 807 if (decision.instructionIDs[index] == uid) 808 continue; 809 810 if (decision.instructionIDs[index] != 0) { 811 InstructionSpecifier &newInfo = 812 InstructionSpecifiers[uid]; 813 InstructionSpecifier &previousInfo = 814 InstructionSpecifiers[decision.instructionIDs[index]]; 815 816 // Instructions such as MOV8ao8 and MOV8ao8_16 differ only in the 817 // presence of the AdSize prefix. However, the disassembler doesn't 818 // care about that difference in the instruction definition; it 819 // handles 16-bit vs. 32-bit addressing for itself based purely 820 // on the 0x67 prefix and the CPU mode. So there's no need to 821 // disambiguate between them; just let them conflict/coexist. 822 if (previousInfo.name + "_16" == newInfo.name) 823 continue; 824 825 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" || 826 newInfo.name == "XCHG32ar" || 827 newInfo.name == "XCHG32ar64" || 828 newInfo.name == "XCHG64ar")) 829 continue; // special case for XCHG*ar and NOOP 830 831 if (outranks(previousInfo.insnContext, newInfo.insnContext)) 832 continue; 833 834 if (previousInfo.insnContext == newInfo.insnContext) { 835 errs() << "Error: Primary decode conflict: "; 836 errs() << newInfo.name << " would overwrite " << previousInfo.name; 837 errs() << "\n"; 838 errs() << "ModRM " << index << "\n"; 839 errs() << "Opcode " << (uint16_t)opcode << "\n"; 840 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n"; 841 HasConflicts = true; 842 } 843 } 844 845 decision.instructionIDs[index] = uid; 846 } 847 } 848 } 849 850 void DisassemblerTables::setTableFields(OpcodeType type, 851 InstructionContext insnContext, 852 uint8_t opcode, 853 const ModRMFilter &filter, 854 InstrUID uid, 855 bool is32bit, 856 bool ignoresVEX_L) { 857 ContextDecision &decision = *Tables[type]; 858 859 for (unsigned index = 0; index < IC_max; ++index) { 860 if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT)) 861 continue; 862 863 if (inheritsFrom((InstructionContext)index, 864 InstructionSpecifiers[uid].insnContext, ignoresVEX_L)) 865 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode], 866 filter, 867 uid, 868 opcode); 869 } 870 } 871