1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler Emitter. 11 // It contains the implementation of the disassembler tables. 12 // Documentation for the disassembler emitter in general can be found in 13 // X86DisasemblerEmitter.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "X86DisassemblerTables.h" 18 #include "X86DisassemblerShared.h" 19 #include "llvm/ADT/STLExtras.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include "llvm/Support/Format.h" 22 #include <map> 23 24 using namespace llvm; 25 using namespace X86Disassembler; 26 27 /// stringForContext - Returns a string containing the name of a particular 28 /// InstructionContext, usually for diagnostic purposes. 29 /// 30 /// @param insnContext - The instruction class to transform to a string. 31 /// @return - A statically-allocated string constant that contains the 32 /// name of the instruction class. 33 static inline const char* stringForContext(InstructionContext insnContext) { 34 switch (insnContext) { 35 default: 36 llvm_unreachable("Unhandled instruction class"); 37 #define ENUM_ENTRY(n, r, d) case n: return #n; break; 38 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\ 39 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)\ 40 ENUM_ENTRY(n##_KZ_B, r, d) 41 INSTRUCTION_CONTEXTS 42 #undef ENUM_ENTRY 43 #undef ENUM_ENTRY_K_B 44 } 45 } 46 47 /// stringForOperandType - Like stringForContext, but for OperandTypes. 48 static inline const char* stringForOperandType(OperandType type) { 49 switch (type) { 50 default: 51 llvm_unreachable("Unhandled type"); 52 #define ENUM_ENTRY(i, d) case i: return #i; 53 TYPES 54 #undef ENUM_ENTRY 55 } 56 } 57 58 /// stringForOperandEncoding - like stringForContext, but for 59 /// OperandEncodings. 60 static inline const char* stringForOperandEncoding(OperandEncoding encoding) { 61 switch (encoding) { 62 default: 63 llvm_unreachable("Unhandled encoding"); 64 #define ENUM_ENTRY(i, d) case i: return #i; 65 ENCODINGS 66 #undef ENUM_ENTRY 67 } 68 } 69 70 /// inheritsFrom - Indicates whether all instructions in one class also belong 71 /// to another class. 72 /// 73 /// @param child - The class that may be the subset 74 /// @param parent - The class that may be the superset 75 /// @return - True if child is a subset of parent, false otherwise. 76 static inline bool inheritsFrom(InstructionContext child, 77 InstructionContext parent, 78 bool VEX_LIG = false) { 79 if (child == parent) 80 return true; 81 82 switch (parent) { 83 case IC: 84 return(inheritsFrom(child, IC_64BIT) || 85 inheritsFrom(child, IC_OPSIZE) || 86 inheritsFrom(child, IC_ADSIZE) || 87 inheritsFrom(child, IC_XD) || 88 inheritsFrom(child, IC_XS)); 89 case IC_64BIT: 90 return(inheritsFrom(child, IC_64BIT_REXW) || 91 inheritsFrom(child, IC_64BIT_OPSIZE) || 92 inheritsFrom(child, IC_64BIT_ADSIZE) || 93 inheritsFrom(child, IC_64BIT_XD) || 94 inheritsFrom(child, IC_64BIT_XS)); 95 case IC_OPSIZE: 96 return inheritsFrom(child, IC_64BIT_OPSIZE); 97 case IC_ADSIZE: 98 case IC_64BIT_ADSIZE: 99 return false; 100 case IC_XD: 101 return inheritsFrom(child, IC_64BIT_XD); 102 case IC_XS: 103 return inheritsFrom(child, IC_64BIT_XS); 104 case IC_XD_OPSIZE: 105 return inheritsFrom(child, IC_64BIT_XD_OPSIZE); 106 case IC_XS_OPSIZE: 107 return inheritsFrom(child, IC_64BIT_XS_OPSIZE); 108 case IC_64BIT_REXW: 109 return(inheritsFrom(child, IC_64BIT_REXW_XS) || 110 inheritsFrom(child, IC_64BIT_REXW_XD) || 111 inheritsFrom(child, IC_64BIT_REXW_OPSIZE)); 112 case IC_64BIT_OPSIZE: 113 return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE)); 114 case IC_64BIT_XD: 115 return(inheritsFrom(child, IC_64BIT_REXW_XD)); 116 case IC_64BIT_XS: 117 return(inheritsFrom(child, IC_64BIT_REXW_XS)); 118 case IC_64BIT_XD_OPSIZE: 119 case IC_64BIT_XS_OPSIZE: 120 return false; 121 case IC_64BIT_REXW_XD: 122 case IC_64BIT_REXW_XS: 123 case IC_64BIT_REXW_OPSIZE: 124 return false; 125 case IC_VEX: 126 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W)) || 127 inheritsFrom(child, IC_VEX_W) || 128 (VEX_LIG && inheritsFrom(child, IC_VEX_L)); 129 case IC_VEX_XS: 130 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS)) || 131 inheritsFrom(child, IC_VEX_W_XS) || 132 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS)); 133 case IC_VEX_XD: 134 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD)) || 135 inheritsFrom(child, IC_VEX_W_XD) || 136 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD)); 137 case IC_VEX_OPSIZE: 138 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE)) || 139 inheritsFrom(child, IC_VEX_W_OPSIZE) || 140 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE)); 141 case IC_VEX_W: 142 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W); 143 case IC_VEX_W_XS: 144 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS); 145 case IC_VEX_W_XD: 146 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD); 147 case IC_VEX_W_OPSIZE: 148 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE); 149 case IC_VEX_L: 150 return inheritsFrom(child, IC_VEX_L_W); 151 case IC_VEX_L_XS: 152 return inheritsFrom(child, IC_VEX_L_W_XS); 153 case IC_VEX_L_XD: 154 return inheritsFrom(child, IC_VEX_L_W_XD); 155 case IC_VEX_L_OPSIZE: 156 return inheritsFrom(child, IC_VEX_L_W_OPSIZE); 157 case IC_VEX_L_W: 158 case IC_VEX_L_W_XS: 159 case IC_VEX_L_W_XD: 160 case IC_VEX_L_W_OPSIZE: 161 return false; 162 case IC_EVEX: 163 return inheritsFrom(child, IC_EVEX_W) || 164 inheritsFrom(child, IC_EVEX_L_W); 165 case IC_EVEX_XS: 166 return inheritsFrom(child, IC_EVEX_W_XS) || 167 inheritsFrom(child, IC_EVEX_L_W_XS); 168 case IC_EVEX_XD: 169 return inheritsFrom(child, IC_EVEX_W_XD) || 170 inheritsFrom(child, IC_EVEX_L_W_XD); 171 case IC_EVEX_OPSIZE: 172 return inheritsFrom(child, IC_EVEX_W_OPSIZE) || 173 inheritsFrom(child, IC_EVEX_L_W_OPSIZE); 174 case IC_EVEX_W: 175 case IC_EVEX_W_XS: 176 case IC_EVEX_W_XD: 177 case IC_EVEX_W_OPSIZE: 178 return false; 179 case IC_EVEX_L: 180 case IC_EVEX_L_XS: 181 case IC_EVEX_L_XD: 182 case IC_EVEX_L_OPSIZE: 183 return false; 184 case IC_EVEX_L_W: 185 case IC_EVEX_L_W_XS: 186 case IC_EVEX_L_W_XD: 187 case IC_EVEX_L_W_OPSIZE: 188 return false; 189 case IC_EVEX_L2: 190 case IC_EVEX_L2_XS: 191 case IC_EVEX_L2_XD: 192 case IC_EVEX_L2_OPSIZE: 193 return false; 194 case IC_EVEX_L2_W: 195 case IC_EVEX_L2_W_XS: 196 case IC_EVEX_L2_W_XD: 197 case IC_EVEX_L2_W_OPSIZE: 198 return false; 199 case IC_EVEX_K: 200 return inheritsFrom(child, IC_EVEX_W_K) || 201 inheritsFrom(child, IC_EVEX_L_W_K); 202 case IC_EVEX_XS_K: 203 return inheritsFrom(child, IC_EVEX_W_XS_K) || 204 inheritsFrom(child, IC_EVEX_L_W_XS_K); 205 case IC_EVEX_XD_K: 206 return inheritsFrom(child, IC_EVEX_W_XD_K) || 207 inheritsFrom(child, IC_EVEX_L_W_XD_K); 208 case IC_EVEX_K_B: 209 case IC_EVEX_KZ: 210 return false; 211 case IC_EVEX_XS_KZ: 212 return inheritsFrom(child, IC_EVEX_W_XS_KZ) || 213 inheritsFrom(child, IC_EVEX_L_W_XS_KZ); 214 case IC_EVEX_XD_KZ: 215 return inheritsFrom(child, IC_EVEX_W_XD_KZ) || 216 inheritsFrom(child, IC_EVEX_L_W_XD_KZ); 217 case IC_EVEX_KZ_B: 218 case IC_EVEX_OPSIZE_K: 219 case IC_EVEX_OPSIZE_B: 220 case IC_EVEX_OPSIZE_K_B: 221 case IC_EVEX_OPSIZE_KZ: 222 case IC_EVEX_OPSIZE_KZ_B: 223 return false; 224 case IC_EVEX_W_K: 225 case IC_EVEX_W_XS_K: 226 case IC_EVEX_W_XD_K: 227 case IC_EVEX_W_OPSIZE_K: 228 case IC_EVEX_W_OPSIZE_B: 229 case IC_EVEX_W_OPSIZE_K_B: 230 return false; 231 case IC_EVEX_L_K: 232 case IC_EVEX_L_XS_K: 233 case IC_EVEX_L_XD_K: 234 case IC_EVEX_L_OPSIZE_K: 235 case IC_EVEX_L_OPSIZE_B: 236 case IC_EVEX_L_OPSIZE_K_B: 237 return false; 238 case IC_EVEX_W_KZ: 239 case IC_EVEX_W_XS_KZ: 240 case IC_EVEX_W_XD_KZ: 241 case IC_EVEX_W_OPSIZE_KZ: 242 case IC_EVEX_W_OPSIZE_KZ_B: 243 return false; 244 case IC_EVEX_L_KZ: 245 case IC_EVEX_L_XS_KZ: 246 case IC_EVEX_L_XD_KZ: 247 case IC_EVEX_L_OPSIZE_KZ: 248 case IC_EVEX_L_OPSIZE_KZ_B: 249 return false; 250 case IC_EVEX_L_W_K: 251 case IC_EVEX_L_W_XS_K: 252 case IC_EVEX_L_W_XD_K: 253 case IC_EVEX_L_W_OPSIZE_K: 254 case IC_EVEX_L_W_OPSIZE_B: 255 case IC_EVEX_L_W_OPSIZE_K_B: 256 case IC_EVEX_L_W_KZ: 257 case IC_EVEX_L_W_XS_KZ: 258 case IC_EVEX_L_W_XD_KZ: 259 case IC_EVEX_L_W_OPSIZE_KZ: 260 case IC_EVEX_L_W_OPSIZE_KZ_B: 261 return false; 262 case IC_EVEX_L2_K: 263 case IC_EVEX_L2_B: 264 case IC_EVEX_L2_K_B: 265 case IC_EVEX_L2_KZ_B: 266 case IC_EVEX_L2_XS_K: 267 case IC_EVEX_L2_XS_B: 268 case IC_EVEX_L2_XD_B: 269 case IC_EVEX_L2_XD_K: 270 case IC_EVEX_L2_OPSIZE_K: 271 case IC_EVEX_L2_OPSIZE_B: 272 case IC_EVEX_L2_OPSIZE_K_B: 273 case IC_EVEX_L2_KZ: 274 case IC_EVEX_L2_XS_KZ: 275 case IC_EVEX_L2_XD_KZ: 276 case IC_EVEX_L2_OPSIZE_KZ: 277 case IC_EVEX_L2_OPSIZE_KZ_B: 278 return false; 279 case IC_EVEX_L2_W_K: 280 case IC_EVEX_L2_W_B: 281 case IC_EVEX_L2_W_XS_K: 282 case IC_EVEX_L2_W_XD_K: 283 case IC_EVEX_L2_W_XD_B: 284 case IC_EVEX_L2_W_OPSIZE_K: 285 case IC_EVEX_L2_W_OPSIZE_B: 286 case IC_EVEX_L2_W_OPSIZE_K_B: 287 case IC_EVEX_L2_W_KZ: 288 case IC_EVEX_L2_W_XS_KZ: 289 case IC_EVEX_L2_W_XD_KZ: 290 case IC_EVEX_L2_W_OPSIZE_KZ: 291 case IC_EVEX_L2_W_OPSIZE_KZ_B: 292 return false; 293 default: 294 errs() << "Unknown instruction class: " << 295 stringForContext((InstructionContext)parent) << "\n"; 296 llvm_unreachable("Unknown instruction class"); 297 } 298 } 299 300 /// outranks - Indicates whether, if an instruction has two different applicable 301 /// classes, which class should be preferred when performing decode. This 302 /// imposes a total ordering (ties are resolved toward "lower") 303 /// 304 /// @param upper - The class that may be preferable 305 /// @param lower - The class that may be less preferable 306 /// @return - True if upper is to be preferred, false otherwise. 307 static inline bool outranks(InstructionContext upper, 308 InstructionContext lower) { 309 assert(upper < IC_max); 310 assert(lower < IC_max); 311 312 #define ENUM_ENTRY(n, r, d) r, 313 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) \ 314 ENUM_ENTRY(n##_K_B, r, d) ENUM_ENTRY(n##_KZ_B, r, d) \ 315 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d) 316 static int ranks[IC_max] = { 317 INSTRUCTION_CONTEXTS 318 }; 319 #undef ENUM_ENTRY 320 #undef ENUM_ENTRY_K_B 321 322 return (ranks[upper] > ranks[lower]); 323 } 324 325 /// getDecisionType - Determines whether a ModRM decision with 255 entries can 326 /// be compacted by eliminating redundant information. 327 /// 328 /// @param decision - The decision to be compacted. 329 /// @return - The compactest available representation for the decision. 330 static ModRMDecisionType getDecisionType(ModRMDecision &decision) { 331 bool satisfiesOneEntry = true; 332 bool satisfiesSplitRM = true; 333 bool satisfiesSplitReg = true; 334 bool satisfiesSplitMisc = true; 335 336 for (unsigned index = 0; index < 256; ++index) { 337 if (decision.instructionIDs[index] != decision.instructionIDs[0]) 338 satisfiesOneEntry = false; 339 340 if (((index & 0xc0) == 0xc0) && 341 (decision.instructionIDs[index] != decision.instructionIDs[0xc0])) 342 satisfiesSplitRM = false; 343 344 if (((index & 0xc0) != 0xc0) && 345 (decision.instructionIDs[index] != decision.instructionIDs[0x00])) 346 satisfiesSplitRM = false; 347 348 if (((index & 0xc0) == 0xc0) && 349 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8])) 350 satisfiesSplitReg = false; 351 352 if (((index & 0xc0) != 0xc0) && 353 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38])) 354 satisfiesSplitMisc = false; 355 } 356 357 if (satisfiesOneEntry) 358 return MODRM_ONEENTRY; 359 360 if (satisfiesSplitRM) 361 return MODRM_SPLITRM; 362 363 if (satisfiesSplitReg && satisfiesSplitMisc) 364 return MODRM_SPLITREG; 365 366 if (satisfiesSplitMisc) 367 return MODRM_SPLITMISC; 368 369 return MODRM_FULL; 370 } 371 372 /// stringForDecisionType - Returns a statically-allocated string corresponding 373 /// to a particular decision type. 374 /// 375 /// @param dt - The decision type. 376 /// @return - A pointer to the statically-allocated string (e.g., 377 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY). 378 static const char* stringForDecisionType(ModRMDecisionType dt) { 379 #define ENUM_ENTRY(n) case n: return #n; 380 switch (dt) { 381 default: 382 llvm_unreachable("Unknown decision type"); 383 MODRMTYPES 384 }; 385 #undef ENUM_ENTRY 386 } 387 388 DisassemblerTables::DisassemblerTables() { 389 unsigned i; 390 391 for (i = 0; i < array_lengthof(Tables); i++) { 392 Tables[i] = new ContextDecision; 393 memset(Tables[i], 0, sizeof(ContextDecision)); 394 } 395 396 HasConflicts = false; 397 } 398 399 DisassemblerTables::~DisassemblerTables() { 400 unsigned i; 401 402 for (i = 0; i < array_lengthof(Tables); i++) 403 delete Tables[i]; 404 } 405 406 void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2, 407 unsigned &i1, unsigned &i2, 408 unsigned &ModRMTableNum, 409 ModRMDecision &decision) const { 410 static uint32_t sTableNumber = 0; 411 static uint32_t sEntryNumber = 1; 412 ModRMDecisionType dt = getDecisionType(decision); 413 414 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0) 415 { 416 o2.indent(i2) << "{ /* ModRMDecision */" << "\n"; 417 i2++; 418 419 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n"; 420 o2.indent(i2) << 0 << " /* EmptyTable */\n"; 421 422 i2--; 423 o2.indent(i2) << "}"; 424 return; 425 } 426 427 std::vector<unsigned> ModRMDecision; 428 429 switch (dt) { 430 default: 431 llvm_unreachable("Unknown decision type"); 432 case MODRM_ONEENTRY: 433 ModRMDecision.push_back(decision.instructionIDs[0]); 434 break; 435 case MODRM_SPLITRM: 436 ModRMDecision.push_back(decision.instructionIDs[0x00]); 437 ModRMDecision.push_back(decision.instructionIDs[0xc0]); 438 break; 439 case MODRM_SPLITREG: 440 for (unsigned index = 0; index < 64; index += 8) 441 ModRMDecision.push_back(decision.instructionIDs[index]); 442 for (unsigned index = 0xc0; index < 256; index += 8) 443 ModRMDecision.push_back(decision.instructionIDs[index]); 444 break; 445 case MODRM_SPLITMISC: 446 for (unsigned index = 0; index < 64; index += 8) 447 ModRMDecision.push_back(decision.instructionIDs[index]); 448 for (unsigned index = 0xc0; index < 256; ++index) 449 ModRMDecision.push_back(decision.instructionIDs[index]); 450 break; 451 case MODRM_FULL: 452 for (unsigned index = 0; index < 256; ++index) 453 ModRMDecision.push_back(decision.instructionIDs[index]); 454 break; 455 } 456 457 unsigned &EntryNumber = ModRMTable[ModRMDecision]; 458 if (EntryNumber == 0) { 459 EntryNumber = ModRMTableNum; 460 461 ModRMTableNum += ModRMDecision.size(); 462 o1 << "/* Table" << EntryNumber << " */\n"; 463 i1++; 464 for (std::vector<unsigned>::const_iterator I = ModRMDecision.begin(), 465 E = ModRMDecision.end(); I != E; ++I) { 466 o1.indent(i1 * 2) << format("0x%hx", *I) << ", /* " 467 << InstructionSpecifiers[*I].name << " */\n"; 468 } 469 i1--; 470 } 471 472 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n"; 473 i2++; 474 475 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n"; 476 o2.indent(i2) << EntryNumber << " /* Table" << EntryNumber << " */\n"; 477 478 i2--; 479 o2.indent(i2) << "}"; 480 481 switch (dt) { 482 default: 483 llvm_unreachable("Unknown decision type"); 484 case MODRM_ONEENTRY: 485 sEntryNumber += 1; 486 break; 487 case MODRM_SPLITRM: 488 sEntryNumber += 2; 489 break; 490 case MODRM_SPLITREG: 491 sEntryNumber += 16; 492 break; 493 case MODRM_SPLITMISC: 494 sEntryNumber += 8 + 64; 495 break; 496 case MODRM_FULL: 497 sEntryNumber += 256; 498 break; 499 } 500 501 // We assume that the index can fit into uint16_t. 502 assert(sEntryNumber < 65536U && 503 "Index into ModRMDecision is too large for uint16_t!"); 504 505 ++sTableNumber; 506 } 507 508 void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2, 509 unsigned &i1, unsigned &i2, 510 unsigned &ModRMTableNum, 511 OpcodeDecision &decision) const { 512 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n"; 513 i2++; 514 o2.indent(i2) << "{" << "\n"; 515 i2++; 516 517 for (unsigned index = 0; index < 256; ++index) { 518 o2.indent(i2); 519 520 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n"; 521 522 emitModRMDecision(o1, o2, i1, i2, ModRMTableNum, 523 decision.modRMDecisions[index]); 524 525 if (index < 255) 526 o2 << ","; 527 528 o2 << "\n"; 529 } 530 531 i2--; 532 o2.indent(i2) << "}" << "\n"; 533 i2--; 534 o2.indent(i2) << "}" << "\n"; 535 } 536 537 void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2, 538 unsigned &i1, unsigned &i2, 539 unsigned &ModRMTableNum, 540 ContextDecision &decision, 541 const char* name) const { 542 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n"; 543 i2++; 544 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n"; 545 i2++; 546 547 for (unsigned index = 0; index < IC_max; ++index) { 548 o2.indent(i2) << "/* "; 549 o2 << stringForContext((InstructionContext)index); 550 o2 << " */"; 551 o2 << "\n"; 552 553 emitOpcodeDecision(o1, o2, i1, i2, ModRMTableNum, 554 decision.opcodeDecisions[index]); 555 556 if (index + 1 < IC_max) 557 o2 << ", "; 558 } 559 560 i2--; 561 o2.indent(i2) << "}" << "\n"; 562 i2--; 563 o2.indent(i2) << "};" << "\n"; 564 } 565 566 void DisassemblerTables::emitInstructionInfo(raw_ostream &o, 567 unsigned &i) const { 568 unsigned NumInstructions = InstructionSpecifiers.size(); 569 570 o << "static const struct OperandSpecifier x86OperandSets[][" 571 << X86_MAX_OPERANDS << "] = {\n"; 572 573 typedef std::vector<std::pair<const char *, const char *> > OperandListTy; 574 std::map<OperandListTy, unsigned> OperandSets; 575 576 unsigned OperandSetNum = 0; 577 for (unsigned Index = 0; Index < NumInstructions; ++Index) { 578 OperandListTy OperandList; 579 580 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS; 581 ++OperandIndex) { 582 const char *Encoding = 583 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[Index] 584 .operands[OperandIndex].encoding); 585 const char *Type = 586 stringForOperandType((OperandType)InstructionSpecifiers[Index] 587 .operands[OperandIndex].type); 588 OperandList.push_back(std::make_pair(Encoding, Type)); 589 } 590 unsigned &N = OperandSets[OperandList]; 591 if (N != 0) continue; 592 593 N = ++OperandSetNum; 594 595 o << " { /* " << (OperandSetNum - 1) << " */\n"; 596 for (unsigned i = 0, e = OperandList.size(); i != e; ++i) { 597 o << " { " << OperandList[i].first << ", " 598 << OperandList[i].second << " },\n"; 599 } 600 o << " },\n"; 601 } 602 o << "};" << "\n\n"; 603 604 o.indent(i * 2) << "static const struct InstructionSpecifier "; 605 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n"; 606 607 i++; 608 609 for (unsigned index = 0; index < NumInstructions; ++index) { 610 o.indent(i * 2) << "{ /* " << index << " */" << "\n"; 611 i++; 612 613 OperandListTy OperandList; 614 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS; 615 ++OperandIndex) { 616 const char *Encoding = 617 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[index] 618 .operands[OperandIndex].encoding); 619 const char *Type = 620 stringForOperandType((OperandType)InstructionSpecifiers[index] 621 .operands[OperandIndex].type); 622 OperandList.push_back(std::make_pair(Encoding, Type)); 623 } 624 o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n"; 625 626 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */"; 627 o << "\n"; 628 629 i--; 630 o.indent(i * 2) << "}"; 631 632 if (index + 1 < NumInstructions) 633 o << ","; 634 635 o << "\n"; 636 } 637 638 i--; 639 o.indent(i * 2) << "};" << "\n"; 640 } 641 642 void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const { 643 const unsigned int tableSize = 16384; 644 o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR 645 "[" << tableSize << "] = {\n"; 646 i++; 647 648 for (unsigned index = 0; index < tableSize; ++index) { 649 o.indent(i * 2); 650 651 if (index & ATTR_EVEX) { 652 o << "IC_EVEX"; 653 if (index & ATTR_EVEXL2) 654 o << "_L2"; 655 else if (index & ATTR_EVEXL) 656 o << "_L"; 657 if (index & ATTR_REXW) 658 o << "_W"; 659 if (index & ATTR_OPSIZE) 660 o << "_OPSIZE"; 661 else if (index & ATTR_XD) 662 o << "_XD"; 663 else if (index & ATTR_XS) 664 o << "_XS"; 665 if (index & ATTR_EVEXKZ) 666 o << "_KZ"; 667 else if (index & ATTR_EVEXK) 668 o << "_K"; 669 if (index & ATTR_EVEXB) 670 o << "_B"; 671 } 672 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE)) 673 o << "IC_VEX_L_W_OPSIZE"; 674 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XD)) 675 o << "IC_VEX_L_W_XD"; 676 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XS)) 677 o << "IC_VEX_L_W_XS"; 678 else if ((index & ATTR_VEXL) && (index & ATTR_REXW)) 679 o << "IC_VEX_L_W"; 680 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE)) 681 o << "IC_VEX_L_OPSIZE"; 682 else if ((index & ATTR_VEXL) && (index & ATTR_XD)) 683 o << "IC_VEX_L_XD"; 684 else if ((index & ATTR_VEXL) && (index & ATTR_XS)) 685 o << "IC_VEX_L_XS"; 686 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE)) 687 o << "IC_VEX_W_OPSIZE"; 688 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD)) 689 o << "IC_VEX_W_XD"; 690 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS)) 691 o << "IC_VEX_W_XS"; 692 else if (index & ATTR_VEXL) 693 o << "IC_VEX_L"; 694 else if ((index & ATTR_VEX) && (index & ATTR_REXW)) 695 o << "IC_VEX_W"; 696 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE)) 697 o << "IC_VEX_OPSIZE"; 698 else if ((index & ATTR_VEX) && (index & ATTR_XD)) 699 o << "IC_VEX_XD"; 700 else if ((index & ATTR_VEX) && (index & ATTR_XS)) 701 o << "IC_VEX_XS"; 702 else if (index & ATTR_VEX) 703 o << "IC_VEX"; 704 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS)) 705 o << "IC_64BIT_REXW_XS"; 706 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD)) 707 o << "IC_64BIT_REXW_XD"; 708 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && 709 (index & ATTR_OPSIZE)) 710 o << "IC_64BIT_REXW_OPSIZE"; 711 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE)) 712 o << "IC_64BIT_XD_OPSIZE"; 713 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE)) 714 o << "IC_64BIT_XS_OPSIZE"; 715 else if ((index & ATTR_64BIT) && (index & ATTR_XS)) 716 o << "IC_64BIT_XS"; 717 else if ((index & ATTR_64BIT) && (index & ATTR_XD)) 718 o << "IC_64BIT_XD"; 719 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE)) 720 o << "IC_64BIT_OPSIZE"; 721 else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE)) 722 o << "IC_64BIT_ADSIZE"; 723 else if ((index & ATTR_64BIT) && (index & ATTR_REXW)) 724 o << "IC_64BIT_REXW"; 725 else if ((index & ATTR_64BIT)) 726 o << "IC_64BIT"; 727 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE)) 728 o << "IC_XS_OPSIZE"; 729 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE)) 730 o << "IC_XD_OPSIZE"; 731 else if (index & ATTR_XS) 732 o << "IC_XS"; 733 else if (index & ATTR_XD) 734 o << "IC_XD"; 735 else if (index & ATTR_OPSIZE) 736 o << "IC_OPSIZE"; 737 else if (index & ATTR_ADSIZE) 738 o << "IC_ADSIZE"; 739 else 740 o << "IC"; 741 742 if (index < tableSize - 1) 743 o << ","; 744 else 745 o << " "; 746 747 o << " /* " << index << " */"; 748 749 o << "\n"; 750 } 751 752 i--; 753 o.indent(i * 2) << "};" << "\n"; 754 } 755 756 void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2, 757 unsigned &i1, unsigned &i2, 758 unsigned &ModRMTableNum) const { 759 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[0], ONEBYTE_STR); 760 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[1], TWOBYTE_STR); 761 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[2], THREEBYTE38_STR); 762 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[3], THREEBYTE3A_STR); 763 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[4], XOP8_MAP_STR); 764 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[5], XOP9_MAP_STR); 765 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[6], XOPA_MAP_STR); 766 } 767 768 void DisassemblerTables::emit(raw_ostream &o) const { 769 unsigned i1 = 0; 770 unsigned i2 = 0; 771 772 std::string s1; 773 std::string s2; 774 775 raw_string_ostream o1(s1); 776 raw_string_ostream o2(s2); 777 778 emitInstructionInfo(o, i2); 779 o << "\n"; 780 781 emitContextTable(o, i2); 782 o << "\n"; 783 784 unsigned ModRMTableNum = 0; 785 786 o << "static const InstrUID modRMTable[] = {\n"; 787 i1++; 788 std::vector<unsigned> EmptyTable(1, 0); 789 ModRMTable[EmptyTable] = ModRMTableNum; 790 ModRMTableNum += EmptyTable.size(); 791 o1 << "/* EmptyTable */\n"; 792 o1.indent(i1 * 2) << "0x0,\n"; 793 i1--; 794 emitContextDecisions(o1, o2, i1, i2, ModRMTableNum); 795 796 o << o1.str(); 797 o << " 0x0\n"; 798 o << "};\n"; 799 o << "\n"; 800 o << o2.str(); 801 o << "\n"; 802 o << "\n"; 803 } 804 805 void DisassemblerTables::setTableFields(ModRMDecision &decision, 806 const ModRMFilter &filter, 807 InstrUID uid, 808 uint8_t opcode) { 809 for (unsigned index = 0; index < 256; ++index) { 810 if (filter.accepts(index)) { 811 if (decision.instructionIDs[index] == uid) 812 continue; 813 814 if (decision.instructionIDs[index] != 0) { 815 InstructionSpecifier &newInfo = 816 InstructionSpecifiers[uid]; 817 InstructionSpecifier &previousInfo = 818 InstructionSpecifiers[decision.instructionIDs[index]]; 819 820 // Instructions such as MOV8ao8 and MOV8ao8_16 differ only in the 821 // presence of the AdSize prefix. However, the disassembler doesn't 822 // care about that difference in the instruction definition; it 823 // handles 16-bit vs. 32-bit addressing for itself based purely 824 // on the 0x67 prefix and the CPU mode. So there's no need to 825 // disambiguate between them; just let them conflict/coexist. 826 if (previousInfo.name + "_16" == newInfo.name) 827 continue; 828 829 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" || 830 newInfo.name == "XCHG32ar" || 831 newInfo.name == "XCHG32ar64" || 832 newInfo.name == "XCHG64ar")) 833 continue; // special case for XCHG*ar and NOOP 834 835 if (outranks(previousInfo.insnContext, newInfo.insnContext)) 836 continue; 837 838 if (previousInfo.insnContext == newInfo.insnContext) { 839 errs() << "Error: Primary decode conflict: "; 840 errs() << newInfo.name << " would overwrite " << previousInfo.name; 841 errs() << "\n"; 842 errs() << "ModRM " << index << "\n"; 843 errs() << "Opcode " << (uint16_t)opcode << "\n"; 844 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n"; 845 HasConflicts = true; 846 } 847 } 848 849 decision.instructionIDs[index] = uid; 850 } 851 } 852 } 853 854 void DisassemblerTables::setTableFields(OpcodeType type, 855 InstructionContext insnContext, 856 uint8_t opcode, 857 const ModRMFilter &filter, 858 InstrUID uid, 859 bool is32bit, 860 bool ignoresVEX_L) { 861 ContextDecision &decision = *Tables[type]; 862 863 for (unsigned index = 0; index < IC_max; ++index) { 864 if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT)) 865 continue; 866 867 if (inheritsFrom((InstructionContext)index, 868 InstructionSpecifiers[uid].insnContext, ignoresVEX_L)) 869 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode], 870 filter, 871 uid, 872 opcode); 873 } 874 } 875