1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler Emitter. 11 // It contains the implementation of the disassembler tables. 12 // Documentation for the disassembler emitter in general can be found in 13 // X86DisassemblerEmitter.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "X86DisassemblerTables.h" 18 #include "X86DisassemblerShared.h" 19 #include "llvm/ADT/STLExtras.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include "llvm/Support/Format.h" 22 #include <map> 23 24 using namespace llvm; 25 using namespace X86Disassembler; 26 27 /// stringForContext - Returns a string containing the name of a particular 28 /// InstructionContext, usually for diagnostic purposes. 29 /// 30 /// @param insnContext - The instruction class to transform to a string. 31 /// @return - A statically-allocated string constant that contains the 32 /// name of the instruction class. 33 static inline const char* stringForContext(InstructionContext insnContext) { 34 switch (insnContext) { 35 default: 36 llvm_unreachable("Unhandled instruction class"); 37 #define ENUM_ENTRY(n, r, d) case n: return #n; break; 38 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\ 39 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)\ 40 ENUM_ENTRY(n##_KZ_B, r, d) 41 INSTRUCTION_CONTEXTS 42 #undef ENUM_ENTRY 43 #undef ENUM_ENTRY_K_B 44 } 45 } 46 47 /// stringForOperandType - Like stringForContext, but for OperandTypes. 48 static inline const char* stringForOperandType(OperandType type) { 49 switch (type) { 50 default: 51 llvm_unreachable("Unhandled type"); 52 #define ENUM_ENTRY(i, d) case i: return #i; 53 TYPES 54 #undef ENUM_ENTRY 55 } 56 } 57 58 /// stringForOperandEncoding - like stringForContext, but for 59 /// OperandEncodings. 60 static inline const char* stringForOperandEncoding(OperandEncoding encoding) { 61 switch (encoding) { 62 default: 63 llvm_unreachable("Unhandled encoding"); 64 #define ENUM_ENTRY(i, d) case i: return #i; 65 ENCODINGS 66 #undef ENUM_ENTRY 67 } 68 } 69 70 /// inheritsFrom - Indicates whether all instructions in one class also belong 71 /// to another class. 72 /// 73 /// @param child - The class that may be the subset 74 /// @param parent - The class that may be the superset 75 /// @return - True if child is a subset of parent, false otherwise. 76 static inline bool inheritsFrom(InstructionContext child, 77 InstructionContext parent, bool noPrefix = true, 78 bool VEX_LIG = false, bool VEX_WIG = false, 79 bool AdSize64 = false) { 80 if (child == parent) 81 return true; 82 83 switch (parent) { 84 case IC: 85 return(inheritsFrom(child, IC_64BIT, AdSize64) || 86 (noPrefix && inheritsFrom(child, IC_OPSIZE, noPrefix)) || 87 inheritsFrom(child, IC_ADSIZE) || 88 (noPrefix && inheritsFrom(child, IC_XD, noPrefix)) || 89 (noPrefix && inheritsFrom(child, IC_XS, noPrefix))); 90 case IC_64BIT: 91 return(inheritsFrom(child, IC_64BIT_REXW) || 92 (noPrefix && inheritsFrom(child, IC_64BIT_OPSIZE, noPrefix)) || 93 (!AdSize64 && inheritsFrom(child, IC_64BIT_ADSIZE)) || 94 (noPrefix && inheritsFrom(child, IC_64BIT_XD, noPrefix)) || 95 (noPrefix && inheritsFrom(child, IC_64BIT_XS, noPrefix))); 96 case IC_OPSIZE: 97 return inheritsFrom(child, IC_64BIT_OPSIZE) || 98 inheritsFrom(child, IC_OPSIZE_ADSIZE); 99 case IC_ADSIZE: 100 return (noPrefix && inheritsFrom(child, IC_OPSIZE_ADSIZE, noPrefix)); 101 case IC_OPSIZE_ADSIZE: 102 return false; 103 case IC_64BIT_ADSIZE: 104 return (noPrefix && inheritsFrom(child, IC_64BIT_OPSIZE_ADSIZE, noPrefix)); 105 case IC_64BIT_OPSIZE_ADSIZE: 106 return false; 107 case IC_XD: 108 return inheritsFrom(child, IC_64BIT_XD); 109 case IC_XS: 110 return inheritsFrom(child, IC_64BIT_XS); 111 case IC_XD_OPSIZE: 112 return inheritsFrom(child, IC_64BIT_XD_OPSIZE); 113 case IC_XS_OPSIZE: 114 return inheritsFrom(child, IC_64BIT_XS_OPSIZE); 115 case IC_64BIT_REXW: 116 return((noPrefix && inheritsFrom(child, IC_64BIT_REXW_XS, noPrefix)) || 117 (noPrefix && inheritsFrom(child, IC_64BIT_REXW_XD, noPrefix)) || 118 (noPrefix && inheritsFrom(child, IC_64BIT_REXW_OPSIZE, noPrefix)) || 119 (!AdSize64 && inheritsFrom(child, IC_64BIT_REXW_ADSIZE))); 120 case IC_64BIT_OPSIZE: 121 return inheritsFrom(child, IC_64BIT_REXW_OPSIZE) || 122 (!AdSize64 && inheritsFrom(child, IC_64BIT_OPSIZE_ADSIZE)) || 123 (!AdSize64 && inheritsFrom(child, IC_64BIT_REXW_ADSIZE)); 124 case IC_64BIT_XD: 125 return(inheritsFrom(child, IC_64BIT_REXW_XD)); 126 case IC_64BIT_XS: 127 return(inheritsFrom(child, IC_64BIT_REXW_XS)); 128 case IC_64BIT_XD_OPSIZE: 129 case IC_64BIT_XS_OPSIZE: 130 return false; 131 case IC_64BIT_REXW_XD: 132 case IC_64BIT_REXW_XS: 133 case IC_64BIT_REXW_OPSIZE: 134 case IC_64BIT_REXW_ADSIZE: 135 return false; 136 case IC_VEX: 137 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_VEX_L_W)) || 138 (VEX_WIG && inheritsFrom(child, IC_VEX_W)) || 139 (VEX_LIG && inheritsFrom(child, IC_VEX_L)); 140 case IC_VEX_XS: 141 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_VEX_L_W_XS)) || 142 (VEX_WIG && inheritsFrom(child, IC_VEX_W_XS)) || 143 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS)); 144 case IC_VEX_XD: 145 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_VEX_L_W_XD)) || 146 (VEX_WIG && inheritsFrom(child, IC_VEX_W_XD)) || 147 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD)); 148 case IC_VEX_OPSIZE: 149 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE)) || 150 (VEX_WIG && inheritsFrom(child, IC_VEX_W_OPSIZE)) || 151 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE)); 152 case IC_VEX_W: 153 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W); 154 case IC_VEX_W_XS: 155 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS); 156 case IC_VEX_W_XD: 157 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD); 158 case IC_VEX_W_OPSIZE: 159 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE); 160 case IC_VEX_L: 161 return VEX_WIG && inheritsFrom(child, IC_VEX_L_W); 162 case IC_VEX_L_XS: 163 return VEX_WIG && inheritsFrom(child, IC_VEX_L_W_XS); 164 case IC_VEX_L_XD: 165 return VEX_WIG && inheritsFrom(child, IC_VEX_L_W_XD); 166 case IC_VEX_L_OPSIZE: 167 return VEX_WIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE); 168 case IC_VEX_L_W: 169 case IC_VEX_L_W_XS: 170 case IC_VEX_L_W_XD: 171 case IC_VEX_L_W_OPSIZE: 172 return false; 173 case IC_EVEX: 174 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L_W)) || 175 (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W)) || 176 (VEX_WIG && inheritsFrom(child, IC_EVEX_W)) || 177 (VEX_LIG && inheritsFrom(child, IC_EVEX_L)) || 178 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2)); 179 case IC_EVEX_XS: 180 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_XS)) || 181 (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_XS)) || 182 (VEX_WIG && inheritsFrom(child, IC_EVEX_W_XS)) || 183 (VEX_LIG && inheritsFrom(child, IC_EVEX_L_XS)) || 184 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_XS)); 185 case IC_EVEX_XD: 186 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_XD)) || 187 (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_XD)) || 188 (VEX_WIG && inheritsFrom(child, IC_EVEX_W_XD)) || 189 (VEX_LIG && inheritsFrom(child, IC_EVEX_L_XD)) || 190 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_XD)); 191 case IC_EVEX_OPSIZE: 192 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE)) || 193 (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE)) || 194 (VEX_WIG && inheritsFrom(child, IC_EVEX_W_OPSIZE)) || 195 (VEX_LIG && inheritsFrom(child, IC_EVEX_L_OPSIZE)) || 196 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_OPSIZE)); 197 case IC_EVEX_K: 198 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_K)) || 199 (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_K)) || 200 (VEX_WIG && inheritsFrom(child, IC_EVEX_W_K)) || 201 (VEX_LIG && inheritsFrom(child, IC_EVEX_L_K)) || 202 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_K)); 203 case IC_EVEX_XS_K: 204 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_XS_K)) || 205 (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_XS_K)) || 206 (VEX_WIG && inheritsFrom(child, IC_EVEX_W_XS_K)) || 207 (VEX_LIG && inheritsFrom(child, IC_EVEX_L_XS_K)) || 208 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_XS_K)); 209 case IC_EVEX_XD_K: 210 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_XD_K)) || 211 (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_XD_K)) || 212 (VEX_WIG && inheritsFrom(child, IC_EVEX_W_XD_K)) || 213 (VEX_LIG && inheritsFrom(child, IC_EVEX_L_XD_K)) || 214 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_XD_K)); 215 case IC_EVEX_OPSIZE_K: 216 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE_K)) || 217 (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_K)) || 218 (VEX_WIG && inheritsFrom(child, IC_EVEX_W_OPSIZE_K)) || 219 (VEX_LIG && inheritsFrom(child, IC_EVEX_L_OPSIZE_K)) || 220 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_OPSIZE_K)); 221 case IC_EVEX_KZ: 222 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_KZ)) || 223 (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_KZ)) || 224 (VEX_WIG && inheritsFrom(child, IC_EVEX_W_KZ)) || 225 (VEX_LIG && inheritsFrom(child, IC_EVEX_L_KZ)) || 226 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_KZ)); 227 case IC_EVEX_XS_KZ: 228 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_XS_KZ)) || 229 (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_XS_KZ)) || 230 (VEX_WIG && inheritsFrom(child, IC_EVEX_W_XS_KZ)) || 231 (VEX_LIG && inheritsFrom(child, IC_EVEX_L_XS_KZ)) || 232 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_XS_KZ)); 233 case IC_EVEX_XD_KZ: 234 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_XD_KZ)) || 235 (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_XD_KZ)) || 236 (VEX_WIG && inheritsFrom(child, IC_EVEX_W_XD_KZ)) || 237 (VEX_LIG && inheritsFrom(child, IC_EVEX_L_XD_KZ)) || 238 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_XD_KZ)); 239 case IC_EVEX_OPSIZE_KZ: 240 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE_KZ)) || 241 (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_KZ)) || 242 (VEX_WIG && inheritsFrom(child, IC_EVEX_W_OPSIZE_KZ)) || 243 (VEX_LIG && inheritsFrom(child, IC_EVEX_L_OPSIZE_KZ)) || 244 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_OPSIZE_KZ)); 245 case IC_EVEX_W: 246 return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W)) || 247 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W)); 248 case IC_EVEX_W_XS: 249 return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XS)) || 250 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_XS)); 251 case IC_EVEX_W_XD: 252 return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XD)) || 253 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_XD)); 254 case IC_EVEX_W_OPSIZE: 255 return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE)) || 256 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE)); 257 case IC_EVEX_W_K: 258 return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_K)) || 259 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_K)); 260 case IC_EVEX_W_XS_K: 261 return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XS_K)) || 262 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_XS_K)); 263 case IC_EVEX_W_XD_K: 264 return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XD_K)) || 265 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_XD_K)); 266 case IC_EVEX_W_OPSIZE_K: 267 return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE_K)) || 268 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_K)); 269 case IC_EVEX_W_KZ: 270 return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_KZ)) || 271 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_KZ)); 272 case IC_EVEX_W_XS_KZ: 273 return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XS_KZ)) || 274 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_XS_KZ)); 275 case IC_EVEX_W_XD_KZ: 276 return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XD_KZ)) || 277 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_XD_KZ)); 278 case IC_EVEX_W_OPSIZE_KZ: 279 return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE_KZ)) || 280 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_KZ)); 281 case IC_EVEX_L: 282 return VEX_WIG && inheritsFrom(child, IC_EVEX_L_W); 283 case IC_EVEX_L_XS: 284 return VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_XS); 285 case IC_EVEX_L_XD: 286 return VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_XD); 287 case IC_EVEX_L_OPSIZE: 288 return VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE); 289 case IC_EVEX_L_K: 290 return VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_K); 291 case IC_EVEX_L_XS_K: 292 return VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_XS_K); 293 case IC_EVEX_L_XD_K: 294 return VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_XD_K); 295 case IC_EVEX_L_OPSIZE_K: 296 return VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE_K); 297 case IC_EVEX_L_KZ: 298 return VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_KZ); 299 case IC_EVEX_L_XS_KZ: 300 return VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_XS_KZ); 301 case IC_EVEX_L_XD_KZ: 302 return VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_XD_KZ); 303 case IC_EVEX_L_OPSIZE_KZ: 304 return VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE_KZ); 305 case IC_EVEX_L_W: 306 case IC_EVEX_L_W_XS: 307 case IC_EVEX_L_W_XD: 308 case IC_EVEX_L_W_OPSIZE: 309 return false; 310 case IC_EVEX_L_W_K: 311 case IC_EVEX_L_W_XS_K: 312 case IC_EVEX_L_W_XD_K: 313 case IC_EVEX_L_W_OPSIZE_K: 314 return false; 315 case IC_EVEX_L_W_KZ: 316 case IC_EVEX_L_W_XS_KZ: 317 case IC_EVEX_L_W_XD_KZ: 318 case IC_EVEX_L_W_OPSIZE_KZ: 319 return false; 320 case IC_EVEX_L2: 321 return VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W); 322 case IC_EVEX_L2_XS: 323 return VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_XS); 324 case IC_EVEX_L2_XD: 325 return VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_XD); 326 case IC_EVEX_L2_OPSIZE: 327 return VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE); 328 case IC_EVEX_L2_K: 329 return VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_K); 330 case IC_EVEX_L2_XS_K: 331 return VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_XS_K); 332 case IC_EVEX_L2_XD_K: 333 return VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_XD_K); 334 case IC_EVEX_L2_OPSIZE_K: 335 return VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_K); 336 case IC_EVEX_L2_KZ: 337 return VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_KZ); 338 case IC_EVEX_L2_XS_KZ: 339 return VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_XS_KZ); 340 case IC_EVEX_L2_XD_KZ: 341 return VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_XD_KZ); 342 case IC_EVEX_L2_OPSIZE_KZ: 343 return VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_KZ); 344 case IC_EVEX_L2_W: 345 case IC_EVEX_L2_W_XS: 346 case IC_EVEX_L2_W_XD: 347 case IC_EVEX_L2_W_OPSIZE: 348 return false; 349 case IC_EVEX_L2_W_K: 350 case IC_EVEX_L2_W_XS_K: 351 case IC_EVEX_L2_W_XD_K: 352 case IC_EVEX_L2_W_OPSIZE_K: 353 return false; 354 case IC_EVEX_L2_W_KZ: 355 case IC_EVEX_L2_W_XS_KZ: 356 case IC_EVEX_L2_W_XD_KZ: 357 case IC_EVEX_L2_W_OPSIZE_KZ: 358 return false; 359 case IC_EVEX_B: 360 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_B)) || 361 (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_B)) || 362 (VEX_WIG && inheritsFrom(child, IC_EVEX_W_B)) || 363 (VEX_LIG && inheritsFrom(child, IC_EVEX_L_B)) || 364 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_B)); 365 case IC_EVEX_XS_B: 366 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_XS_B)) || 367 (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_XS_B)) || 368 (VEX_WIG && inheritsFrom(child, IC_EVEX_W_XS_B)) || 369 (VEX_LIG && inheritsFrom(child, IC_EVEX_L_XS_B)) || 370 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_XS_B)); 371 case IC_EVEX_XD_B: 372 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_XD_B)) || 373 (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_XD_B)) || 374 (VEX_WIG && inheritsFrom(child, IC_EVEX_W_XD_B)) || 375 (VEX_LIG && inheritsFrom(child, IC_EVEX_L_XD_B)) || 376 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_XD_B)); 377 case IC_EVEX_OPSIZE_B: 378 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE_B)) || 379 (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_B)) || 380 (VEX_WIG && inheritsFrom(child, IC_EVEX_W_OPSIZE_B)) || 381 (VEX_LIG && inheritsFrom(child, IC_EVEX_L_OPSIZE_B)) || 382 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_OPSIZE_B)); 383 case IC_EVEX_K_B: 384 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_K_B)) || 385 (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_K_B)) || 386 (VEX_WIG && inheritsFrom(child, IC_EVEX_W_K_B)) || 387 (VEX_LIG && inheritsFrom(child, IC_EVEX_L_K_B)) || 388 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_K_B)); 389 case IC_EVEX_XS_K_B: 390 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_XS_K_B)) || 391 (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_XS_K_B)) || 392 (VEX_WIG && inheritsFrom(child, IC_EVEX_W_XS_K_B)) || 393 (VEX_LIG && inheritsFrom(child, IC_EVEX_L_XS_K_B)) || 394 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_XS_K_B)); 395 case IC_EVEX_XD_K_B: 396 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_XD_K_B)) || 397 (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_XD_K_B)) || 398 (VEX_WIG && inheritsFrom(child, IC_EVEX_W_XD_K_B)) || 399 (VEX_LIG && inheritsFrom(child, IC_EVEX_L_XD_K_B)) || 400 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_XD_K_B)); 401 case IC_EVEX_OPSIZE_K_B: 402 return (VEX_LIG && VEX_WIG && 403 inheritsFrom(child, IC_EVEX_L_W_OPSIZE_K_B)) || 404 (VEX_LIG && VEX_WIG && 405 inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_K_B)) || 406 (VEX_WIG && inheritsFrom(child, IC_EVEX_W_OPSIZE_K_B)) || 407 (VEX_LIG && inheritsFrom(child, IC_EVEX_L_OPSIZE_K_B)) || 408 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_OPSIZE_K_B)); 409 case IC_EVEX_KZ_B: 410 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_KZ_B)) || 411 (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_KZ_B)) || 412 (VEX_WIG && inheritsFrom(child, IC_EVEX_W_KZ_B)) || 413 (VEX_LIG && inheritsFrom(child, IC_EVEX_L_KZ_B)) || 414 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_KZ_B)); 415 case IC_EVEX_XS_KZ_B: 416 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_XS_KZ_B)) || 417 (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_XS_KZ_B)) || 418 (VEX_WIG && inheritsFrom(child, IC_EVEX_W_XS_KZ_B)) || 419 (VEX_LIG && inheritsFrom(child, IC_EVEX_L_XS_KZ_B)) || 420 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_XS_KZ_B)); 421 case IC_EVEX_XD_KZ_B: 422 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_XD_KZ_B)) || 423 (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_XD_KZ_B)) || 424 (VEX_WIG && inheritsFrom(child, IC_EVEX_W_XD_KZ_B)) || 425 (VEX_LIG && inheritsFrom(child, IC_EVEX_L_XD_KZ_B)) || 426 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_XD_KZ_B)); 427 case IC_EVEX_OPSIZE_KZ_B: 428 return (VEX_LIG && VEX_WIG && 429 inheritsFrom(child, IC_EVEX_L_W_OPSIZE_KZ_B)) || 430 (VEX_LIG && VEX_WIG && 431 inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_KZ_B)) || 432 (VEX_WIG && inheritsFrom(child, IC_EVEX_W_OPSIZE_KZ_B)) || 433 (VEX_LIG && inheritsFrom(child, IC_EVEX_L_OPSIZE_KZ_B)) || 434 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_OPSIZE_KZ_B)); 435 case IC_EVEX_W_B: 436 return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_B)) || 437 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_B)); 438 case IC_EVEX_W_XS_B: 439 return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XS_B)) || 440 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_XS_B)); 441 case IC_EVEX_W_XD_B: 442 return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XD_B)) || 443 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_XD_B)); 444 case IC_EVEX_W_OPSIZE_B: 445 return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE_B)) || 446 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_B)); 447 case IC_EVEX_W_K_B: 448 return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_K_B)) || 449 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_K_B)); 450 case IC_EVEX_W_XS_K_B: 451 return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XS_K_B)) || 452 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_XS_K_B)); 453 case IC_EVEX_W_XD_K_B: 454 return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XD_K_B)) || 455 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_XD_K_B)); 456 case IC_EVEX_W_OPSIZE_K_B: 457 return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE_K_B)) || 458 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_K_B)); 459 case IC_EVEX_W_KZ_B: 460 return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_KZ_B)) || 461 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_KZ_B)); 462 case IC_EVEX_W_XS_KZ_B: 463 return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XS_KZ_B)) || 464 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_XS_KZ_B)); 465 case IC_EVEX_W_XD_KZ_B: 466 return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XD_KZ_B)) || 467 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_XD_KZ_B)); 468 case IC_EVEX_W_OPSIZE_KZ_B: 469 return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE_KZ_B)) || 470 (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_KZ_B)); 471 case IC_EVEX_L_B: 472 return VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_B); 473 case IC_EVEX_L_XS_B: 474 return VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_XS_B); 475 case IC_EVEX_L_XD_B: 476 return VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_XD_B); 477 case IC_EVEX_L_OPSIZE_B: 478 return VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE_B); 479 case IC_EVEX_L_K_B: 480 return VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_K_B); 481 case IC_EVEX_L_XS_K_B: 482 return VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_XS_K_B); 483 case IC_EVEX_L_XD_K_B: 484 return VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_XD_K_B); 485 case IC_EVEX_L_OPSIZE_K_B: 486 return VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE_K_B); 487 case IC_EVEX_L_KZ_B: 488 return VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_KZ_B); 489 case IC_EVEX_L_XS_KZ_B: 490 return VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_XS_KZ_B); 491 case IC_EVEX_L_XD_KZ_B: 492 return VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_XD_KZ_B); 493 case IC_EVEX_L_OPSIZE_KZ_B: 494 return VEX_WIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE_KZ_B); 495 case IC_EVEX_L_W_B: 496 case IC_EVEX_L_W_XS_B: 497 case IC_EVEX_L_W_XD_B: 498 case IC_EVEX_L_W_OPSIZE_B: 499 return false; 500 case IC_EVEX_L_W_K_B: 501 case IC_EVEX_L_W_XS_K_B: 502 case IC_EVEX_L_W_XD_K_B: 503 case IC_EVEX_L_W_OPSIZE_K_B: 504 return false; 505 case IC_EVEX_L_W_KZ_B: 506 case IC_EVEX_L_W_XS_KZ_B: 507 case IC_EVEX_L_W_XD_KZ_B: 508 case IC_EVEX_L_W_OPSIZE_KZ_B: 509 return false; 510 case IC_EVEX_L2_B: 511 return VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_B); 512 case IC_EVEX_L2_XS_B: 513 return VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_XS_B); 514 case IC_EVEX_L2_XD_B: 515 return VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_XD_B); 516 case IC_EVEX_L2_OPSIZE_B: 517 return VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_B); 518 case IC_EVEX_L2_K_B: 519 return VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_K_B); 520 case IC_EVEX_L2_XS_K_B: 521 return VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_XS_K_B); 522 case IC_EVEX_L2_XD_K_B: 523 return VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_XD_K_B); 524 case IC_EVEX_L2_OPSIZE_K_B: 525 return VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_K_B); 526 case IC_EVEX_L2_KZ_B: 527 return VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_KZ_B); 528 case IC_EVEX_L2_XS_KZ_B: 529 return VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_XS_KZ_B); 530 case IC_EVEX_L2_XD_KZ_B: 531 return VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_XD_KZ_B); 532 case IC_EVEX_L2_OPSIZE_KZ_B: 533 return VEX_WIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_KZ_B); 534 case IC_EVEX_L2_W_B: 535 case IC_EVEX_L2_W_XS_B: 536 case IC_EVEX_L2_W_XD_B: 537 case IC_EVEX_L2_W_OPSIZE_B: 538 return false; 539 case IC_EVEX_L2_W_K_B: 540 case IC_EVEX_L2_W_XS_K_B: 541 case IC_EVEX_L2_W_XD_K_B: 542 case IC_EVEX_L2_W_OPSIZE_K_B: 543 return false; 544 case IC_EVEX_L2_W_KZ_B: 545 case IC_EVEX_L2_W_XS_KZ_B: 546 case IC_EVEX_L2_W_XD_KZ_B: 547 case IC_EVEX_L2_W_OPSIZE_KZ_B: 548 return false; 549 case IC_3DNOW: 550 return false; 551 default: 552 errs() << "Unknown instruction class: " << 553 stringForContext((InstructionContext)parent) << "\n"; 554 llvm_unreachable("Unknown instruction class"); 555 } 556 } 557 558 /// outranks - Indicates whether, if an instruction has two different applicable 559 /// classes, which class should be preferred when performing decode. This 560 /// imposes a total ordering (ties are resolved toward "lower") 561 /// 562 /// @param upper - The class that may be preferable 563 /// @param lower - The class that may be less preferable 564 /// @return - True if upper is to be preferred, false otherwise. 565 static inline bool outranks(InstructionContext upper, 566 InstructionContext lower) { 567 assert(upper < IC_max); 568 assert(lower < IC_max); 569 570 #define ENUM_ENTRY(n, r, d) r, 571 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) \ 572 ENUM_ENTRY(n##_K_B, r, d) ENUM_ENTRY(n##_KZ_B, r, d) \ 573 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d) 574 static int ranks[IC_max] = { 575 INSTRUCTION_CONTEXTS 576 }; 577 #undef ENUM_ENTRY 578 #undef ENUM_ENTRY_K_B 579 580 return (ranks[upper] > ranks[lower]); 581 } 582 583 /// getDecisionType - Determines whether a ModRM decision with 255 entries can 584 /// be compacted by eliminating redundant information. 585 /// 586 /// @param decision - The decision to be compacted. 587 /// @return - The compactest available representation for the decision. 588 static ModRMDecisionType getDecisionType(ModRMDecision &decision) { 589 bool satisfiesOneEntry = true; 590 bool satisfiesSplitRM = true; 591 bool satisfiesSplitReg = true; 592 bool satisfiesSplitMisc = true; 593 594 for (unsigned index = 0; index < 256; ++index) { 595 if (decision.instructionIDs[index] != decision.instructionIDs[0]) 596 satisfiesOneEntry = false; 597 598 if (((index & 0xc0) == 0xc0) && 599 (decision.instructionIDs[index] != decision.instructionIDs[0xc0])) 600 satisfiesSplitRM = false; 601 602 if (((index & 0xc0) != 0xc0) && 603 (decision.instructionIDs[index] != decision.instructionIDs[0x00])) 604 satisfiesSplitRM = false; 605 606 if (((index & 0xc0) == 0xc0) && 607 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8])) 608 satisfiesSplitReg = false; 609 610 if (((index & 0xc0) != 0xc0) && 611 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38])) 612 satisfiesSplitMisc = false; 613 } 614 615 if (satisfiesOneEntry) 616 return MODRM_ONEENTRY; 617 618 if (satisfiesSplitRM) 619 return MODRM_SPLITRM; 620 621 if (satisfiesSplitReg && satisfiesSplitMisc) 622 return MODRM_SPLITREG; 623 624 if (satisfiesSplitMisc) 625 return MODRM_SPLITMISC; 626 627 return MODRM_FULL; 628 } 629 630 /// stringForDecisionType - Returns a statically-allocated string corresponding 631 /// to a particular decision type. 632 /// 633 /// @param dt - The decision type. 634 /// @return - A pointer to the statically-allocated string (e.g., 635 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY). 636 static const char* stringForDecisionType(ModRMDecisionType dt) { 637 #define ENUM_ENTRY(n) case n: return #n; 638 switch (dt) { 639 default: 640 llvm_unreachable("Unknown decision type"); 641 MODRMTYPES 642 }; 643 #undef ENUM_ENTRY 644 } 645 646 DisassemblerTables::DisassemblerTables() { 647 for (unsigned i = 0; i < array_lengthof(Tables); i++) 648 Tables[i] = llvm::make_unique<ContextDecision>(); 649 650 HasConflicts = false; 651 } 652 653 DisassemblerTables::~DisassemblerTables() { 654 } 655 656 void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2, 657 unsigned &i1, unsigned &i2, 658 unsigned &ModRMTableNum, 659 ModRMDecision &decision) const { 660 static uint32_t sTableNumber = 0; 661 static uint32_t sEntryNumber = 1; 662 ModRMDecisionType dt = getDecisionType(decision); 663 664 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0) 665 { 666 o2.indent(i2) << "{ /* ModRMDecision */" << "\n"; 667 i2++; 668 669 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n"; 670 o2.indent(i2) << 0 << " /* EmptyTable */\n"; 671 672 i2--; 673 o2.indent(i2) << "}"; 674 return; 675 } 676 677 std::vector<unsigned> ModRMDecision; 678 679 switch (dt) { 680 default: 681 llvm_unreachable("Unknown decision type"); 682 case MODRM_ONEENTRY: 683 ModRMDecision.push_back(decision.instructionIDs[0]); 684 break; 685 case MODRM_SPLITRM: 686 ModRMDecision.push_back(decision.instructionIDs[0x00]); 687 ModRMDecision.push_back(decision.instructionIDs[0xc0]); 688 break; 689 case MODRM_SPLITREG: 690 for (unsigned index = 0; index < 64; index += 8) 691 ModRMDecision.push_back(decision.instructionIDs[index]); 692 for (unsigned index = 0xc0; index < 256; index += 8) 693 ModRMDecision.push_back(decision.instructionIDs[index]); 694 break; 695 case MODRM_SPLITMISC: 696 for (unsigned index = 0; index < 64; index += 8) 697 ModRMDecision.push_back(decision.instructionIDs[index]); 698 for (unsigned index = 0xc0; index < 256; ++index) 699 ModRMDecision.push_back(decision.instructionIDs[index]); 700 break; 701 case MODRM_FULL: 702 for (unsigned index = 0; index < 256; ++index) 703 ModRMDecision.push_back(decision.instructionIDs[index]); 704 break; 705 } 706 707 unsigned &EntryNumber = ModRMTable[ModRMDecision]; 708 if (EntryNumber == 0) { 709 EntryNumber = ModRMTableNum; 710 711 ModRMTableNum += ModRMDecision.size(); 712 o1 << "/* Table" << EntryNumber << " */\n"; 713 i1++; 714 for (std::vector<unsigned>::const_iterator I = ModRMDecision.begin(), 715 E = ModRMDecision.end(); I != E; ++I) { 716 o1.indent(i1 * 2) << format("0x%hx", *I) << ", /* " 717 << InstructionSpecifiers[*I].name << " */\n"; 718 } 719 i1--; 720 } 721 722 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n"; 723 i2++; 724 725 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n"; 726 o2.indent(i2) << EntryNumber << " /* Table" << EntryNumber << " */\n"; 727 728 i2--; 729 o2.indent(i2) << "}"; 730 731 switch (dt) { 732 default: 733 llvm_unreachable("Unknown decision type"); 734 case MODRM_ONEENTRY: 735 sEntryNumber += 1; 736 break; 737 case MODRM_SPLITRM: 738 sEntryNumber += 2; 739 break; 740 case MODRM_SPLITREG: 741 sEntryNumber += 16; 742 break; 743 case MODRM_SPLITMISC: 744 sEntryNumber += 8 + 64; 745 break; 746 case MODRM_FULL: 747 sEntryNumber += 256; 748 break; 749 } 750 751 // We assume that the index can fit into uint16_t. 752 assert(sEntryNumber < 65536U && 753 "Index into ModRMDecision is too large for uint16_t!"); 754 755 ++sTableNumber; 756 } 757 758 void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2, 759 unsigned &i1, unsigned &i2, 760 unsigned &ModRMTableNum, 761 OpcodeDecision &decision) const { 762 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n"; 763 i2++; 764 o2.indent(i2) << "{" << "\n"; 765 i2++; 766 767 for (unsigned index = 0; index < 256; ++index) { 768 o2.indent(i2); 769 770 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n"; 771 772 emitModRMDecision(o1, o2, i1, i2, ModRMTableNum, 773 decision.modRMDecisions[index]); 774 775 if (index < 255) 776 o2 << ","; 777 778 o2 << "\n"; 779 } 780 781 i2--; 782 o2.indent(i2) << "}" << "\n"; 783 i2--; 784 o2.indent(i2) << "}" << "\n"; 785 } 786 787 void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2, 788 unsigned &i1, unsigned &i2, 789 unsigned &ModRMTableNum, 790 ContextDecision &decision, 791 const char* name) const { 792 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n"; 793 i2++; 794 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n"; 795 i2++; 796 797 for (unsigned index = 0; index < IC_max; ++index) { 798 o2.indent(i2) << "/* "; 799 o2 << stringForContext((InstructionContext)index); 800 o2 << " */"; 801 o2 << "\n"; 802 803 emitOpcodeDecision(o1, o2, i1, i2, ModRMTableNum, 804 decision.opcodeDecisions[index]); 805 806 if (index + 1 < IC_max) 807 o2 << ", "; 808 } 809 810 i2--; 811 o2.indent(i2) << "}" << "\n"; 812 i2--; 813 o2.indent(i2) << "};" << "\n"; 814 } 815 816 void DisassemblerTables::emitInstructionInfo(raw_ostream &o, 817 unsigned &i) const { 818 unsigned NumInstructions = InstructionSpecifiers.size(); 819 820 o << "static const struct OperandSpecifier x86OperandSets[][" 821 << X86_MAX_OPERANDS << "] = {\n"; 822 823 typedef SmallVector<std::pair<OperandEncoding, OperandType>, 824 X86_MAX_OPERANDS> OperandListTy; 825 std::map<OperandListTy, unsigned> OperandSets; 826 827 unsigned OperandSetNum = 0; 828 for (unsigned Index = 0; Index < NumInstructions; ++Index) { 829 OperandListTy OperandList; 830 831 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS; 832 ++OperandIndex) { 833 OperandEncoding Encoding = (OperandEncoding)InstructionSpecifiers[Index] 834 .operands[OperandIndex].encoding; 835 OperandType Type = (OperandType)InstructionSpecifiers[Index] 836 .operands[OperandIndex].type; 837 OperandList.push_back(std::make_pair(Encoding, Type)); 838 } 839 unsigned &N = OperandSets[OperandList]; 840 if (N != 0) continue; 841 842 N = ++OperandSetNum; 843 844 o << " { /* " << (OperandSetNum - 1) << " */\n"; 845 for (unsigned i = 0, e = OperandList.size(); i != e; ++i) { 846 const char *Encoding = stringForOperandEncoding(OperandList[i].first); 847 const char *Type = stringForOperandType(OperandList[i].second); 848 o << " { " << Encoding << ", " << Type << " },\n"; 849 } 850 o << " },\n"; 851 } 852 o << "};" << "\n\n"; 853 854 o.indent(i * 2) << "static const struct InstructionSpecifier "; 855 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n"; 856 857 i++; 858 859 for (unsigned index = 0; index < NumInstructions; ++index) { 860 o.indent(i * 2) << "{ /* " << index << " */\n"; 861 i++; 862 863 OperandListTy OperandList; 864 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS; 865 ++OperandIndex) { 866 OperandEncoding Encoding = (OperandEncoding)InstructionSpecifiers[index] 867 .operands[OperandIndex].encoding; 868 OperandType Type = (OperandType)InstructionSpecifiers[index] 869 .operands[OperandIndex].type; 870 OperandList.push_back(std::make_pair(Encoding, Type)); 871 } 872 o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n"; 873 874 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */\n"; 875 876 i--; 877 o.indent(i * 2) << "},\n"; 878 } 879 880 i--; 881 o.indent(i * 2) << "};" << "\n"; 882 } 883 884 void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const { 885 const unsigned int tableSize = 32768; 886 o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR 887 "[" << tableSize << "] = {\n"; 888 i++; 889 890 for (unsigned index = 0; index < tableSize; ++index) { 891 o.indent(i * 2); 892 893 if (index & ATTR_3DNOW) 894 o << "IC_3DNOW"; 895 else if (index & ATTR_EVEX) { 896 o << "IC_EVEX"; 897 if (index & ATTR_EVEXL2) 898 o << "_L2"; 899 else if (index & ATTR_EVEXL) 900 o << "_L"; 901 if (index & ATTR_REXW) 902 o << "_W"; 903 if (index & ATTR_OPSIZE) 904 o << "_OPSIZE"; 905 else if (index & ATTR_XD) 906 o << "_XD"; 907 else if (index & ATTR_XS) 908 o << "_XS"; 909 if (index & ATTR_EVEXKZ) 910 o << "_KZ"; 911 else if (index & ATTR_EVEXK) 912 o << "_K"; 913 if (index & ATTR_EVEXB) 914 o << "_B"; 915 } 916 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE)) 917 o << "IC_VEX_L_W_OPSIZE"; 918 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XD)) 919 o << "IC_VEX_L_W_XD"; 920 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XS)) 921 o << "IC_VEX_L_W_XS"; 922 else if ((index & ATTR_VEXL) && (index & ATTR_REXW)) 923 o << "IC_VEX_L_W"; 924 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE)) 925 o << "IC_VEX_L_OPSIZE"; 926 else if ((index & ATTR_VEXL) && (index & ATTR_XD)) 927 o << "IC_VEX_L_XD"; 928 else if ((index & ATTR_VEXL) && (index & ATTR_XS)) 929 o << "IC_VEX_L_XS"; 930 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE)) 931 o << "IC_VEX_W_OPSIZE"; 932 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD)) 933 o << "IC_VEX_W_XD"; 934 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS)) 935 o << "IC_VEX_W_XS"; 936 else if (index & ATTR_VEXL) 937 o << "IC_VEX_L"; 938 else if ((index & ATTR_VEX) && (index & ATTR_REXW)) 939 o << "IC_VEX_W"; 940 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE)) 941 o << "IC_VEX_OPSIZE"; 942 else if ((index & ATTR_VEX) && (index & ATTR_XD)) 943 o << "IC_VEX_XD"; 944 else if ((index & ATTR_VEX) && (index & ATTR_XS)) 945 o << "IC_VEX_XS"; 946 else if (index & ATTR_VEX) 947 o << "IC_VEX"; 948 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS)) 949 o << "IC_64BIT_REXW_XS"; 950 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD)) 951 o << "IC_64BIT_REXW_XD"; 952 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && 953 (index & ATTR_OPSIZE)) 954 o << "IC_64BIT_REXW_OPSIZE"; 955 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && 956 (index & ATTR_ADSIZE)) 957 o << "IC_64BIT_REXW_ADSIZE"; 958 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE)) 959 o << "IC_64BIT_XD_OPSIZE"; 960 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE)) 961 o << "IC_64BIT_XS_OPSIZE"; 962 else if ((index & ATTR_64BIT) && (index & ATTR_XS)) 963 o << "IC_64BIT_XS"; 964 else if ((index & ATTR_64BIT) && (index & ATTR_XD)) 965 o << "IC_64BIT_XD"; 966 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE) && 967 (index & ATTR_ADSIZE)) 968 o << "IC_64BIT_OPSIZE_ADSIZE"; 969 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE)) 970 o << "IC_64BIT_OPSIZE"; 971 else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE)) 972 o << "IC_64BIT_ADSIZE"; 973 else if ((index & ATTR_64BIT) && (index & ATTR_REXW)) 974 o << "IC_64BIT_REXW"; 975 else if ((index & ATTR_64BIT)) 976 o << "IC_64BIT"; 977 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE)) 978 o << "IC_XS_OPSIZE"; 979 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE)) 980 o << "IC_XD_OPSIZE"; 981 else if (index & ATTR_XS) 982 o << "IC_XS"; 983 else if (index & ATTR_XD) 984 o << "IC_XD"; 985 else if ((index & ATTR_OPSIZE) && (index & ATTR_ADSIZE)) 986 o << "IC_OPSIZE_ADSIZE"; 987 else if (index & ATTR_OPSIZE) 988 o << "IC_OPSIZE"; 989 else if (index & ATTR_ADSIZE) 990 o << "IC_ADSIZE"; 991 else 992 o << "IC"; 993 994 if (index < tableSize - 1) 995 o << ","; 996 else 997 o << " "; 998 999 o << " /* " << index << " */"; 1000 1001 o << "\n"; 1002 } 1003 1004 i--; 1005 o.indent(i * 2) << "};" << "\n"; 1006 } 1007 1008 void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2, 1009 unsigned &i1, unsigned &i2, 1010 unsigned &ModRMTableNum) const { 1011 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[0], ONEBYTE_STR); 1012 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[1], TWOBYTE_STR); 1013 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[2], THREEBYTE38_STR); 1014 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[3], THREEBYTE3A_STR); 1015 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[4], XOP8_MAP_STR); 1016 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[5], XOP9_MAP_STR); 1017 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[6], XOPA_MAP_STR); 1018 } 1019 1020 void DisassemblerTables::emit(raw_ostream &o) const { 1021 unsigned i1 = 0; 1022 unsigned i2 = 0; 1023 1024 std::string s1; 1025 std::string s2; 1026 1027 raw_string_ostream o1(s1); 1028 raw_string_ostream o2(s2); 1029 1030 emitInstructionInfo(o, i2); 1031 o << "\n"; 1032 1033 emitContextTable(o, i2); 1034 o << "\n"; 1035 1036 unsigned ModRMTableNum = 0; 1037 1038 o << "static const InstrUID modRMTable[] = {\n"; 1039 i1++; 1040 std::vector<unsigned> EmptyTable(1, 0); 1041 ModRMTable[EmptyTable] = ModRMTableNum; 1042 ModRMTableNum += EmptyTable.size(); 1043 o1 << "/* EmptyTable */\n"; 1044 o1.indent(i1 * 2) << "0x0,\n"; 1045 i1--; 1046 emitContextDecisions(o1, o2, i1, i2, ModRMTableNum); 1047 1048 o << o1.str(); 1049 o << " 0x0\n"; 1050 o << "};\n"; 1051 o << "\n"; 1052 o << o2.str(); 1053 o << "\n"; 1054 o << "\n"; 1055 } 1056 1057 void DisassemblerTables::setTableFields(ModRMDecision &decision, 1058 const ModRMFilter &filter, 1059 InstrUID uid, 1060 uint8_t opcode) { 1061 for (unsigned index = 0; index < 256; ++index) { 1062 if (filter.accepts(index)) { 1063 if (decision.instructionIDs[index] == uid) 1064 continue; 1065 1066 if (decision.instructionIDs[index] != 0) { 1067 InstructionSpecifier &newInfo = 1068 InstructionSpecifiers[uid]; 1069 InstructionSpecifier &previousInfo = 1070 InstructionSpecifiers[decision.instructionIDs[index]]; 1071 1072 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" || 1073 newInfo.name == "XCHG32ar" || 1074 newInfo.name == "XCHG32ar64" || 1075 newInfo.name == "XCHG64ar")) 1076 continue; // special case for XCHG*ar and NOOP 1077 1078 if (previousInfo.name == "DATA16_PREFIX" && 1079 newInfo.name == "DATA32_PREFIX") 1080 continue; // special case for data16 and data32 1081 1082 if (outranks(previousInfo.insnContext, newInfo.insnContext)) 1083 continue; 1084 1085 if (previousInfo.insnContext == newInfo.insnContext) { 1086 errs() << "Error: Primary decode conflict: "; 1087 errs() << newInfo.name << " would overwrite " << previousInfo.name; 1088 errs() << "\n"; 1089 errs() << "ModRM " << index << "\n"; 1090 errs() << "Opcode " << (uint16_t)opcode << "\n"; 1091 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n"; 1092 HasConflicts = true; 1093 } 1094 } 1095 1096 decision.instructionIDs[index] = uid; 1097 } 1098 } 1099 } 1100 1101 void DisassemblerTables::setTableFields(OpcodeType type, 1102 InstructionContext insnContext, 1103 uint8_t opcode, 1104 const ModRMFilter &filter, 1105 InstrUID uid, 1106 bool is32bit, 1107 bool noPrefix, 1108 bool ignoresVEX_L, 1109 bool ignoresVEX_W, 1110 unsigned addressSize) { 1111 ContextDecision &decision = *Tables[type]; 1112 1113 for (unsigned index = 0; index < IC_max; ++index) { 1114 if ((is32bit || addressSize == 16) && 1115 inheritsFrom((InstructionContext)index, IC_64BIT)) 1116 continue; 1117 1118 bool adSize64 = addressSize == 64; 1119 if (inheritsFrom((InstructionContext)index, 1120 InstructionSpecifiers[uid].insnContext, noPrefix, 1121 ignoresVEX_L, ignoresVEX_W, adSize64)) 1122 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode], 1123 filter, 1124 uid, 1125 opcode); 1126 } 1127 } 1128