1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler Emitter. 11 // It contains the implementation of the disassembler tables. 12 // Documentation for the disassembler emitter in general can be found in 13 // X86DisasemblerEmitter.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "X86DisassemblerTables.h" 18 #include "X86DisassemblerShared.h" 19 #include "llvm/ADT/STLExtras.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include "llvm/Support/Format.h" 22 #include "llvm/TableGen/TableGenBackend.h" 23 #include <map> 24 25 using namespace llvm; 26 using namespace X86Disassembler; 27 28 /// stringForContext - Returns a string containing the name of a particular 29 /// InstructionContext, usually for diagnostic purposes. 30 /// 31 /// @param insnContext - The instruction class to transform to a string. 32 /// @return - A statically-allocated string constant that contains the 33 /// name of the instruction class. 34 static inline const char* stringForContext(InstructionContext insnContext) { 35 switch (insnContext) { 36 default: 37 llvm_unreachable("Unhandled instruction class"); 38 #define ENUM_ENTRY(n, r, d) case n: return #n; break; 39 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\ 40 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)\ 41 ENUM_ENTRY(n##_KZ_B, r, d) 42 INSTRUCTION_CONTEXTS 43 #undef ENUM_ENTRY 44 #undef ENUM_ENTRY_K_B 45 } 46 } 47 48 /// stringForOperandType - Like stringForContext, but for OperandTypes. 49 static inline const char* stringForOperandType(OperandType type) { 50 switch (type) { 51 default: 52 llvm_unreachable("Unhandled type"); 53 #define ENUM_ENTRY(i, d) case i: return #i; 54 TYPES 55 #undef ENUM_ENTRY 56 } 57 } 58 59 /// stringForOperandEncoding - like stringForContext, but for 60 /// OperandEncodings. 61 static inline const char* stringForOperandEncoding(OperandEncoding encoding) { 62 switch (encoding) { 63 default: 64 llvm_unreachable("Unhandled encoding"); 65 #define ENUM_ENTRY(i, d) case i: return #i; 66 ENCODINGS 67 #undef ENUM_ENTRY 68 } 69 } 70 71 /// inheritsFrom - Indicates whether all instructions in one class also belong 72 /// to another class. 73 /// 74 /// @param child - The class that may be the subset 75 /// @param parent - The class that may be the superset 76 /// @return - True if child is a subset of parent, false otherwise. 77 static inline bool inheritsFrom(InstructionContext child, 78 InstructionContext parent, 79 bool VEX_LIG = false) { 80 if (child == parent) 81 return true; 82 83 switch (parent) { 84 case IC: 85 return(inheritsFrom(child, IC_64BIT) || 86 inheritsFrom(child, IC_OPSIZE) || 87 inheritsFrom(child, IC_ADSIZE) || 88 inheritsFrom(child, IC_XD) || 89 inheritsFrom(child, IC_XS)); 90 case IC_64BIT: 91 return(inheritsFrom(child, IC_64BIT_REXW) || 92 inheritsFrom(child, IC_64BIT_OPSIZE) || 93 inheritsFrom(child, IC_64BIT_ADSIZE) || 94 inheritsFrom(child, IC_64BIT_XD) || 95 inheritsFrom(child, IC_64BIT_XS)); 96 case IC_OPSIZE: 97 return inheritsFrom(child, IC_64BIT_OPSIZE); 98 case IC_ADSIZE: 99 case IC_64BIT_ADSIZE: 100 return false; 101 case IC_XD: 102 return inheritsFrom(child, IC_64BIT_XD); 103 case IC_XS: 104 return inheritsFrom(child, IC_64BIT_XS); 105 case IC_XD_OPSIZE: 106 return inheritsFrom(child, IC_64BIT_XD_OPSIZE); 107 case IC_XS_OPSIZE: 108 return inheritsFrom(child, IC_64BIT_XS_OPSIZE); 109 case IC_64BIT_REXW: 110 return(inheritsFrom(child, IC_64BIT_REXW_XS) || 111 inheritsFrom(child, IC_64BIT_REXW_XD) || 112 inheritsFrom(child, IC_64BIT_REXW_OPSIZE)); 113 case IC_64BIT_OPSIZE: 114 return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE)); 115 case IC_64BIT_XD: 116 return(inheritsFrom(child, IC_64BIT_REXW_XD)); 117 case IC_64BIT_XS: 118 return(inheritsFrom(child, IC_64BIT_REXW_XS)); 119 case IC_64BIT_XD_OPSIZE: 120 case IC_64BIT_XS_OPSIZE: 121 return false; 122 case IC_64BIT_REXW_XD: 123 case IC_64BIT_REXW_XS: 124 case IC_64BIT_REXW_OPSIZE: 125 return false; 126 case IC_VEX: 127 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W)) || 128 inheritsFrom(child, IC_VEX_W) || 129 (VEX_LIG && inheritsFrom(child, IC_VEX_L)); 130 case IC_VEX_XS: 131 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS)) || 132 inheritsFrom(child, IC_VEX_W_XS) || 133 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS)); 134 case IC_VEX_XD: 135 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD)) || 136 inheritsFrom(child, IC_VEX_W_XD) || 137 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD)); 138 case IC_VEX_OPSIZE: 139 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE)) || 140 inheritsFrom(child, IC_VEX_W_OPSIZE) || 141 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE)); 142 case IC_VEX_W: 143 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W); 144 case IC_VEX_W_XS: 145 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS); 146 case IC_VEX_W_XD: 147 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD); 148 case IC_VEX_W_OPSIZE: 149 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE); 150 case IC_VEX_L: 151 return inheritsFrom(child, IC_VEX_L_W); 152 case IC_VEX_L_XS: 153 return inheritsFrom(child, IC_VEX_L_W_XS); 154 case IC_VEX_L_XD: 155 return inheritsFrom(child, IC_VEX_L_W_XD); 156 case IC_VEX_L_OPSIZE: 157 return inheritsFrom(child, IC_VEX_L_W_OPSIZE); 158 case IC_VEX_L_W: 159 case IC_VEX_L_W_XS: 160 case IC_VEX_L_W_XD: 161 case IC_VEX_L_W_OPSIZE: 162 return false; 163 case IC_EVEX: 164 return inheritsFrom(child, IC_EVEX_W) || 165 inheritsFrom(child, IC_EVEX_L_W); 166 case IC_EVEX_XS: 167 return inheritsFrom(child, IC_EVEX_W_XS) || 168 inheritsFrom(child, IC_EVEX_L_W_XS); 169 case IC_EVEX_XD: 170 return inheritsFrom(child, IC_EVEX_W_XD) || 171 inheritsFrom(child, IC_EVEX_L_W_XD); 172 case IC_EVEX_OPSIZE: 173 return inheritsFrom(child, IC_EVEX_W_OPSIZE) || 174 inheritsFrom(child, IC_EVEX_L_W_OPSIZE); 175 case IC_EVEX_W: 176 case IC_EVEX_W_XS: 177 case IC_EVEX_W_XD: 178 case IC_EVEX_W_OPSIZE: 179 return false; 180 case IC_EVEX_L: 181 case IC_EVEX_L_XS: 182 case IC_EVEX_L_XD: 183 case IC_EVEX_L_OPSIZE: 184 return false; 185 case IC_EVEX_L_W: 186 case IC_EVEX_L_W_XS: 187 case IC_EVEX_L_W_XD: 188 case IC_EVEX_L_W_OPSIZE: 189 return false; 190 case IC_EVEX_L2: 191 case IC_EVEX_L2_XS: 192 case IC_EVEX_L2_XD: 193 case IC_EVEX_L2_OPSIZE: 194 return false; 195 case IC_EVEX_L2_W: 196 case IC_EVEX_L2_W_XS: 197 case IC_EVEX_L2_W_XD: 198 case IC_EVEX_L2_W_OPSIZE: 199 return false; 200 case IC_EVEX_K: 201 return inheritsFrom(child, IC_EVEX_W_K) || 202 inheritsFrom(child, IC_EVEX_L_W_K); 203 case IC_EVEX_XS_K: 204 return inheritsFrom(child, IC_EVEX_W_XS_K) || 205 inheritsFrom(child, IC_EVEX_L_W_XS_K); 206 case IC_EVEX_XD_K: 207 return inheritsFrom(child, IC_EVEX_W_XD_K) || 208 inheritsFrom(child, IC_EVEX_L_W_XD_K); 209 case IC_EVEX_OPSIZE_K: 210 case IC_EVEX_OPSIZE_B: 211 return false; 212 case IC_EVEX_W_K: 213 case IC_EVEX_W_XS_K: 214 case IC_EVEX_W_XD_K: 215 case IC_EVEX_W_OPSIZE_K: 216 case IC_EVEX_W_OPSIZE_B: 217 return false; 218 case IC_EVEX_L_K: 219 case IC_EVEX_L_XS_K: 220 case IC_EVEX_L_XD_K: 221 case IC_EVEX_L_OPSIZE_K: 222 return false; 223 case IC_EVEX_W_KZ: 224 case IC_EVEX_W_XS_KZ: 225 case IC_EVEX_W_XD_KZ: 226 case IC_EVEX_W_OPSIZE_KZ: 227 return false; 228 case IC_EVEX_L_KZ: 229 case IC_EVEX_L_XS_KZ: 230 case IC_EVEX_L_XD_KZ: 231 case IC_EVEX_L_OPSIZE_KZ: 232 return false; 233 case IC_EVEX_L_W_K: 234 case IC_EVEX_L_W_XS_K: 235 case IC_EVEX_L_W_XD_K: 236 case IC_EVEX_L_W_OPSIZE_K: 237 case IC_EVEX_L_W_KZ: 238 case IC_EVEX_L_W_XS_KZ: 239 case IC_EVEX_L_W_XD_KZ: 240 case IC_EVEX_L_W_OPSIZE_KZ: 241 return false; 242 case IC_EVEX_L2_K: 243 case IC_EVEX_L2_B: 244 case IC_EVEX_L2_XS_K: 245 case IC_EVEX_L2_XS_B: 246 case IC_EVEX_L2_XD_B: 247 case IC_EVEX_L2_XD_K: 248 case IC_EVEX_L2_OPSIZE_K: 249 case IC_EVEX_L2_OPSIZE_B: 250 case IC_EVEX_L2_OPSIZE_K_B: 251 case IC_EVEX_L2_KZ: 252 case IC_EVEX_L2_XS_KZ: 253 case IC_EVEX_L2_XD_KZ: 254 case IC_EVEX_L2_OPSIZE_KZ: 255 case IC_EVEX_L2_OPSIZE_KZ_B: 256 return false; 257 case IC_EVEX_L2_W_K: 258 case IC_EVEX_L2_W_B: 259 case IC_EVEX_L2_W_XS_K: 260 case IC_EVEX_L2_W_XD_K: 261 case IC_EVEX_L2_W_XD_B: 262 case IC_EVEX_L2_W_OPSIZE_K: 263 case IC_EVEX_L2_W_OPSIZE_B: 264 case IC_EVEX_L2_W_OPSIZE_K_B: 265 case IC_EVEX_L2_W_KZ: 266 case IC_EVEX_L2_W_XS_KZ: 267 case IC_EVEX_L2_W_XD_KZ: 268 case IC_EVEX_L2_W_OPSIZE_KZ: 269 case IC_EVEX_L2_W_OPSIZE_KZ_B: 270 return false; 271 default: 272 errs() << "Unknown instruction class: " << 273 stringForContext((InstructionContext)parent) << "\n"; 274 llvm_unreachable("Unknown instruction class"); 275 } 276 } 277 278 /// outranks - Indicates whether, if an instruction has two different applicable 279 /// classes, which class should be preferred when performing decode. This 280 /// imposes a total ordering (ties are resolved toward "lower") 281 /// 282 /// @param upper - The class that may be preferable 283 /// @param lower - The class that may be less preferable 284 /// @return - True if upper is to be preferred, false otherwise. 285 static inline bool outranks(InstructionContext upper, 286 InstructionContext lower) { 287 assert(upper < IC_max); 288 assert(lower < IC_max); 289 290 #define ENUM_ENTRY(n, r, d) r, 291 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) \ 292 ENUM_ENTRY(n##_K_B, r, d) ENUM_ENTRY(n##_KZ_B, r, d) \ 293 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d) 294 static int ranks[IC_max] = { 295 INSTRUCTION_CONTEXTS 296 }; 297 #undef ENUM_ENTRY 298 #undef ENUM_ENTRY_K_B 299 300 return (ranks[upper] > ranks[lower]); 301 } 302 303 /// getDecisionType - Determines whether a ModRM decision with 255 entries can 304 /// be compacted by eliminating redundant information. 305 /// 306 /// @param decision - The decision to be compacted. 307 /// @return - The compactest available representation for the decision. 308 static ModRMDecisionType getDecisionType(ModRMDecision &decision) { 309 bool satisfiesOneEntry = true; 310 bool satisfiesSplitRM = true; 311 bool satisfiesSplitReg = true; 312 bool satisfiesSplitMisc = true; 313 314 for (unsigned index = 0; index < 256; ++index) { 315 if (decision.instructionIDs[index] != decision.instructionIDs[0]) 316 satisfiesOneEntry = false; 317 318 if (((index & 0xc0) == 0xc0) && 319 (decision.instructionIDs[index] != decision.instructionIDs[0xc0])) 320 satisfiesSplitRM = false; 321 322 if (((index & 0xc0) != 0xc0) && 323 (decision.instructionIDs[index] != decision.instructionIDs[0x00])) 324 satisfiesSplitRM = false; 325 326 if (((index & 0xc0) == 0xc0) && 327 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8])) 328 satisfiesSplitReg = false; 329 330 if (((index & 0xc0) != 0xc0) && 331 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38])) 332 satisfiesSplitMisc = false; 333 } 334 335 if (satisfiesOneEntry) 336 return MODRM_ONEENTRY; 337 338 if (satisfiesSplitRM) 339 return MODRM_SPLITRM; 340 341 if (satisfiesSplitReg && satisfiesSplitMisc) 342 return MODRM_SPLITREG; 343 344 if (satisfiesSplitMisc) 345 return MODRM_SPLITMISC; 346 347 return MODRM_FULL; 348 } 349 350 /// stringForDecisionType - Returns a statically-allocated string corresponding 351 /// to a particular decision type. 352 /// 353 /// @param dt - The decision type. 354 /// @return - A pointer to the statically-allocated string (e.g., 355 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY). 356 static const char* stringForDecisionType(ModRMDecisionType dt) { 357 #define ENUM_ENTRY(n) case n: return #n; 358 switch (dt) { 359 default: 360 llvm_unreachable("Unknown decision type"); 361 MODRMTYPES 362 }; 363 #undef ENUM_ENTRY 364 } 365 366 DisassemblerTables::DisassemblerTables() { 367 unsigned i; 368 369 for (i = 0; i < array_lengthof(Tables); i++) { 370 Tables[i] = new ContextDecision; 371 memset(Tables[i], 0, sizeof(ContextDecision)); 372 } 373 374 HasConflicts = false; 375 } 376 377 DisassemblerTables::~DisassemblerTables() { 378 unsigned i; 379 380 for (i = 0; i < array_lengthof(Tables); i++) 381 delete Tables[i]; 382 } 383 384 void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2, 385 unsigned &i1, unsigned &i2, 386 unsigned &ModRMTableNum, 387 ModRMDecision &decision) const { 388 static uint32_t sTableNumber = 0; 389 static uint32_t sEntryNumber = 1; 390 ModRMDecisionType dt = getDecisionType(decision); 391 392 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0) 393 { 394 o2.indent(i2) << "{ /* ModRMDecision */" << "\n"; 395 i2++; 396 397 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n"; 398 o2.indent(i2) << 0 << " /* EmptyTable */\n"; 399 400 i2--; 401 o2.indent(i2) << "}"; 402 return; 403 } 404 405 std::vector<unsigned> ModRMDecision; 406 407 switch (dt) { 408 default: 409 llvm_unreachable("Unknown decision type"); 410 case MODRM_ONEENTRY: 411 ModRMDecision.push_back(decision.instructionIDs[0]); 412 break; 413 case MODRM_SPLITRM: 414 ModRMDecision.push_back(decision.instructionIDs[0x00]); 415 ModRMDecision.push_back(decision.instructionIDs[0xc0]); 416 break; 417 case MODRM_SPLITREG: 418 for (unsigned index = 0; index < 64; index += 8) 419 ModRMDecision.push_back(decision.instructionIDs[index]); 420 for (unsigned index = 0xc0; index < 256; index += 8) 421 ModRMDecision.push_back(decision.instructionIDs[index]); 422 break; 423 case MODRM_SPLITMISC: 424 for (unsigned index = 0; index < 64; index += 8) 425 ModRMDecision.push_back(decision.instructionIDs[index]); 426 for (unsigned index = 0xc0; index < 256; ++index) 427 ModRMDecision.push_back(decision.instructionIDs[index]); 428 break; 429 case MODRM_FULL: 430 for (unsigned index = 0; index < 256; ++index) 431 ModRMDecision.push_back(decision.instructionIDs[index]); 432 break; 433 } 434 435 unsigned &EntryNumber = ModRMTable[ModRMDecision]; 436 if (EntryNumber == 0) { 437 EntryNumber = ModRMTableNum; 438 439 ModRMTableNum += ModRMDecision.size(); 440 o1 << "/* Table" << EntryNumber << " */\n"; 441 i1++; 442 for (std::vector<unsigned>::const_iterator I = ModRMDecision.begin(), 443 E = ModRMDecision.end(); I != E; ++I) { 444 o1.indent(i1 * 2) << format("0x%hx", *I) << ", /* " 445 << InstructionSpecifiers[*I].name << " */\n"; 446 } 447 i1--; 448 } 449 450 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n"; 451 i2++; 452 453 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n"; 454 o2.indent(i2) << EntryNumber << " /* Table" << EntryNumber << " */\n"; 455 456 i2--; 457 o2.indent(i2) << "}"; 458 459 switch (dt) { 460 default: 461 llvm_unreachable("Unknown decision type"); 462 case MODRM_ONEENTRY: 463 sEntryNumber += 1; 464 break; 465 case MODRM_SPLITRM: 466 sEntryNumber += 2; 467 break; 468 case MODRM_SPLITREG: 469 sEntryNumber += 16; 470 break; 471 case MODRM_SPLITMISC: 472 sEntryNumber += 8 + 64; 473 break; 474 case MODRM_FULL: 475 sEntryNumber += 256; 476 break; 477 } 478 479 // We assume that the index can fit into uint16_t. 480 assert(sEntryNumber < 65536U && 481 "Index into ModRMDecision is too large for uint16_t!"); 482 483 ++sTableNumber; 484 } 485 486 void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2, 487 unsigned &i1, unsigned &i2, 488 unsigned &ModRMTableNum, 489 OpcodeDecision &decision) const { 490 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n"; 491 i2++; 492 o2.indent(i2) << "{" << "\n"; 493 i2++; 494 495 for (unsigned index = 0; index < 256; ++index) { 496 o2.indent(i2); 497 498 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n"; 499 500 emitModRMDecision(o1, o2, i1, i2, ModRMTableNum, 501 decision.modRMDecisions[index]); 502 503 if (index < 255) 504 o2 << ","; 505 506 o2 << "\n"; 507 } 508 509 i2--; 510 o2.indent(i2) << "}" << "\n"; 511 i2--; 512 o2.indent(i2) << "}" << "\n"; 513 } 514 515 void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2, 516 unsigned &i1, unsigned &i2, 517 unsigned &ModRMTableNum, 518 ContextDecision &decision, 519 const char* name) const { 520 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n"; 521 i2++; 522 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n"; 523 i2++; 524 525 for (unsigned index = 0; index < IC_max; ++index) { 526 o2.indent(i2) << "/* "; 527 o2 << stringForContext((InstructionContext)index); 528 o2 << " */"; 529 o2 << "\n"; 530 531 emitOpcodeDecision(o1, o2, i1, i2, ModRMTableNum, 532 decision.opcodeDecisions[index]); 533 534 if (index + 1 < IC_max) 535 o2 << ", "; 536 } 537 538 i2--; 539 o2.indent(i2) << "}" << "\n"; 540 i2--; 541 o2.indent(i2) << "};" << "\n"; 542 } 543 544 void DisassemblerTables::emitInstructionInfo(raw_ostream &o, 545 unsigned &i) const { 546 unsigned NumInstructions = InstructionSpecifiers.size(); 547 548 o << "static const struct OperandSpecifier x86OperandSets[][" 549 << X86_MAX_OPERANDS << "] = {\n"; 550 551 typedef std::vector<std::pair<const char *, const char *> > OperandListTy; 552 std::map<OperandListTy, unsigned> OperandSets; 553 554 unsigned OperandSetNum = 0; 555 for (unsigned Index = 0; Index < NumInstructions; ++Index) { 556 OperandListTy OperandList; 557 558 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS; 559 ++OperandIndex) { 560 const char *Encoding = 561 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[Index] 562 .operands[OperandIndex].encoding); 563 const char *Type = 564 stringForOperandType((OperandType)InstructionSpecifiers[Index] 565 .operands[OperandIndex].type); 566 OperandList.push_back(std::make_pair(Encoding, Type)); 567 } 568 unsigned &N = OperandSets[OperandList]; 569 if (N != 0) continue; 570 571 N = ++OperandSetNum; 572 573 o << " { /* " << (OperandSetNum - 1) << " */\n"; 574 for (unsigned i = 0, e = OperandList.size(); i != e; ++i) { 575 o << " { " << OperandList[i].first << ", " 576 << OperandList[i].second << " },\n"; 577 } 578 o << " },\n"; 579 } 580 o << "};" << "\n\n"; 581 582 o.indent(i * 2) << "static const struct InstructionSpecifier "; 583 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n"; 584 585 i++; 586 587 for (unsigned index = 0; index < NumInstructions; ++index) { 588 o.indent(i * 2) << "{ /* " << index << " */" << "\n"; 589 i++; 590 591 OperandListTy OperandList; 592 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS; 593 ++OperandIndex) { 594 const char *Encoding = 595 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[index] 596 .operands[OperandIndex].encoding); 597 const char *Type = 598 stringForOperandType((OperandType)InstructionSpecifiers[index] 599 .operands[OperandIndex].type); 600 OperandList.push_back(std::make_pair(Encoding, Type)); 601 } 602 o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n"; 603 604 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */"; 605 o << "\n"; 606 607 i--; 608 o.indent(i * 2) << "}"; 609 610 if (index + 1 < NumInstructions) 611 o << ","; 612 613 o << "\n"; 614 } 615 616 i--; 617 o.indent(i * 2) << "};" << "\n"; 618 } 619 620 void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const { 621 const unsigned int tableSize = 16384; 622 o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR 623 "[" << tableSize << "] = {\n"; 624 i++; 625 626 for (unsigned index = 0; index < tableSize; ++index) { 627 o.indent(i * 2); 628 629 if (index & ATTR_EVEX) { 630 o << "IC_EVEX"; 631 if (index & ATTR_EVEXL2) 632 o << "_L2"; 633 else if (index & ATTR_EVEXL) 634 o << "_L"; 635 if (index & ATTR_REXW) 636 o << "_W"; 637 if (index & ATTR_OPSIZE) 638 o << "_OPSIZE"; 639 else if (index & ATTR_XD) 640 o << "_XD"; 641 else if (index & ATTR_XS) 642 o << "_XS"; 643 if (index & ATTR_EVEXKZ) 644 o << "_KZ"; 645 else if (index & ATTR_EVEXK) 646 o << "_K"; 647 if (index & ATTR_EVEXB) 648 o << "_B"; 649 } 650 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE)) 651 o << "IC_VEX_L_W_OPSIZE"; 652 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XD)) 653 o << "IC_VEX_L_W_XD"; 654 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XS)) 655 o << "IC_VEX_L_W_XS"; 656 else if ((index & ATTR_VEXL) && (index & ATTR_REXW)) 657 o << "IC_VEX_L_W"; 658 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE)) 659 o << "IC_VEX_L_OPSIZE"; 660 else if ((index & ATTR_VEXL) && (index & ATTR_XD)) 661 o << "IC_VEX_L_XD"; 662 else if ((index & ATTR_VEXL) && (index & ATTR_XS)) 663 o << "IC_VEX_L_XS"; 664 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE)) 665 o << "IC_VEX_W_OPSIZE"; 666 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD)) 667 o << "IC_VEX_W_XD"; 668 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS)) 669 o << "IC_VEX_W_XS"; 670 else if (index & ATTR_VEXL) 671 o << "IC_VEX_L"; 672 else if ((index & ATTR_VEX) && (index & ATTR_REXW)) 673 o << "IC_VEX_W"; 674 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE)) 675 o << "IC_VEX_OPSIZE"; 676 else if ((index & ATTR_VEX) && (index & ATTR_XD)) 677 o << "IC_VEX_XD"; 678 else if ((index & ATTR_VEX) && (index & ATTR_XS)) 679 o << "IC_VEX_XS"; 680 else if (index & ATTR_VEX) 681 o << "IC_VEX"; 682 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS)) 683 o << "IC_64BIT_REXW_XS"; 684 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD)) 685 o << "IC_64BIT_REXW_XD"; 686 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && 687 (index & ATTR_OPSIZE)) 688 o << "IC_64BIT_REXW_OPSIZE"; 689 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE)) 690 o << "IC_64BIT_XD_OPSIZE"; 691 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE)) 692 o << "IC_64BIT_XS_OPSIZE"; 693 else if ((index & ATTR_64BIT) && (index & ATTR_XS)) 694 o << "IC_64BIT_XS"; 695 else if ((index & ATTR_64BIT) && (index & ATTR_XD)) 696 o << "IC_64BIT_XD"; 697 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE)) 698 o << "IC_64BIT_OPSIZE"; 699 else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE)) 700 o << "IC_64BIT_ADSIZE"; 701 else if ((index & ATTR_64BIT) && (index & ATTR_REXW)) 702 o << "IC_64BIT_REXW"; 703 else if ((index & ATTR_64BIT)) 704 o << "IC_64BIT"; 705 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE)) 706 o << "IC_XS_OPSIZE"; 707 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE)) 708 o << "IC_XD_OPSIZE"; 709 else if (index & ATTR_XS) 710 o << "IC_XS"; 711 else if (index & ATTR_XD) 712 o << "IC_XD"; 713 else if (index & ATTR_OPSIZE) 714 o << "IC_OPSIZE"; 715 else if (index & ATTR_ADSIZE) 716 o << "IC_ADSIZE"; 717 else 718 o << "IC"; 719 720 if (index < tableSize - 1) 721 o << ","; 722 else 723 o << " "; 724 725 o << " /* " << index << " */"; 726 727 o << "\n"; 728 } 729 730 i--; 731 o.indent(i * 2) << "};" << "\n"; 732 } 733 734 void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2, 735 unsigned &i1, unsigned &i2, 736 unsigned &ModRMTableNum) const { 737 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[0], ONEBYTE_STR); 738 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[1], TWOBYTE_STR); 739 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[2], THREEBYTE38_STR); 740 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[3], THREEBYTE3A_STR); 741 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[4], THREEBYTEA6_STR); 742 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[5], THREEBYTEA7_STR); 743 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[6], XOP8_MAP_STR); 744 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[7], XOP9_MAP_STR); 745 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[8], XOPA_MAP_STR); 746 } 747 748 void DisassemblerTables::emit(raw_ostream &o) const { 749 unsigned i1 = 0; 750 unsigned i2 = 0; 751 752 std::string s1; 753 std::string s2; 754 755 raw_string_ostream o1(s1); 756 raw_string_ostream o2(s2); 757 758 emitInstructionInfo(o, i2); 759 o << "\n"; 760 761 emitContextTable(o, i2); 762 o << "\n"; 763 764 unsigned ModRMTableNum = 0; 765 766 o << "static const InstrUID modRMTable[] = {\n"; 767 i1++; 768 std::vector<unsigned> EmptyTable(1, 0); 769 ModRMTable[EmptyTable] = ModRMTableNum; 770 ModRMTableNum += EmptyTable.size(); 771 o1 << "/* EmptyTable */\n"; 772 o1.indent(i1 * 2) << "0x0,\n"; 773 i1--; 774 emitContextDecisions(o1, o2, i1, i2, ModRMTableNum); 775 776 o << o1.str(); 777 o << " 0x0\n"; 778 o << "};\n"; 779 o << "\n"; 780 o << o2.str(); 781 o << "\n"; 782 o << "\n"; 783 } 784 785 void DisassemblerTables::setTableFields(ModRMDecision &decision, 786 const ModRMFilter &filter, 787 InstrUID uid, 788 uint8_t opcode) { 789 for (unsigned index = 0; index < 256; ++index) { 790 if (filter.accepts(index)) { 791 if (decision.instructionIDs[index] == uid) 792 continue; 793 794 if (decision.instructionIDs[index] != 0) { 795 InstructionSpecifier &newInfo = 796 InstructionSpecifiers[uid]; 797 InstructionSpecifier &previousInfo = 798 InstructionSpecifiers[decision.instructionIDs[index]]; 799 800 if(newInfo.filtered) 801 continue; // filtered instructions get lowest priority 802 803 // Instructions such as MOV8ao8 and MOV8ao8_16 differ only in the 804 // presence of the AdSize prefix. However, the disassembler doesn't 805 // care about that difference in the instruction definition; it 806 // handles 16-bit vs. 32-bit addressing for itself based purely 807 // on the 0x67 prefix and the CPU mode. So there's no need to 808 // disambiguate between them; just let them conflict/coexist. 809 if (previousInfo.name + "_16" == newInfo.name) 810 continue; 811 812 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" || 813 newInfo.name == "XCHG32ar" || 814 newInfo.name == "XCHG32ar64" || 815 newInfo.name == "XCHG64ar")) 816 continue; // special case for XCHG*ar and NOOP 817 818 if (outranks(previousInfo.insnContext, newInfo.insnContext)) 819 continue; 820 821 if (previousInfo.insnContext == newInfo.insnContext && 822 !previousInfo.filtered) { 823 errs() << "Error: Primary decode conflict: "; 824 errs() << newInfo.name << " would overwrite " << previousInfo.name; 825 errs() << "\n"; 826 errs() << "ModRM " << index << "\n"; 827 errs() << "Opcode " << (uint16_t)opcode << "\n"; 828 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n"; 829 HasConflicts = true; 830 } 831 } 832 833 decision.instructionIDs[index] = uid; 834 } 835 } 836 } 837 838 void DisassemblerTables::setTableFields(OpcodeType type, 839 InstructionContext insnContext, 840 uint8_t opcode, 841 const ModRMFilter &filter, 842 InstrUID uid, 843 bool is32bit, 844 bool ignoresVEX_L) { 845 ContextDecision &decision = *Tables[type]; 846 847 for (unsigned index = 0; index < IC_max; ++index) { 848 if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT)) 849 continue; 850 851 if (inheritsFrom((InstructionContext)index, 852 InstructionSpecifiers[uid].insnContext, ignoresVEX_L)) 853 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode], 854 filter, 855 uid, 856 opcode); 857 } 858 } 859