1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler Emitter. 11 // It contains the implementation of the disassembler tables. 12 // Documentation for the disassembler emitter in general can be found in 13 // X86DisasemblerEmitter.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "X86DisassemblerTables.h" 18 #include "X86DisassemblerShared.h" 19 #include "llvm/ADT/STLExtras.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include "llvm/Support/Format.h" 22 #include <map> 23 24 using namespace llvm; 25 using namespace X86Disassembler; 26 27 /// stringForContext - Returns a string containing the name of a particular 28 /// InstructionContext, usually for diagnostic purposes. 29 /// 30 /// @param insnContext - The instruction class to transform to a string. 31 /// @return - A statically-allocated string constant that contains the 32 /// name of the instruction class. 33 static inline const char* stringForContext(InstructionContext insnContext) { 34 switch (insnContext) { 35 default: 36 llvm_unreachable("Unhandled instruction class"); 37 #define ENUM_ENTRY(n, r, d) case n: return #n; break; 38 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\ 39 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)\ 40 ENUM_ENTRY(n##_KZ_B, r, d) 41 INSTRUCTION_CONTEXTS 42 #undef ENUM_ENTRY 43 #undef ENUM_ENTRY_K_B 44 } 45 } 46 47 /// stringForOperandType - Like stringForContext, but for OperandTypes. 48 static inline const char* stringForOperandType(OperandType type) { 49 switch (type) { 50 default: 51 llvm_unreachable("Unhandled type"); 52 #define ENUM_ENTRY(i, d) case i: return #i; 53 TYPES 54 #undef ENUM_ENTRY 55 } 56 } 57 58 /// stringForOperandEncoding - like stringForContext, but for 59 /// OperandEncodings. 60 static inline const char* stringForOperandEncoding(OperandEncoding encoding) { 61 switch (encoding) { 62 default: 63 llvm_unreachable("Unhandled encoding"); 64 #define ENUM_ENTRY(i, d) case i: return #i; 65 ENCODINGS 66 #undef ENUM_ENTRY 67 } 68 } 69 70 /// inheritsFrom - Indicates whether all instructions in one class also belong 71 /// to another class. 72 /// 73 /// @param child - The class that may be the subset 74 /// @param parent - The class that may be the superset 75 /// @return - True if child is a subset of parent, false otherwise. 76 static inline bool inheritsFrom(InstructionContext child, 77 InstructionContext parent, 78 bool VEX_LIG = false, bool AdSize64 = false) { 79 if (child == parent) 80 return true; 81 82 switch (parent) { 83 case IC: 84 return(inheritsFrom(child, IC_64BIT, AdSize64) || 85 inheritsFrom(child, IC_OPSIZE) || 86 inheritsFrom(child, IC_ADSIZE) || 87 inheritsFrom(child, IC_XD) || 88 inheritsFrom(child, IC_XS)); 89 case IC_64BIT: 90 return(inheritsFrom(child, IC_64BIT_REXW) || 91 inheritsFrom(child, IC_64BIT_OPSIZE) || 92 (!AdSize64 && inheritsFrom(child, IC_64BIT_ADSIZE)) || 93 inheritsFrom(child, IC_64BIT_XD) || 94 inheritsFrom(child, IC_64BIT_XS)); 95 case IC_OPSIZE: 96 return inheritsFrom(child, IC_64BIT_OPSIZE) || 97 inheritsFrom(child, IC_OPSIZE_ADSIZE); 98 case IC_ADSIZE: 99 return inheritsFrom(child, IC_OPSIZE_ADSIZE); 100 case IC_OPSIZE_ADSIZE: 101 return false; 102 case IC_64BIT_ADSIZE: 103 return inheritsFrom(child, IC_64BIT_OPSIZE_ADSIZE); 104 case IC_64BIT_OPSIZE_ADSIZE: 105 return false; 106 case IC_XD: 107 return inheritsFrom(child, IC_64BIT_XD); 108 case IC_XS: 109 return inheritsFrom(child, IC_64BIT_XS); 110 case IC_XD_OPSIZE: 111 return inheritsFrom(child, IC_64BIT_XD_OPSIZE); 112 case IC_XS_OPSIZE: 113 return inheritsFrom(child, IC_64BIT_XS_OPSIZE); 114 case IC_64BIT_REXW: 115 return(inheritsFrom(child, IC_64BIT_REXW_XS) || 116 inheritsFrom(child, IC_64BIT_REXW_XD) || 117 inheritsFrom(child, IC_64BIT_REXW_OPSIZE) || 118 (!AdSize64 && inheritsFrom(child, IC_64BIT_REXW_ADSIZE))); 119 case IC_64BIT_OPSIZE: 120 return inheritsFrom(child, IC_64BIT_REXW_OPSIZE) || 121 (!AdSize64 && inheritsFrom(child, IC_64BIT_OPSIZE_ADSIZE)) || 122 (!AdSize64 && inheritsFrom(child, IC_64BIT_REXW_ADSIZE)); 123 case IC_64BIT_XD: 124 return(inheritsFrom(child, IC_64BIT_REXW_XD)); 125 case IC_64BIT_XS: 126 return(inheritsFrom(child, IC_64BIT_REXW_XS)); 127 case IC_64BIT_XD_OPSIZE: 128 case IC_64BIT_XS_OPSIZE: 129 return false; 130 case IC_64BIT_REXW_XD: 131 case IC_64BIT_REXW_XS: 132 case IC_64BIT_REXW_OPSIZE: 133 case IC_64BIT_REXW_ADSIZE: 134 return false; 135 case IC_VEX: 136 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W)) || 137 inheritsFrom(child, IC_VEX_W) || 138 (VEX_LIG && inheritsFrom(child, IC_VEX_L)); 139 case IC_VEX_XS: 140 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS)) || 141 inheritsFrom(child, IC_VEX_W_XS) || 142 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS)); 143 case IC_VEX_XD: 144 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD)) || 145 inheritsFrom(child, IC_VEX_W_XD) || 146 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD)); 147 case IC_VEX_OPSIZE: 148 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE)) || 149 inheritsFrom(child, IC_VEX_W_OPSIZE) || 150 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE)); 151 case IC_VEX_W: 152 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W); 153 case IC_VEX_W_XS: 154 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS); 155 case IC_VEX_W_XD: 156 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD); 157 case IC_VEX_W_OPSIZE: 158 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE); 159 case IC_VEX_L: 160 return inheritsFrom(child, IC_VEX_L_W); 161 case IC_VEX_L_XS: 162 return inheritsFrom(child, IC_VEX_L_W_XS); 163 case IC_VEX_L_XD: 164 return inheritsFrom(child, IC_VEX_L_W_XD); 165 case IC_VEX_L_OPSIZE: 166 return inheritsFrom(child, IC_VEX_L_W_OPSIZE); 167 case IC_VEX_L_W: 168 case IC_VEX_L_W_XS: 169 case IC_VEX_L_W_XD: 170 case IC_VEX_L_W_OPSIZE: 171 return false; 172 case IC_EVEX: 173 return inheritsFrom(child, IC_EVEX_W) || 174 inheritsFrom(child, IC_EVEX_L_W); 175 case IC_EVEX_XS: 176 return inheritsFrom(child, IC_EVEX_W_XS) || 177 inheritsFrom(child, IC_EVEX_L_W_XS); 178 case IC_EVEX_XD: 179 return inheritsFrom(child, IC_EVEX_W_XD) || 180 inheritsFrom(child, IC_EVEX_L_W_XD); 181 case IC_EVEX_OPSIZE: 182 return inheritsFrom(child, IC_EVEX_W_OPSIZE) || 183 inheritsFrom(child, IC_EVEX_L_W_OPSIZE); 184 case IC_EVEX_B: 185 return false; 186 case IC_EVEX_W: 187 case IC_EVEX_W_XS: 188 case IC_EVEX_W_XD: 189 case IC_EVEX_W_OPSIZE: 190 return false; 191 case IC_EVEX_L: 192 case IC_EVEX_L_K_B: 193 case IC_EVEX_L_KZ_B: 194 case IC_EVEX_L_B: 195 case IC_EVEX_L_XS: 196 case IC_EVEX_L_XD: 197 case IC_EVEX_L_OPSIZE: 198 return false; 199 case IC_EVEX_L_W: 200 case IC_EVEX_L_W_XS: 201 case IC_EVEX_L_W_XD: 202 case IC_EVEX_L_W_OPSIZE: 203 return false; 204 case IC_EVEX_L2: 205 case IC_EVEX_L2_XS: 206 case IC_EVEX_L2_XD: 207 case IC_EVEX_L2_OPSIZE: 208 return false; 209 case IC_EVEX_L2_W: 210 case IC_EVEX_L2_W_XS: 211 case IC_EVEX_L2_W_XD: 212 case IC_EVEX_L2_W_OPSIZE: 213 return false; 214 case IC_EVEX_K: 215 return inheritsFrom(child, IC_EVEX_W_K) || 216 inheritsFrom(child, IC_EVEX_L_W_K); 217 case IC_EVEX_XS_K: 218 case IC_EVEX_XS_K_B: 219 case IC_EVEX_XS_KZ_B: 220 return inheritsFrom(child, IC_EVEX_W_XS_K) || 221 inheritsFrom(child, IC_EVEX_L_W_XS_K); 222 case IC_EVEX_XD_K: 223 case IC_EVEX_XD_K_B: 224 case IC_EVEX_XD_KZ_B: 225 return inheritsFrom(child, IC_EVEX_W_XD_K) || 226 inheritsFrom(child, IC_EVEX_L_W_XD_K); 227 case IC_EVEX_XS_B: 228 case IC_EVEX_XD_B: 229 case IC_EVEX_K_B: 230 case IC_EVEX_KZ: 231 return false; 232 case IC_EVEX_XS_KZ: 233 return inheritsFrom(child, IC_EVEX_W_XS_KZ) || 234 inheritsFrom(child, IC_EVEX_L_W_XS_KZ); 235 case IC_EVEX_XD_KZ: 236 return inheritsFrom(child, IC_EVEX_W_XD_KZ) || 237 inheritsFrom(child, IC_EVEX_L_W_XD_KZ); 238 case IC_EVEX_KZ_B: 239 case IC_EVEX_OPSIZE_K: 240 case IC_EVEX_OPSIZE_B: 241 case IC_EVEX_OPSIZE_K_B: 242 case IC_EVEX_OPSIZE_KZ: 243 case IC_EVEX_OPSIZE_KZ_B: 244 return false; 245 case IC_EVEX_W_K: 246 case IC_EVEX_W_XS_K: 247 case IC_EVEX_W_XD_K: 248 case IC_EVEX_W_OPSIZE_K: 249 case IC_EVEX_W_OPSIZE_B: 250 case IC_EVEX_W_OPSIZE_K_B: 251 return false; 252 case IC_EVEX_L_K: 253 case IC_EVEX_L_XS_K: 254 case IC_EVEX_L_XD_K: 255 case IC_EVEX_L_OPSIZE_K: 256 case IC_EVEX_L_OPSIZE_B: 257 case IC_EVEX_L_OPSIZE_K_B: 258 return false; 259 case IC_EVEX_W_KZ: 260 case IC_EVEX_W_XS_KZ: 261 case IC_EVEX_W_XD_KZ: 262 case IC_EVEX_W_XS_B: 263 case IC_EVEX_W_XD_B: 264 case IC_EVEX_W_XS_K_B: 265 case IC_EVEX_W_XD_K_B: 266 case IC_EVEX_W_XS_KZ_B: 267 case IC_EVEX_W_XD_KZ_B: 268 case IC_EVEX_W_OPSIZE_KZ: 269 case IC_EVEX_W_OPSIZE_KZ_B: 270 return false; 271 case IC_EVEX_L_KZ: 272 case IC_EVEX_L_XS_KZ: 273 case IC_EVEX_L_XS_B: 274 case IC_EVEX_L_XS_K_B: 275 case IC_EVEX_L_XD_KZ: 276 case IC_EVEX_L_OPSIZE_KZ: 277 case IC_EVEX_L_OPSIZE_KZ_B: 278 return false; 279 case IC_EVEX_L_W_K: 280 case IC_EVEX_L_W_XS_K: 281 case IC_EVEX_L_W_XS_B: 282 case IC_EVEX_L_W_XS_K_B: 283 case IC_EVEX_L_W_XD_K: 284 case IC_EVEX_L_W_OPSIZE_K: 285 case IC_EVEX_L_W_OPSIZE_B: 286 case IC_EVEX_L_W_OPSIZE_K_B: 287 case IC_EVEX_L_W_KZ: 288 case IC_EVEX_L_W_XS_KZ: 289 case IC_EVEX_L_W_XD_KZ: 290 case IC_EVEX_L_W_OPSIZE_KZ: 291 case IC_EVEX_L_W_OPSIZE_KZ_B: 292 return false; 293 case IC_EVEX_L2_K: 294 case IC_EVEX_L2_B: 295 case IC_EVEX_L2_K_B: 296 case IC_EVEX_L2_KZ_B: 297 case IC_EVEX_L2_XS_K: 298 case IC_EVEX_L2_XS_K_B: 299 case IC_EVEX_L2_XS_B: 300 case IC_EVEX_L2_XD_B: 301 case IC_EVEX_L2_XD_K: 302 case IC_EVEX_L2_OPSIZE_K: 303 case IC_EVEX_L2_OPSIZE_B: 304 case IC_EVEX_L2_OPSIZE_K_B: 305 case IC_EVEX_L2_KZ: 306 case IC_EVEX_L2_XS_KZ: 307 case IC_EVEX_L2_XD_KZ: 308 case IC_EVEX_L2_OPSIZE_KZ: 309 case IC_EVEX_L2_OPSIZE_KZ_B: 310 return false; 311 case IC_EVEX_L2_W_K: 312 case IC_EVEX_L2_W_B: 313 case IC_EVEX_L2_W_XS_K: 314 case IC_EVEX_L2_W_XS_B: 315 case IC_EVEX_L2_W_XS_K_B: 316 case IC_EVEX_L2_W_XD_K: 317 case IC_EVEX_L2_W_XD_B: 318 case IC_EVEX_L2_W_OPSIZE_K: 319 case IC_EVEX_L2_W_OPSIZE_B: 320 case IC_EVEX_L2_W_OPSIZE_K_B: 321 case IC_EVEX_L2_W_KZ: 322 case IC_EVEX_L2_W_XS_KZ: 323 case IC_EVEX_L2_W_XD_KZ: 324 case IC_EVEX_L2_W_OPSIZE_KZ: 325 case IC_EVEX_L2_W_OPSIZE_KZ_B: 326 return false; 327 default: 328 errs() << "Unknown instruction class: " << 329 stringForContext((InstructionContext)parent) << "\n"; 330 llvm_unreachable("Unknown instruction class"); 331 } 332 } 333 334 /// outranks - Indicates whether, if an instruction has two different applicable 335 /// classes, which class should be preferred when performing decode. This 336 /// imposes a total ordering (ties are resolved toward "lower") 337 /// 338 /// @param upper - The class that may be preferable 339 /// @param lower - The class that may be less preferable 340 /// @return - True if upper is to be preferred, false otherwise. 341 static inline bool outranks(InstructionContext upper, 342 InstructionContext lower) { 343 assert(upper < IC_max); 344 assert(lower < IC_max); 345 346 #define ENUM_ENTRY(n, r, d) r, 347 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) \ 348 ENUM_ENTRY(n##_K_B, r, d) ENUM_ENTRY(n##_KZ_B, r, d) \ 349 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d) 350 static int ranks[IC_max] = { 351 INSTRUCTION_CONTEXTS 352 }; 353 #undef ENUM_ENTRY 354 #undef ENUM_ENTRY_K_B 355 356 return (ranks[upper] > ranks[lower]); 357 } 358 359 /// getDecisionType - Determines whether a ModRM decision with 255 entries can 360 /// be compacted by eliminating redundant information. 361 /// 362 /// @param decision - The decision to be compacted. 363 /// @return - The compactest available representation for the decision. 364 static ModRMDecisionType getDecisionType(ModRMDecision &decision) { 365 bool satisfiesOneEntry = true; 366 bool satisfiesSplitRM = true; 367 bool satisfiesSplitReg = true; 368 bool satisfiesSplitMisc = true; 369 370 for (unsigned index = 0; index < 256; ++index) { 371 if (decision.instructionIDs[index] != decision.instructionIDs[0]) 372 satisfiesOneEntry = false; 373 374 if (((index & 0xc0) == 0xc0) && 375 (decision.instructionIDs[index] != decision.instructionIDs[0xc0])) 376 satisfiesSplitRM = false; 377 378 if (((index & 0xc0) != 0xc0) && 379 (decision.instructionIDs[index] != decision.instructionIDs[0x00])) 380 satisfiesSplitRM = false; 381 382 if (((index & 0xc0) == 0xc0) && 383 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8])) 384 satisfiesSplitReg = false; 385 386 if (((index & 0xc0) != 0xc0) && 387 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38])) 388 satisfiesSplitMisc = false; 389 } 390 391 if (satisfiesOneEntry) 392 return MODRM_ONEENTRY; 393 394 if (satisfiesSplitRM) 395 return MODRM_SPLITRM; 396 397 if (satisfiesSplitReg && satisfiesSplitMisc) 398 return MODRM_SPLITREG; 399 400 if (satisfiesSplitMisc) 401 return MODRM_SPLITMISC; 402 403 return MODRM_FULL; 404 } 405 406 /// stringForDecisionType - Returns a statically-allocated string corresponding 407 /// to a particular decision type. 408 /// 409 /// @param dt - The decision type. 410 /// @return - A pointer to the statically-allocated string (e.g., 411 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY). 412 static const char* stringForDecisionType(ModRMDecisionType dt) { 413 #define ENUM_ENTRY(n) case n: return #n; 414 switch (dt) { 415 default: 416 llvm_unreachable("Unknown decision type"); 417 MODRMTYPES 418 }; 419 #undef ENUM_ENTRY 420 } 421 422 DisassemblerTables::DisassemblerTables() { 423 unsigned i; 424 425 for (i = 0; i < array_lengthof(Tables); i++) { 426 Tables[i] = new ContextDecision; 427 memset(Tables[i], 0, sizeof(ContextDecision)); 428 } 429 430 HasConflicts = false; 431 } 432 433 DisassemblerTables::~DisassemblerTables() { 434 unsigned i; 435 436 for (i = 0; i < array_lengthof(Tables); i++) 437 delete Tables[i]; 438 } 439 440 void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2, 441 unsigned &i1, unsigned &i2, 442 unsigned &ModRMTableNum, 443 ModRMDecision &decision) const { 444 static uint32_t sTableNumber = 0; 445 static uint32_t sEntryNumber = 1; 446 ModRMDecisionType dt = getDecisionType(decision); 447 448 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0) 449 { 450 o2.indent(i2) << "{ /* ModRMDecision */" << "\n"; 451 i2++; 452 453 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n"; 454 o2.indent(i2) << 0 << " /* EmptyTable */\n"; 455 456 i2--; 457 o2.indent(i2) << "}"; 458 return; 459 } 460 461 std::vector<unsigned> ModRMDecision; 462 463 switch (dt) { 464 default: 465 llvm_unreachable("Unknown decision type"); 466 case MODRM_ONEENTRY: 467 ModRMDecision.push_back(decision.instructionIDs[0]); 468 break; 469 case MODRM_SPLITRM: 470 ModRMDecision.push_back(decision.instructionIDs[0x00]); 471 ModRMDecision.push_back(decision.instructionIDs[0xc0]); 472 break; 473 case MODRM_SPLITREG: 474 for (unsigned index = 0; index < 64; index += 8) 475 ModRMDecision.push_back(decision.instructionIDs[index]); 476 for (unsigned index = 0xc0; index < 256; index += 8) 477 ModRMDecision.push_back(decision.instructionIDs[index]); 478 break; 479 case MODRM_SPLITMISC: 480 for (unsigned index = 0; index < 64; index += 8) 481 ModRMDecision.push_back(decision.instructionIDs[index]); 482 for (unsigned index = 0xc0; index < 256; ++index) 483 ModRMDecision.push_back(decision.instructionIDs[index]); 484 break; 485 case MODRM_FULL: 486 for (unsigned index = 0; index < 256; ++index) 487 ModRMDecision.push_back(decision.instructionIDs[index]); 488 break; 489 } 490 491 unsigned &EntryNumber = ModRMTable[ModRMDecision]; 492 if (EntryNumber == 0) { 493 EntryNumber = ModRMTableNum; 494 495 ModRMTableNum += ModRMDecision.size(); 496 o1 << "/* Table" << EntryNumber << " */\n"; 497 i1++; 498 for (std::vector<unsigned>::const_iterator I = ModRMDecision.begin(), 499 E = ModRMDecision.end(); I != E; ++I) { 500 o1.indent(i1 * 2) << format("0x%hx", *I) << ", /* " 501 << InstructionSpecifiers[*I].name << " */\n"; 502 } 503 i1--; 504 } 505 506 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n"; 507 i2++; 508 509 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n"; 510 o2.indent(i2) << EntryNumber << " /* Table" << EntryNumber << " */\n"; 511 512 i2--; 513 o2.indent(i2) << "}"; 514 515 switch (dt) { 516 default: 517 llvm_unreachable("Unknown decision type"); 518 case MODRM_ONEENTRY: 519 sEntryNumber += 1; 520 break; 521 case MODRM_SPLITRM: 522 sEntryNumber += 2; 523 break; 524 case MODRM_SPLITREG: 525 sEntryNumber += 16; 526 break; 527 case MODRM_SPLITMISC: 528 sEntryNumber += 8 + 64; 529 break; 530 case MODRM_FULL: 531 sEntryNumber += 256; 532 break; 533 } 534 535 // We assume that the index can fit into uint16_t. 536 assert(sEntryNumber < 65536U && 537 "Index into ModRMDecision is too large for uint16_t!"); 538 539 ++sTableNumber; 540 } 541 542 void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2, 543 unsigned &i1, unsigned &i2, 544 unsigned &ModRMTableNum, 545 OpcodeDecision &decision) const { 546 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n"; 547 i2++; 548 o2.indent(i2) << "{" << "\n"; 549 i2++; 550 551 for (unsigned index = 0; index < 256; ++index) { 552 o2.indent(i2); 553 554 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n"; 555 556 emitModRMDecision(o1, o2, i1, i2, ModRMTableNum, 557 decision.modRMDecisions[index]); 558 559 if (index < 255) 560 o2 << ","; 561 562 o2 << "\n"; 563 } 564 565 i2--; 566 o2.indent(i2) << "}" << "\n"; 567 i2--; 568 o2.indent(i2) << "}" << "\n"; 569 } 570 571 void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2, 572 unsigned &i1, unsigned &i2, 573 unsigned &ModRMTableNum, 574 ContextDecision &decision, 575 const char* name) const { 576 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n"; 577 i2++; 578 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n"; 579 i2++; 580 581 for (unsigned index = 0; index < IC_max; ++index) { 582 o2.indent(i2) << "/* "; 583 o2 << stringForContext((InstructionContext)index); 584 o2 << " */"; 585 o2 << "\n"; 586 587 emitOpcodeDecision(o1, o2, i1, i2, ModRMTableNum, 588 decision.opcodeDecisions[index]); 589 590 if (index + 1 < IC_max) 591 o2 << ", "; 592 } 593 594 i2--; 595 o2.indent(i2) << "}" << "\n"; 596 i2--; 597 o2.indent(i2) << "};" << "\n"; 598 } 599 600 void DisassemblerTables::emitInstructionInfo(raw_ostream &o, 601 unsigned &i) const { 602 unsigned NumInstructions = InstructionSpecifiers.size(); 603 604 o << "static const struct OperandSpecifier x86OperandSets[][" 605 << X86_MAX_OPERANDS << "] = {\n"; 606 607 typedef SmallVector<std::pair<OperandEncoding, OperandType>, 608 X86_MAX_OPERANDS> OperandListTy; 609 std::map<OperandListTy, unsigned> OperandSets; 610 611 unsigned OperandSetNum = 0; 612 for (unsigned Index = 0; Index < NumInstructions; ++Index) { 613 OperandListTy OperandList; 614 615 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS; 616 ++OperandIndex) { 617 OperandEncoding Encoding = (OperandEncoding)InstructionSpecifiers[Index] 618 .operands[OperandIndex].encoding; 619 OperandType Type = (OperandType)InstructionSpecifiers[Index] 620 .operands[OperandIndex].type; 621 OperandList.push_back(std::make_pair(Encoding, Type)); 622 } 623 unsigned &N = OperandSets[OperandList]; 624 if (N != 0) continue; 625 626 N = ++OperandSetNum; 627 628 o << " { /* " << (OperandSetNum - 1) << " */\n"; 629 for (unsigned i = 0, e = OperandList.size(); i != e; ++i) { 630 const char *Encoding = stringForOperandEncoding(OperandList[i].first); 631 const char *Type = stringForOperandType(OperandList[i].second); 632 o << " { " << Encoding << ", " << Type << " },\n"; 633 } 634 o << " },\n"; 635 } 636 o << "};" << "\n\n"; 637 638 o.indent(i * 2) << "static const struct InstructionSpecifier "; 639 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n"; 640 641 i++; 642 643 for (unsigned index = 0; index < NumInstructions; ++index) { 644 o.indent(i * 2) << "{ /* " << index << " */\n"; 645 i++; 646 647 OperandListTy OperandList; 648 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS; 649 ++OperandIndex) { 650 OperandEncoding Encoding = (OperandEncoding)InstructionSpecifiers[index] 651 .operands[OperandIndex].encoding; 652 OperandType Type = (OperandType)InstructionSpecifiers[index] 653 .operands[OperandIndex].type; 654 OperandList.push_back(std::make_pair(Encoding, Type)); 655 } 656 o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n"; 657 658 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */\n"; 659 660 i--; 661 o.indent(i * 2) << "},\n"; 662 } 663 664 i--; 665 o.indent(i * 2) << "};" << "\n"; 666 } 667 668 void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const { 669 const unsigned int tableSize = 16384; 670 o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR 671 "[" << tableSize << "] = {\n"; 672 i++; 673 674 for (unsigned index = 0; index < tableSize; ++index) { 675 o.indent(i * 2); 676 677 if (index & ATTR_EVEX) { 678 o << "IC_EVEX"; 679 if (index & ATTR_EVEXL2) 680 o << "_L2"; 681 else if (index & ATTR_EVEXL) 682 o << "_L"; 683 if (index & ATTR_REXW) 684 o << "_W"; 685 if (index & ATTR_OPSIZE) 686 o << "_OPSIZE"; 687 else if (index & ATTR_XD) 688 o << "_XD"; 689 else if (index & ATTR_XS) 690 o << "_XS"; 691 if (index & ATTR_EVEXKZ) 692 o << "_KZ"; 693 else if (index & ATTR_EVEXK) 694 o << "_K"; 695 if (index & ATTR_EVEXB) 696 o << "_B"; 697 } 698 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE)) 699 o << "IC_VEX_L_W_OPSIZE"; 700 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XD)) 701 o << "IC_VEX_L_W_XD"; 702 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XS)) 703 o << "IC_VEX_L_W_XS"; 704 else if ((index & ATTR_VEXL) && (index & ATTR_REXW)) 705 o << "IC_VEX_L_W"; 706 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE)) 707 o << "IC_VEX_L_OPSIZE"; 708 else if ((index & ATTR_VEXL) && (index & ATTR_XD)) 709 o << "IC_VEX_L_XD"; 710 else if ((index & ATTR_VEXL) && (index & ATTR_XS)) 711 o << "IC_VEX_L_XS"; 712 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE)) 713 o << "IC_VEX_W_OPSIZE"; 714 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD)) 715 o << "IC_VEX_W_XD"; 716 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS)) 717 o << "IC_VEX_W_XS"; 718 else if (index & ATTR_VEXL) 719 o << "IC_VEX_L"; 720 else if ((index & ATTR_VEX) && (index & ATTR_REXW)) 721 o << "IC_VEX_W"; 722 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE)) 723 o << "IC_VEX_OPSIZE"; 724 else if ((index & ATTR_VEX) && (index & ATTR_XD)) 725 o << "IC_VEX_XD"; 726 else if ((index & ATTR_VEX) && (index & ATTR_XS)) 727 o << "IC_VEX_XS"; 728 else if (index & ATTR_VEX) 729 o << "IC_VEX"; 730 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS)) 731 o << "IC_64BIT_REXW_XS"; 732 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD)) 733 o << "IC_64BIT_REXW_XD"; 734 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && 735 (index & ATTR_OPSIZE)) 736 o << "IC_64BIT_REXW_OPSIZE"; 737 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && 738 (index & ATTR_ADSIZE)) 739 o << "IC_64BIT_REXW_ADSIZE"; 740 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE)) 741 o << "IC_64BIT_XD_OPSIZE"; 742 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE)) 743 o << "IC_64BIT_XS_OPSIZE"; 744 else if ((index & ATTR_64BIT) && (index & ATTR_XS)) 745 o << "IC_64BIT_XS"; 746 else if ((index & ATTR_64BIT) && (index & ATTR_XD)) 747 o << "IC_64BIT_XD"; 748 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE) && 749 (index & ATTR_ADSIZE)) 750 o << "IC_64BIT_OPSIZE_ADSIZE"; 751 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE)) 752 o << "IC_64BIT_OPSIZE"; 753 else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE)) 754 o << "IC_64BIT_ADSIZE"; 755 else if ((index & ATTR_64BIT) && (index & ATTR_REXW)) 756 o << "IC_64BIT_REXW"; 757 else if ((index & ATTR_64BIT)) 758 o << "IC_64BIT"; 759 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE)) 760 o << "IC_XS_OPSIZE"; 761 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE)) 762 o << "IC_XD_OPSIZE"; 763 else if (index & ATTR_XS) 764 o << "IC_XS"; 765 else if (index & ATTR_XD) 766 o << "IC_XD"; 767 else if ((index & ATTR_OPSIZE) && (index & ATTR_ADSIZE)) 768 o << "IC_OPSIZE_ADSIZE"; 769 else if (index & ATTR_OPSIZE) 770 o << "IC_OPSIZE"; 771 else if (index & ATTR_ADSIZE) 772 o << "IC_ADSIZE"; 773 else 774 o << "IC"; 775 776 if (index < tableSize - 1) 777 o << ","; 778 else 779 o << " "; 780 781 o << " /* " << index << " */"; 782 783 o << "\n"; 784 } 785 786 i--; 787 o.indent(i * 2) << "};" << "\n"; 788 } 789 790 void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2, 791 unsigned &i1, unsigned &i2, 792 unsigned &ModRMTableNum) const { 793 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[0], ONEBYTE_STR); 794 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[1], TWOBYTE_STR); 795 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[2], THREEBYTE38_STR); 796 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[3], THREEBYTE3A_STR); 797 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[4], XOP8_MAP_STR); 798 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[5], XOP9_MAP_STR); 799 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[6], XOPA_MAP_STR); 800 } 801 802 void DisassemblerTables::emit(raw_ostream &o) const { 803 unsigned i1 = 0; 804 unsigned i2 = 0; 805 806 std::string s1; 807 std::string s2; 808 809 raw_string_ostream o1(s1); 810 raw_string_ostream o2(s2); 811 812 emitInstructionInfo(o, i2); 813 o << "\n"; 814 815 emitContextTable(o, i2); 816 o << "\n"; 817 818 unsigned ModRMTableNum = 0; 819 820 o << "static const InstrUID modRMTable[] = {\n"; 821 i1++; 822 std::vector<unsigned> EmptyTable(1, 0); 823 ModRMTable[EmptyTable] = ModRMTableNum; 824 ModRMTableNum += EmptyTable.size(); 825 o1 << "/* EmptyTable */\n"; 826 o1.indent(i1 * 2) << "0x0,\n"; 827 i1--; 828 emitContextDecisions(o1, o2, i1, i2, ModRMTableNum); 829 830 o << o1.str(); 831 o << " 0x0\n"; 832 o << "};\n"; 833 o << "\n"; 834 o << o2.str(); 835 o << "\n"; 836 o << "\n"; 837 } 838 839 void DisassemblerTables::setTableFields(ModRMDecision &decision, 840 const ModRMFilter &filter, 841 InstrUID uid, 842 uint8_t opcode) { 843 for (unsigned index = 0; index < 256; ++index) { 844 if (filter.accepts(index)) { 845 if (decision.instructionIDs[index] == uid) 846 continue; 847 848 if (decision.instructionIDs[index] != 0) { 849 InstructionSpecifier &newInfo = 850 InstructionSpecifiers[uid]; 851 InstructionSpecifier &previousInfo = 852 InstructionSpecifiers[decision.instructionIDs[index]]; 853 854 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" || 855 newInfo.name == "XCHG32ar" || 856 newInfo.name == "XCHG32ar64" || 857 newInfo.name == "XCHG64ar")) 858 continue; // special case for XCHG*ar and NOOP 859 860 if (outranks(previousInfo.insnContext, newInfo.insnContext)) 861 continue; 862 863 if (previousInfo.insnContext == newInfo.insnContext) { 864 errs() << "Error: Primary decode conflict: "; 865 errs() << newInfo.name << " would overwrite " << previousInfo.name; 866 errs() << "\n"; 867 errs() << "ModRM " << index << "\n"; 868 errs() << "Opcode " << (uint16_t)opcode << "\n"; 869 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n"; 870 HasConflicts = true; 871 } 872 } 873 874 decision.instructionIDs[index] = uid; 875 } 876 } 877 } 878 879 void DisassemblerTables::setTableFields(OpcodeType type, 880 InstructionContext insnContext, 881 uint8_t opcode, 882 const ModRMFilter &filter, 883 InstrUID uid, 884 bool is32bit, 885 bool ignoresVEX_L, 886 unsigned addressSize) { 887 ContextDecision &decision = *Tables[type]; 888 889 for (unsigned index = 0; index < IC_max; ++index) { 890 if ((is32bit || addressSize == 16) && 891 inheritsFrom((InstructionContext)index, IC_64BIT)) 892 continue; 893 894 bool adSize64 = addressSize == 64; 895 if (inheritsFrom((InstructionContext)index, 896 InstructionSpecifiers[uid].insnContext, ignoresVEX_L, 897 adSize64)) 898 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode], 899 filter, 900 uid, 901 opcode); 902 } 903 } 904