1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler Emitter. 11 // It contains the implementation of the disassembler tables. 12 // Documentation for the disassembler emitter in general can be found in 13 // X86DisasemblerEmitter.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "X86DisassemblerShared.h" 18 #include "X86DisassemblerTables.h" 19 20 #include "llvm/TableGen/TableGenBackend.h" 21 #include "llvm/ADT/STLExtras.h" 22 #include "llvm/Support/ErrorHandling.h" 23 #include "llvm/Support/Format.h" 24 25 using namespace llvm; 26 using namespace X86Disassembler; 27 28 /// inheritsFrom - Indicates whether all instructions in one class also belong 29 /// to another class. 30 /// 31 /// @param child - The class that may be the subset 32 /// @param parent - The class that may be the superset 33 /// @return - True if child is a subset of parent, false otherwise. 34 static inline bool inheritsFrom(InstructionContext child, 35 InstructionContext parent, 36 bool VEX_LIG = false) { 37 if (child == parent) 38 return true; 39 40 switch (parent) { 41 case IC: 42 return(inheritsFrom(child, IC_64BIT) || 43 inheritsFrom(child, IC_OPSIZE) || 44 inheritsFrom(child, IC_XD) || 45 inheritsFrom(child, IC_XS)); 46 case IC_64BIT: 47 return(inheritsFrom(child, IC_64BIT_REXW) || 48 inheritsFrom(child, IC_64BIT_OPSIZE) || 49 inheritsFrom(child, IC_64BIT_XD) || 50 inheritsFrom(child, IC_64BIT_XS)); 51 case IC_OPSIZE: 52 return inheritsFrom(child, IC_64BIT_OPSIZE); 53 case IC_XD: 54 return inheritsFrom(child, IC_64BIT_XD); 55 case IC_XS: 56 return inheritsFrom(child, IC_64BIT_XS); 57 case IC_XD_OPSIZE: 58 return inheritsFrom(child, IC_64BIT_XD_OPSIZE); 59 case IC_XS_OPSIZE: 60 return inheritsFrom(child, IC_64BIT_XS_OPSIZE); 61 case IC_64BIT_REXW: 62 return(inheritsFrom(child, IC_64BIT_REXW_XS) || 63 inheritsFrom(child, IC_64BIT_REXW_XD) || 64 inheritsFrom(child, IC_64BIT_REXW_OPSIZE)); 65 case IC_64BIT_OPSIZE: 66 return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE)); 67 case IC_64BIT_XD: 68 return(inheritsFrom(child, IC_64BIT_REXW_XD)); 69 case IC_64BIT_XS: 70 return(inheritsFrom(child, IC_64BIT_REXW_XS)); 71 case IC_64BIT_XD_OPSIZE: 72 case IC_64BIT_XS_OPSIZE: 73 return false; 74 case IC_64BIT_REXW_XD: 75 case IC_64BIT_REXW_XS: 76 case IC_64BIT_REXW_OPSIZE: 77 return false; 78 case IC_VEX: 79 return inheritsFrom(child, IC_VEX_W) || 80 (VEX_LIG && inheritsFrom(child, IC_VEX_L)); 81 case IC_VEX_XS: 82 return inheritsFrom(child, IC_VEX_W_XS) || 83 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS)); 84 case IC_VEX_XD: 85 return inheritsFrom(child, IC_VEX_W_XD) || 86 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD)); 87 case IC_VEX_OPSIZE: 88 return inheritsFrom(child, IC_VEX_W_OPSIZE) || 89 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE)); 90 case IC_VEX_W: 91 case IC_VEX_W_XS: 92 case IC_VEX_W_XD: 93 case IC_VEX_W_OPSIZE: 94 return false; 95 case IC_VEX_L: 96 case IC_VEX_L_XS: 97 case IC_VEX_L_XD: 98 return false; 99 case IC_VEX_L_OPSIZE: 100 return inheritsFrom(child, IC_VEX_L_W_OPSIZE); 101 case IC_VEX_L_W_OPSIZE: 102 return false; 103 default: 104 llvm_unreachable("Unknown instruction class"); 105 return false; 106 } 107 } 108 109 /// outranks - Indicates whether, if an instruction has two different applicable 110 /// classes, which class should be preferred when performing decode. This 111 /// imposes a total ordering (ties are resolved toward "lower") 112 /// 113 /// @param upper - The class that may be preferable 114 /// @param lower - The class that may be less preferable 115 /// @return - True if upper is to be preferred, false otherwise. 116 static inline bool outranks(InstructionContext upper, 117 InstructionContext lower) { 118 assert(upper < IC_max); 119 assert(lower < IC_max); 120 121 #define ENUM_ENTRY(n, r, d) r, 122 static int ranks[IC_max] = { 123 INSTRUCTION_CONTEXTS 124 }; 125 #undef ENUM_ENTRY 126 127 return (ranks[upper] > ranks[lower]); 128 } 129 130 /// stringForContext - Returns a string containing the name of a particular 131 /// InstructionContext, usually for diagnostic purposes. 132 /// 133 /// @param insnContext - The instruction class to transform to a string. 134 /// @return - A statically-allocated string constant that contains the 135 /// name of the instruction class. 136 static inline const char* stringForContext(InstructionContext insnContext) { 137 switch (insnContext) { 138 default: 139 llvm_unreachable("Unhandled instruction class"); 140 #define ENUM_ENTRY(n, r, d) case n: return #n; break; 141 INSTRUCTION_CONTEXTS 142 #undef ENUM_ENTRY 143 } 144 145 return 0; 146 } 147 148 /// stringForOperandType - Like stringForContext, but for OperandTypes. 149 static inline const char* stringForOperandType(OperandType type) { 150 switch (type) { 151 default: 152 llvm_unreachable("Unhandled type"); 153 #define ENUM_ENTRY(i, d) case i: return #i; 154 TYPES 155 #undef ENUM_ENTRY 156 } 157 } 158 159 /// stringForOperandEncoding - like stringForContext, but for 160 /// OperandEncodings. 161 static inline const char* stringForOperandEncoding(OperandEncoding encoding) { 162 switch (encoding) { 163 default: 164 llvm_unreachable("Unhandled encoding"); 165 #define ENUM_ENTRY(i, d) case i: return #i; 166 ENCODINGS 167 #undef ENUM_ENTRY 168 } 169 } 170 171 void DisassemblerTables::emitOneID(raw_ostream &o, 172 uint32_t &i, 173 InstrUID id, 174 bool addComma) const { 175 if (id) 176 o.indent(i * 2) << format("0x%hx", id); 177 else 178 o.indent(i * 2) << 0; 179 180 if (addComma) 181 o << ", "; 182 else 183 o << " "; 184 185 o << "/* "; 186 o << InstructionSpecifiers[id].name; 187 o << "*/"; 188 189 o << "\n"; 190 } 191 192 /// emitEmptyTable - Emits the modRMEmptyTable, which is used as a ID table by 193 /// all ModR/M decisions for instructions that are invalid for all possible 194 /// ModR/M byte values. 195 /// 196 /// @param o - The output stream on which to emit the table. 197 /// @param i - The indentation level for that output stream. 198 static void emitEmptyTable(raw_ostream &o, uint32_t &i) 199 { 200 o.indent(i * 2) << "static const InstrUID modRMEmptyTable[1] = { 0 };\n"; 201 o << "\n"; 202 } 203 204 /// getDecisionType - Determines whether a ModRM decision with 255 entries can 205 /// be compacted by eliminating redundant information. 206 /// 207 /// @param decision - The decision to be compacted. 208 /// @return - The compactest available representation for the decision. 209 static ModRMDecisionType getDecisionType(ModRMDecision &decision) 210 { 211 bool satisfiesOneEntry = true; 212 bool satisfiesSplitRM = true; 213 214 uint16_t index; 215 216 for (index = 0; index < 256; ++index) { 217 if (decision.instructionIDs[index] != decision.instructionIDs[0]) 218 satisfiesOneEntry = false; 219 220 if (((index & 0xc0) == 0xc0) && 221 (decision.instructionIDs[index] != decision.instructionIDs[0xc0])) 222 satisfiesSplitRM = false; 223 224 if (((index & 0xc0) != 0xc0) && 225 (decision.instructionIDs[index] != decision.instructionIDs[0x00])) 226 satisfiesSplitRM = false; 227 } 228 229 if (satisfiesOneEntry) 230 return MODRM_ONEENTRY; 231 232 if (satisfiesSplitRM) 233 return MODRM_SPLITRM; 234 235 return MODRM_FULL; 236 } 237 238 /// stringForDecisionType - Returns a statically-allocated string corresponding 239 /// to a particular decision type. 240 /// 241 /// @param dt - The decision type. 242 /// @return - A pointer to the statically-allocated string (e.g., 243 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY). 244 static const char* stringForDecisionType(ModRMDecisionType dt) 245 { 246 #define ENUM_ENTRY(n) case n: return #n; 247 switch (dt) { 248 default: 249 llvm_unreachable("Unknown decision type"); 250 MODRMTYPES 251 }; 252 #undef ENUM_ENTRY 253 } 254 255 /// stringForModifierType - Returns a statically-allocated string corresponding 256 /// to an opcode modifier type. 257 /// 258 /// @param mt - The modifier type. 259 /// @return - A pointer to the statically-allocated string (e.g., 260 /// "MODIFIER_NONE" for MODIFIER_NONE). 261 static const char* stringForModifierType(ModifierType mt) 262 { 263 #define ENUM_ENTRY(n) case n: return #n; 264 switch(mt) { 265 default: 266 llvm_unreachable("Unknown modifier type"); 267 MODIFIER_TYPES 268 }; 269 #undef ENUM_ENTRY 270 } 271 272 DisassemblerTables::DisassemblerTables() { 273 unsigned i; 274 275 for (i = 0; i < array_lengthof(Tables); i++) { 276 Tables[i] = new ContextDecision; 277 memset(Tables[i], 0, sizeof(ContextDecision)); 278 } 279 280 HasConflicts = false; 281 } 282 283 DisassemblerTables::~DisassemblerTables() { 284 unsigned i; 285 286 for (i = 0; i < array_lengthof(Tables); i++) 287 delete Tables[i]; 288 } 289 290 void DisassemblerTables::emitModRMDecision(raw_ostream &o1, 291 raw_ostream &o2, 292 uint32_t &i1, 293 uint32_t &i2, 294 ModRMDecision &decision) 295 const { 296 static uint64_t sTableNumber = 0; 297 uint64_t thisTableNumber = sTableNumber; 298 ModRMDecisionType dt = getDecisionType(decision); 299 uint16_t index; 300 301 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0) 302 { 303 o2.indent(i2) << "{ /* ModRMDecision */" << "\n"; 304 i2++; 305 306 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n"; 307 o2.indent(i2) << "modRMEmptyTable"; 308 309 i2--; 310 o2.indent(i2) << "}"; 311 return; 312 } 313 314 o1.indent(i1) << "static const InstrUID modRMTable" << thisTableNumber; 315 316 switch (dt) { 317 default: 318 llvm_unreachable("Unknown decision type"); 319 case MODRM_ONEENTRY: 320 o1 << "[1]"; 321 break; 322 case MODRM_SPLITRM: 323 o1 << "[2]"; 324 break; 325 case MODRM_FULL: 326 o1 << "[256]"; 327 break; 328 } 329 330 o1 << " = {" << "\n"; 331 i1++; 332 333 switch (dt) { 334 default: 335 llvm_unreachable("Unknown decision type"); 336 case MODRM_ONEENTRY: 337 emitOneID(o1, i1, decision.instructionIDs[0], false); 338 break; 339 case MODRM_SPLITRM: 340 emitOneID(o1, i1, decision.instructionIDs[0x00], true); // mod = 0b00 341 emitOneID(o1, i1, decision.instructionIDs[0xc0], false); // mod = 0b11 342 break; 343 case MODRM_FULL: 344 for (index = 0; index < 256; ++index) 345 emitOneID(o1, i1, decision.instructionIDs[index], index < 255); 346 break; 347 } 348 349 i1--; 350 o1.indent(i1) << "};" << "\n"; 351 o1 << "\n"; 352 353 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n"; 354 i2++; 355 356 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n"; 357 o2.indent(i2) << "modRMTable" << sTableNumber << "\n"; 358 359 i2--; 360 o2.indent(i2) << "}"; 361 362 ++sTableNumber; 363 } 364 365 void DisassemblerTables::emitOpcodeDecision( 366 raw_ostream &o1, 367 raw_ostream &o2, 368 uint32_t &i1, 369 uint32_t &i2, 370 OpcodeDecision &decision) const { 371 uint16_t index; 372 373 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n"; 374 i2++; 375 o2.indent(i2) << "{" << "\n"; 376 i2++; 377 378 for (index = 0; index < 256; ++index) { 379 o2.indent(i2); 380 381 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n"; 382 383 emitModRMDecision(o1, o2, i1, i2, decision.modRMDecisions[index]); 384 385 if (index < 255) 386 o2 << ","; 387 388 o2 << "\n"; 389 } 390 391 i2--; 392 o2.indent(i2) << "}" << "\n"; 393 i2--; 394 o2.indent(i2) << "}" << "\n"; 395 } 396 397 void DisassemblerTables::emitContextDecision( 398 raw_ostream &o1, 399 raw_ostream &o2, 400 uint32_t &i1, 401 uint32_t &i2, 402 ContextDecision &decision, 403 const char* name) const { 404 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n"; 405 i2++; 406 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n"; 407 i2++; 408 409 unsigned index; 410 411 for (index = 0; index < IC_max; ++index) { 412 o2.indent(i2) << "/* "; 413 o2 << stringForContext((InstructionContext)index); 414 o2 << " */"; 415 o2 << "\n"; 416 417 emitOpcodeDecision(o1, o2, i1, i2, decision.opcodeDecisions[index]); 418 419 if (index + 1 < IC_max) 420 o2 << ", "; 421 } 422 423 i2--; 424 o2.indent(i2) << "}" << "\n"; 425 i2--; 426 o2.indent(i2) << "};" << "\n"; 427 } 428 429 void DisassemblerTables::emitInstructionInfo(raw_ostream &o, uint32_t &i) 430 const { 431 o.indent(i * 2) << "static const struct InstructionSpecifier "; 432 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n"; 433 434 i++; 435 436 uint16_t numInstructions = InstructionSpecifiers.size(); 437 uint16_t index, operandIndex; 438 439 for (index = 0; index < numInstructions; ++index) { 440 o.indent(i * 2) << "{ /* " << index << " */" << "\n"; 441 i++; 442 443 o.indent(i * 2) << 444 stringForModifierType(InstructionSpecifiers[index].modifierType); 445 o << "," << "\n"; 446 447 o.indent(i * 2) << "0x"; 448 o << format("%02hhx", (uint16_t)InstructionSpecifiers[index].modifierBase); 449 o << "," << "\n"; 450 451 o.indent(i * 2) << "{" << "\n"; 452 i++; 453 454 for (operandIndex = 0; operandIndex < X86_MAX_OPERANDS; ++operandIndex) { 455 o.indent(i * 2) << "{ "; 456 o << stringForOperandEncoding(InstructionSpecifiers[index] 457 .operands[operandIndex] 458 .encoding); 459 o << ", "; 460 o << stringForOperandType(InstructionSpecifiers[index] 461 .operands[operandIndex] 462 .type); 463 o << " }"; 464 465 if (operandIndex < X86_MAX_OPERANDS - 1) 466 o << ","; 467 468 o << "\n"; 469 } 470 471 i--; 472 o.indent(i * 2) << "}," << "\n"; 473 474 o.indent(i * 2) << "\"" << InstructionSpecifiers[index].name << "\""; 475 o << "\n"; 476 477 i--; 478 o.indent(i * 2) << "}"; 479 480 if (index + 1 < numInstructions) 481 o << ","; 482 483 o << "\n"; 484 } 485 486 i--; 487 o.indent(i * 2) << "};" << "\n"; 488 } 489 490 void DisassemblerTables::emitContextTable(raw_ostream &o, uint32_t &i) const { 491 uint16_t index; 492 493 o.indent(i * 2) << "static const InstructionContext " CONTEXTS_STR 494 "[256] = {\n"; 495 i++; 496 497 for (index = 0; index < 256; ++index) { 498 o.indent(i * 2); 499 500 if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE)) 501 o << "IC_VEX_L_W_OPSIZE"; 502 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE)) 503 o << "IC_VEX_L_OPSIZE"; 504 else if ((index & ATTR_VEXL) && (index & ATTR_XD)) 505 o << "IC_VEX_L_XD"; 506 else if ((index & ATTR_VEXL) && (index & ATTR_XS)) 507 o << "IC_VEX_L_XS"; 508 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE)) 509 o << "IC_VEX_W_OPSIZE"; 510 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD)) 511 o << "IC_VEX_W_XD"; 512 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS)) 513 o << "IC_VEX_W_XS"; 514 else if (index & ATTR_VEXL) 515 o << "IC_VEX_L"; 516 else if ((index & ATTR_VEX) && (index & ATTR_REXW)) 517 o << "IC_VEX_W"; 518 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE)) 519 o << "IC_VEX_OPSIZE"; 520 else if ((index & ATTR_VEX) && (index & ATTR_XD)) 521 o << "IC_VEX_XD"; 522 else if ((index & ATTR_VEX) && (index & ATTR_XS)) 523 o << "IC_VEX_XS"; 524 else if (index & ATTR_VEX) 525 o << "IC_VEX"; 526 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS)) 527 o << "IC_64BIT_REXW_XS"; 528 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD)) 529 o << "IC_64BIT_REXW_XD"; 530 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && 531 (index & ATTR_OPSIZE)) 532 o << "IC_64BIT_REXW_OPSIZE"; 533 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE)) 534 o << "IC_64BIT_XD_OPSIZE"; 535 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE)) 536 o << "IC_64BIT_XS_OPSIZE"; 537 else if ((index & ATTR_64BIT) && (index & ATTR_XS)) 538 o << "IC_64BIT_XS"; 539 else if ((index & ATTR_64BIT) && (index & ATTR_XD)) 540 o << "IC_64BIT_XD"; 541 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE)) 542 o << "IC_64BIT_OPSIZE"; 543 else if ((index & ATTR_64BIT) && (index & ATTR_REXW)) 544 o << "IC_64BIT_REXW"; 545 else if ((index & ATTR_64BIT)) 546 o << "IC_64BIT"; 547 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE)) 548 o << "IC_XS_OPSIZE"; 549 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE)) 550 o << "IC_XD_OPSIZE"; 551 else if (index & ATTR_XS) 552 o << "IC_XS"; 553 else if (index & ATTR_XD) 554 o << "IC_XD"; 555 else if (index & ATTR_OPSIZE) 556 o << "IC_OPSIZE"; 557 else 558 o << "IC"; 559 560 if (index < 255) 561 o << ","; 562 else 563 o << " "; 564 565 o << " /* " << index << " */"; 566 567 o << "\n"; 568 } 569 570 i--; 571 o.indent(i * 2) << "};" << "\n"; 572 } 573 574 void DisassemblerTables::emitContextDecisions(raw_ostream &o1, 575 raw_ostream &o2, 576 uint32_t &i1, 577 uint32_t &i2) 578 const { 579 emitContextDecision(o1, o2, i1, i2, *Tables[0], ONEBYTE_STR); 580 emitContextDecision(o1, o2, i1, i2, *Tables[1], TWOBYTE_STR); 581 emitContextDecision(o1, o2, i1, i2, *Tables[2], THREEBYTE38_STR); 582 emitContextDecision(o1, o2, i1, i2, *Tables[3], THREEBYTE3A_STR); 583 emitContextDecision(o1, o2, i1, i2, *Tables[4], THREEBYTEA6_STR); 584 emitContextDecision(o1, o2, i1, i2, *Tables[5], THREEBYTEA7_STR); 585 } 586 587 void DisassemblerTables::emit(raw_ostream &o) const { 588 uint32_t i1 = 0; 589 uint32_t i2 = 0; 590 591 std::string s1; 592 std::string s2; 593 594 raw_string_ostream o1(s1); 595 raw_string_ostream o2(s2); 596 597 emitInstructionInfo(o, i2); 598 o << "\n"; 599 600 emitContextTable(o, i2); 601 o << "\n"; 602 603 emitEmptyTable(o1, i1); 604 emitContextDecisions(o1, o2, i1, i2); 605 606 o << o1.str(); 607 o << "\n"; 608 o << o2.str(); 609 o << "\n"; 610 o << "\n"; 611 } 612 613 void DisassemblerTables::setTableFields(ModRMDecision &decision, 614 const ModRMFilter &filter, 615 InstrUID uid, 616 uint8_t opcode) { 617 unsigned index; 618 619 for (index = 0; index < 256; ++index) { 620 if (filter.accepts(index)) { 621 if (decision.instructionIDs[index] == uid) 622 continue; 623 624 if (decision.instructionIDs[index] != 0) { 625 InstructionSpecifier &newInfo = 626 InstructionSpecifiers[uid]; 627 InstructionSpecifier &previousInfo = 628 InstructionSpecifiers[decision.instructionIDs[index]]; 629 630 if(newInfo.filtered) 631 continue; // filtered instructions get lowest priority 632 633 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" || 634 newInfo.name == "XCHG32ar" || 635 newInfo.name == "XCHG32ar64" || 636 newInfo.name == "XCHG64ar")) 637 continue; // special case for XCHG*ar and NOOP 638 639 if (outranks(previousInfo.insnContext, newInfo.insnContext)) 640 continue; 641 642 if (previousInfo.insnContext == newInfo.insnContext && 643 !previousInfo.filtered) { 644 errs() << "Error: Primary decode conflict: "; 645 errs() << newInfo.name << " would overwrite " << previousInfo.name; 646 errs() << "\n"; 647 errs() << "ModRM " << index << "\n"; 648 errs() << "Opcode " << (uint16_t)opcode << "\n"; 649 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n"; 650 HasConflicts = true; 651 } 652 } 653 654 decision.instructionIDs[index] = uid; 655 } 656 } 657 } 658 659 void DisassemblerTables::setTableFields(OpcodeType type, 660 InstructionContext insnContext, 661 uint8_t opcode, 662 const ModRMFilter &filter, 663 InstrUID uid, 664 bool is32bit, 665 bool ignoresVEX_L) { 666 unsigned index; 667 668 ContextDecision &decision = *Tables[type]; 669 670 for (index = 0; index < IC_max; ++index) { 671 if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT)) 672 continue; 673 674 if (inheritsFrom((InstructionContext)index, 675 InstructionSpecifiers[uid].insnContext, ignoresVEX_L)) 676 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode], 677 filter, 678 uid, 679 opcode); 680 } 681 } 682