1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler Emitter. 11 // It contains the implementation of the disassembler tables. 12 // Documentation for the disassembler emitter in general can be found in 13 // X86DisasemblerEmitter.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "X86DisassemblerTables.h" 18 #include "X86DisassemblerShared.h" 19 #include "llvm/ADT/STLExtras.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include "llvm/Support/Format.h" 22 #include "llvm/TableGen/TableGenBackend.h" 23 #include <map> 24 25 using namespace llvm; 26 using namespace X86Disassembler; 27 28 /// stringForContext - Returns a string containing the name of a particular 29 /// InstructionContext, usually for diagnostic purposes. 30 /// 31 /// @param insnContext - The instruction class to transform to a string. 32 /// @return - A statically-allocated string constant that contains the 33 /// name of the instruction class. 34 static inline const char* stringForContext(InstructionContext insnContext) { 35 switch (insnContext) { 36 default: 37 llvm_unreachable("Unhandled instruction class"); 38 #define ENUM_ENTRY(n, r, d) case n: return #n; break; 39 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\ 40 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)\ 41 ENUM_ENTRY(n##_KZ_B, r, d) 42 INSTRUCTION_CONTEXTS 43 #undef ENUM_ENTRY 44 #undef ENUM_ENTRY_K_B 45 } 46 } 47 48 /// stringForOperandType - Like stringForContext, but for OperandTypes. 49 static inline const char* stringForOperandType(OperandType type) { 50 switch (type) { 51 default: 52 llvm_unreachable("Unhandled type"); 53 #define ENUM_ENTRY(i, d) case i: return #i; 54 TYPES 55 #undef ENUM_ENTRY 56 } 57 } 58 59 /// stringForOperandEncoding - like stringForContext, but for 60 /// OperandEncodings. 61 static inline const char* stringForOperandEncoding(OperandEncoding encoding) { 62 switch (encoding) { 63 default: 64 llvm_unreachable("Unhandled encoding"); 65 #define ENUM_ENTRY(i, d) case i: return #i; 66 ENCODINGS 67 #undef ENUM_ENTRY 68 } 69 } 70 71 /// inheritsFrom - Indicates whether all instructions in one class also belong 72 /// to another class. 73 /// 74 /// @param child - The class that may be the subset 75 /// @param parent - The class that may be the superset 76 /// @return - True if child is a subset of parent, false otherwise. 77 static inline bool inheritsFrom(InstructionContext child, 78 InstructionContext parent, 79 bool VEX_LIG = false) { 80 if (child == parent) 81 return true; 82 83 switch (parent) { 84 case IC: 85 return(inheritsFrom(child, IC_64BIT) || 86 inheritsFrom(child, IC_OPSIZE) || 87 inheritsFrom(child, IC_ADSIZE) || 88 inheritsFrom(child, IC_XD) || 89 inheritsFrom(child, IC_XS)); 90 case IC_64BIT: 91 return(inheritsFrom(child, IC_64BIT_REXW) || 92 inheritsFrom(child, IC_64BIT_OPSIZE) || 93 inheritsFrom(child, IC_64BIT_ADSIZE) || 94 inheritsFrom(child, IC_64BIT_XD) || 95 inheritsFrom(child, IC_64BIT_XS)); 96 case IC_OPSIZE: 97 return (inheritsFrom(child, IC_64BIT_OPSIZE) || 98 inheritsFrom(child, IC_OPSIZE_ADSIZE)); 99 case IC_ADSIZE: 100 return inheritsFrom(child, IC_OPSIZE_ADSIZE); 101 case IC_OPSIZE_ADSIZE: 102 case IC_64BIT_ADSIZE: 103 return false; 104 case IC_XD: 105 return inheritsFrom(child, IC_64BIT_XD); 106 case IC_XS: 107 return inheritsFrom(child, IC_64BIT_XS); 108 case IC_XD_OPSIZE: 109 return inheritsFrom(child, IC_64BIT_XD_OPSIZE); 110 case IC_XS_OPSIZE: 111 return inheritsFrom(child, IC_64BIT_XS_OPSIZE); 112 case IC_64BIT_REXW: 113 return(inheritsFrom(child, IC_64BIT_REXW_XS) || 114 inheritsFrom(child, IC_64BIT_REXW_XD) || 115 inheritsFrom(child, IC_64BIT_REXW_OPSIZE)); 116 case IC_64BIT_OPSIZE: 117 return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE)); 118 case IC_64BIT_XD: 119 return(inheritsFrom(child, IC_64BIT_REXW_XD)); 120 case IC_64BIT_XS: 121 return(inheritsFrom(child, IC_64BIT_REXW_XS)); 122 case IC_64BIT_XD_OPSIZE: 123 case IC_64BIT_XS_OPSIZE: 124 return false; 125 case IC_64BIT_REXW_XD: 126 case IC_64BIT_REXW_XS: 127 case IC_64BIT_REXW_OPSIZE: 128 return false; 129 case IC_VEX: 130 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W)) || 131 inheritsFrom(child, IC_VEX_W) || 132 (VEX_LIG && inheritsFrom(child, IC_VEX_L)); 133 case IC_VEX_XS: 134 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS)) || 135 inheritsFrom(child, IC_VEX_W_XS) || 136 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS)); 137 case IC_VEX_XD: 138 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD)) || 139 inheritsFrom(child, IC_VEX_W_XD) || 140 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD)); 141 case IC_VEX_OPSIZE: 142 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE)) || 143 inheritsFrom(child, IC_VEX_W_OPSIZE) || 144 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE)); 145 case IC_VEX_W: 146 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W); 147 case IC_VEX_W_XS: 148 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS); 149 case IC_VEX_W_XD: 150 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD); 151 case IC_VEX_W_OPSIZE: 152 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE); 153 case IC_VEX_L: 154 return inheritsFrom(child, IC_VEX_L_W); 155 case IC_VEX_L_XS: 156 return inheritsFrom(child, IC_VEX_L_W_XS); 157 case IC_VEX_L_XD: 158 return inheritsFrom(child, IC_VEX_L_W_XD); 159 case IC_VEX_L_OPSIZE: 160 return inheritsFrom(child, IC_VEX_L_W_OPSIZE); 161 case IC_VEX_L_W: 162 case IC_VEX_L_W_XS: 163 case IC_VEX_L_W_XD: 164 case IC_VEX_L_W_OPSIZE: 165 return false; 166 case IC_EVEX: 167 return inheritsFrom(child, IC_EVEX_W) || 168 inheritsFrom(child, IC_EVEX_L_W); 169 case IC_EVEX_XS: 170 return inheritsFrom(child, IC_EVEX_W_XS) || 171 inheritsFrom(child, IC_EVEX_L_W_XS); 172 case IC_EVEX_XD: 173 return inheritsFrom(child, IC_EVEX_W_XD) || 174 inheritsFrom(child, IC_EVEX_L_W_XD); 175 case IC_EVEX_OPSIZE: 176 return inheritsFrom(child, IC_EVEX_W_OPSIZE) || 177 inheritsFrom(child, IC_EVEX_L_W_OPSIZE); 178 case IC_EVEX_W: 179 case IC_EVEX_W_XS: 180 case IC_EVEX_W_XD: 181 case IC_EVEX_W_OPSIZE: 182 return false; 183 case IC_EVEX_L: 184 case IC_EVEX_L_XS: 185 case IC_EVEX_L_XD: 186 case IC_EVEX_L_OPSIZE: 187 return false; 188 case IC_EVEX_L_W: 189 case IC_EVEX_L_W_XS: 190 case IC_EVEX_L_W_XD: 191 case IC_EVEX_L_W_OPSIZE: 192 return false; 193 case IC_EVEX_L2: 194 case IC_EVEX_L2_XS: 195 case IC_EVEX_L2_XD: 196 case IC_EVEX_L2_OPSIZE: 197 return false; 198 case IC_EVEX_L2_W: 199 case IC_EVEX_L2_W_XS: 200 case IC_EVEX_L2_W_XD: 201 case IC_EVEX_L2_W_OPSIZE: 202 return false; 203 case IC_EVEX_K: 204 return inheritsFrom(child, IC_EVEX_W_K) || 205 inheritsFrom(child, IC_EVEX_L_W_K); 206 case IC_EVEX_XS_K: 207 return inheritsFrom(child, IC_EVEX_W_XS_K) || 208 inheritsFrom(child, IC_EVEX_L_W_XS_K); 209 case IC_EVEX_XD_K: 210 return inheritsFrom(child, IC_EVEX_W_XD_K) || 211 inheritsFrom(child, IC_EVEX_L_W_XD_K); 212 case IC_EVEX_OPSIZE_K: 213 case IC_EVEX_OPSIZE_B: 214 return false; 215 case IC_EVEX_W_K: 216 case IC_EVEX_W_XS_K: 217 case IC_EVEX_W_XD_K: 218 case IC_EVEX_W_OPSIZE_K: 219 case IC_EVEX_W_OPSIZE_B: 220 return false; 221 case IC_EVEX_L_K: 222 case IC_EVEX_L_XS_K: 223 case IC_EVEX_L_XD_K: 224 case IC_EVEX_L_OPSIZE_K: 225 return false; 226 case IC_EVEX_W_KZ: 227 case IC_EVEX_W_XS_KZ: 228 case IC_EVEX_W_XD_KZ: 229 case IC_EVEX_W_OPSIZE_KZ: 230 return false; 231 case IC_EVEX_L_KZ: 232 case IC_EVEX_L_XS_KZ: 233 case IC_EVEX_L_XD_KZ: 234 case IC_EVEX_L_OPSIZE_KZ: 235 return false; 236 case IC_EVEX_L_W_K: 237 case IC_EVEX_L_W_XS_K: 238 case IC_EVEX_L_W_XD_K: 239 case IC_EVEX_L_W_OPSIZE_K: 240 case IC_EVEX_L_W_KZ: 241 case IC_EVEX_L_W_XS_KZ: 242 case IC_EVEX_L_W_XD_KZ: 243 case IC_EVEX_L_W_OPSIZE_KZ: 244 return false; 245 case IC_EVEX_L2_K: 246 case IC_EVEX_L2_B: 247 case IC_EVEX_L2_XS_K: 248 case IC_EVEX_L2_XS_B: 249 case IC_EVEX_L2_XD_B: 250 case IC_EVEX_L2_XD_K: 251 case IC_EVEX_L2_OPSIZE_K: 252 case IC_EVEX_L2_OPSIZE_B: 253 case IC_EVEX_L2_OPSIZE_K_B: 254 case IC_EVEX_L2_KZ: 255 case IC_EVEX_L2_XS_KZ: 256 case IC_EVEX_L2_XD_KZ: 257 case IC_EVEX_L2_OPSIZE_KZ: 258 case IC_EVEX_L2_OPSIZE_KZ_B: 259 return false; 260 case IC_EVEX_L2_W_K: 261 case IC_EVEX_L2_W_B: 262 case IC_EVEX_L2_W_XS_K: 263 case IC_EVEX_L2_W_XD_K: 264 case IC_EVEX_L2_W_XD_B: 265 case IC_EVEX_L2_W_OPSIZE_K: 266 case IC_EVEX_L2_W_OPSIZE_B: 267 case IC_EVEX_L2_W_OPSIZE_K_B: 268 case IC_EVEX_L2_W_KZ: 269 case IC_EVEX_L2_W_XS_KZ: 270 case IC_EVEX_L2_W_XD_KZ: 271 case IC_EVEX_L2_W_OPSIZE_KZ: 272 case IC_EVEX_L2_W_OPSIZE_KZ_B: 273 return false; 274 default: 275 errs() << "Unknown instruction class: " << 276 stringForContext((InstructionContext)parent) << "\n"; 277 llvm_unreachable("Unknown instruction class"); 278 } 279 } 280 281 /// outranks - Indicates whether, if an instruction has two different applicable 282 /// classes, which class should be preferred when performing decode. This 283 /// imposes a total ordering (ties are resolved toward "lower") 284 /// 285 /// @param upper - The class that may be preferable 286 /// @param lower - The class that may be less preferable 287 /// @return - True if upper is to be preferred, false otherwise. 288 static inline bool outranks(InstructionContext upper, 289 InstructionContext lower) { 290 assert(upper < IC_max); 291 assert(lower < IC_max); 292 293 #define ENUM_ENTRY(n, r, d) r, 294 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) \ 295 ENUM_ENTRY(n##_K_B, r, d) ENUM_ENTRY(n##_KZ_B, r, d) \ 296 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d) 297 static int ranks[IC_max] = { 298 INSTRUCTION_CONTEXTS 299 }; 300 #undef ENUM_ENTRY 301 #undef ENUM_ENTRY_K_B 302 303 return (ranks[upper] > ranks[lower]); 304 } 305 306 /// getDecisionType - Determines whether a ModRM decision with 255 entries can 307 /// be compacted by eliminating redundant information. 308 /// 309 /// @param decision - The decision to be compacted. 310 /// @return - The compactest available representation for the decision. 311 static ModRMDecisionType getDecisionType(ModRMDecision &decision) { 312 bool satisfiesOneEntry = true; 313 bool satisfiesSplitRM = true; 314 bool satisfiesSplitReg = true; 315 bool satisfiesSplitMisc = true; 316 317 for (unsigned index = 0; index < 256; ++index) { 318 if (decision.instructionIDs[index] != decision.instructionIDs[0]) 319 satisfiesOneEntry = false; 320 321 if (((index & 0xc0) == 0xc0) && 322 (decision.instructionIDs[index] != decision.instructionIDs[0xc0])) 323 satisfiesSplitRM = false; 324 325 if (((index & 0xc0) != 0xc0) && 326 (decision.instructionIDs[index] != decision.instructionIDs[0x00])) 327 satisfiesSplitRM = false; 328 329 if (((index & 0xc0) == 0xc0) && 330 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8])) 331 satisfiesSplitReg = false; 332 333 if (((index & 0xc0) != 0xc0) && 334 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38])) 335 satisfiesSplitMisc = false; 336 } 337 338 if (satisfiesOneEntry) 339 return MODRM_ONEENTRY; 340 341 if (satisfiesSplitRM) 342 return MODRM_SPLITRM; 343 344 if (satisfiesSplitReg && satisfiesSplitMisc) 345 return MODRM_SPLITREG; 346 347 if (satisfiesSplitMisc) 348 return MODRM_SPLITMISC; 349 350 return MODRM_FULL; 351 } 352 353 /// stringForDecisionType - Returns a statically-allocated string corresponding 354 /// to a particular decision type. 355 /// 356 /// @param dt - The decision type. 357 /// @return - A pointer to the statically-allocated string (e.g., 358 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY). 359 static const char* stringForDecisionType(ModRMDecisionType dt) { 360 #define ENUM_ENTRY(n) case n: return #n; 361 switch (dt) { 362 default: 363 llvm_unreachable("Unknown decision type"); 364 MODRMTYPES 365 }; 366 #undef ENUM_ENTRY 367 } 368 369 DisassemblerTables::DisassemblerTables() { 370 unsigned i; 371 372 for (i = 0; i < array_lengthof(Tables); i++) { 373 Tables[i] = new ContextDecision; 374 memset(Tables[i], 0, sizeof(ContextDecision)); 375 } 376 377 HasConflicts = false; 378 } 379 380 DisassemblerTables::~DisassemblerTables() { 381 unsigned i; 382 383 for (i = 0; i < array_lengthof(Tables); i++) 384 delete Tables[i]; 385 } 386 387 void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2, 388 unsigned &i1, unsigned &i2, 389 unsigned &ModRMTableNum, 390 ModRMDecision &decision) const { 391 static uint32_t sTableNumber = 0; 392 static uint32_t sEntryNumber = 1; 393 ModRMDecisionType dt = getDecisionType(decision); 394 395 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0) 396 { 397 o2.indent(i2) << "{ /* ModRMDecision */" << "\n"; 398 i2++; 399 400 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n"; 401 o2.indent(i2) << 0 << " /* EmptyTable */\n"; 402 403 i2--; 404 o2.indent(i2) << "}"; 405 return; 406 } 407 408 std::vector<unsigned> ModRMDecision; 409 410 switch (dt) { 411 default: 412 llvm_unreachable("Unknown decision type"); 413 case MODRM_ONEENTRY: 414 ModRMDecision.push_back(decision.instructionIDs[0]); 415 break; 416 case MODRM_SPLITRM: 417 ModRMDecision.push_back(decision.instructionIDs[0x00]); 418 ModRMDecision.push_back(decision.instructionIDs[0xc0]); 419 break; 420 case MODRM_SPLITREG: 421 for (unsigned index = 0; index < 64; index += 8) 422 ModRMDecision.push_back(decision.instructionIDs[index]); 423 for (unsigned index = 0xc0; index < 256; index += 8) 424 ModRMDecision.push_back(decision.instructionIDs[index]); 425 break; 426 case MODRM_SPLITMISC: 427 for (unsigned index = 0; index < 64; index += 8) 428 ModRMDecision.push_back(decision.instructionIDs[index]); 429 for (unsigned index = 0xc0; index < 256; ++index) 430 ModRMDecision.push_back(decision.instructionIDs[index]); 431 break; 432 case MODRM_FULL: 433 for (unsigned index = 0; index < 256; ++index) 434 ModRMDecision.push_back(decision.instructionIDs[index]); 435 break; 436 } 437 438 unsigned &EntryNumber = ModRMTable[ModRMDecision]; 439 if (EntryNumber == 0) { 440 EntryNumber = ModRMTableNum; 441 442 ModRMTableNum += ModRMDecision.size(); 443 o1 << "/* Table" << EntryNumber << " */\n"; 444 i1++; 445 for (std::vector<unsigned>::const_iterator I = ModRMDecision.begin(), 446 E = ModRMDecision.end(); I != E; ++I) { 447 o1.indent(i1 * 2) << format("0x%hx", *I) << ", /* " 448 << InstructionSpecifiers[*I].name << " */\n"; 449 } 450 i1--; 451 } 452 453 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n"; 454 i2++; 455 456 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n"; 457 o2.indent(i2) << EntryNumber << " /* Table" << EntryNumber << " */\n"; 458 459 i2--; 460 o2.indent(i2) << "}"; 461 462 switch (dt) { 463 default: 464 llvm_unreachable("Unknown decision type"); 465 case MODRM_ONEENTRY: 466 sEntryNumber += 1; 467 break; 468 case MODRM_SPLITRM: 469 sEntryNumber += 2; 470 break; 471 case MODRM_SPLITREG: 472 sEntryNumber += 16; 473 break; 474 case MODRM_SPLITMISC: 475 sEntryNumber += 8 + 64; 476 break; 477 case MODRM_FULL: 478 sEntryNumber += 256; 479 break; 480 } 481 482 // We assume that the index can fit into uint16_t. 483 assert(sEntryNumber < 65536U && 484 "Index into ModRMDecision is too large for uint16_t!"); 485 486 ++sTableNumber; 487 } 488 489 void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2, 490 unsigned &i1, unsigned &i2, 491 unsigned &ModRMTableNum, 492 OpcodeDecision &decision) const { 493 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n"; 494 i2++; 495 o2.indent(i2) << "{" << "\n"; 496 i2++; 497 498 for (unsigned index = 0; index < 256; ++index) { 499 o2.indent(i2); 500 501 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n"; 502 503 emitModRMDecision(o1, o2, i1, i2, ModRMTableNum, 504 decision.modRMDecisions[index]); 505 506 if (index < 255) 507 o2 << ","; 508 509 o2 << "\n"; 510 } 511 512 i2--; 513 o2.indent(i2) << "}" << "\n"; 514 i2--; 515 o2.indent(i2) << "}" << "\n"; 516 } 517 518 void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2, 519 unsigned &i1, unsigned &i2, 520 unsigned &ModRMTableNum, 521 ContextDecision &decision, 522 const char* name) const { 523 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n"; 524 i2++; 525 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n"; 526 i2++; 527 528 for (unsigned index = 0; index < IC_max; ++index) { 529 o2.indent(i2) << "/* "; 530 o2 << stringForContext((InstructionContext)index); 531 o2 << " */"; 532 o2 << "\n"; 533 534 emitOpcodeDecision(o1, o2, i1, i2, ModRMTableNum, 535 decision.opcodeDecisions[index]); 536 537 if (index + 1 < IC_max) 538 o2 << ", "; 539 } 540 541 i2--; 542 o2.indent(i2) << "}" << "\n"; 543 i2--; 544 o2.indent(i2) << "};" << "\n"; 545 } 546 547 void DisassemblerTables::emitInstructionInfo(raw_ostream &o, 548 unsigned &i) const { 549 unsigned NumInstructions = InstructionSpecifiers.size(); 550 551 o << "static const struct OperandSpecifier x86OperandSets[][" 552 << X86_MAX_OPERANDS << "] = {\n"; 553 554 typedef std::vector<std::pair<const char *, const char *> > OperandListTy; 555 std::map<OperandListTy, unsigned> OperandSets; 556 557 unsigned OperandSetNum = 0; 558 for (unsigned Index = 0; Index < NumInstructions; ++Index) { 559 OperandListTy OperandList; 560 561 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS; 562 ++OperandIndex) { 563 const char *Encoding = 564 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[Index] 565 .operands[OperandIndex].encoding); 566 const char *Type = 567 stringForOperandType((OperandType)InstructionSpecifiers[Index] 568 .operands[OperandIndex].type); 569 OperandList.push_back(std::make_pair(Encoding, Type)); 570 } 571 unsigned &N = OperandSets[OperandList]; 572 if (N != 0) continue; 573 574 N = ++OperandSetNum; 575 576 o << " { /* " << (OperandSetNum - 1) << " */\n"; 577 for (unsigned i = 0, e = OperandList.size(); i != e; ++i) { 578 o << " { " << OperandList[i].first << ", " 579 << OperandList[i].second << " },\n"; 580 } 581 o << " },\n"; 582 } 583 o << "};" << "\n\n"; 584 585 o.indent(i * 2) << "static const struct InstructionSpecifier "; 586 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n"; 587 588 i++; 589 590 for (unsigned index = 0; index < NumInstructions; ++index) { 591 o.indent(i * 2) << "{ /* " << index << " */" << "\n"; 592 i++; 593 594 OperandListTy OperandList; 595 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS; 596 ++OperandIndex) { 597 const char *Encoding = 598 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[index] 599 .operands[OperandIndex].encoding); 600 const char *Type = 601 stringForOperandType((OperandType)InstructionSpecifiers[index] 602 .operands[OperandIndex].type); 603 OperandList.push_back(std::make_pair(Encoding, Type)); 604 } 605 o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n"; 606 607 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */"; 608 o << "\n"; 609 610 i--; 611 o.indent(i * 2) << "}"; 612 613 if (index + 1 < NumInstructions) 614 o << ","; 615 616 o << "\n"; 617 } 618 619 i--; 620 o.indent(i * 2) << "};" << "\n"; 621 } 622 623 void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const { 624 const unsigned int tableSize = 16384; 625 o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR 626 "[" << tableSize << "] = {\n"; 627 i++; 628 629 for (unsigned index = 0; index < tableSize; ++index) { 630 o.indent(i * 2); 631 632 if (index & ATTR_EVEX) { 633 o << "IC_EVEX"; 634 if (index & ATTR_EVEXL2) 635 o << "_L2"; 636 else if (index & ATTR_EVEXL) 637 o << "_L"; 638 if (index & ATTR_REXW) 639 o << "_W"; 640 if (index & ATTR_OPSIZE) 641 o << "_OPSIZE"; 642 else if (index & ATTR_XD) 643 o << "_XD"; 644 else if (index & ATTR_XS) 645 o << "_XS"; 646 if (index & ATTR_EVEXKZ) 647 o << "_KZ"; 648 else if (index & ATTR_EVEXK) 649 o << "_K"; 650 if (index & ATTR_EVEXB) 651 o << "_B"; 652 } 653 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE)) 654 o << "IC_VEX_L_W_OPSIZE"; 655 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XD)) 656 o << "IC_VEX_L_W_XD"; 657 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XS)) 658 o << "IC_VEX_L_W_XS"; 659 else if ((index & ATTR_VEXL) && (index & ATTR_REXW)) 660 o << "IC_VEX_L_W"; 661 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE)) 662 o << "IC_VEX_L_OPSIZE"; 663 else if ((index & ATTR_VEXL) && (index & ATTR_XD)) 664 o << "IC_VEX_L_XD"; 665 else if ((index & ATTR_VEXL) && (index & ATTR_XS)) 666 o << "IC_VEX_L_XS"; 667 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE)) 668 o << "IC_VEX_W_OPSIZE"; 669 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD)) 670 o << "IC_VEX_W_XD"; 671 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS)) 672 o << "IC_VEX_W_XS"; 673 else if (index & ATTR_VEXL) 674 o << "IC_VEX_L"; 675 else if ((index & ATTR_VEX) && (index & ATTR_REXW)) 676 o << "IC_VEX_W"; 677 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE)) 678 o << "IC_VEX_OPSIZE"; 679 else if ((index & ATTR_VEX) && (index & ATTR_XD)) 680 o << "IC_VEX_XD"; 681 else if ((index & ATTR_VEX) && (index & ATTR_XS)) 682 o << "IC_VEX_XS"; 683 else if (index & ATTR_VEX) 684 o << "IC_VEX"; 685 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS)) 686 o << "IC_64BIT_REXW_XS"; 687 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD)) 688 o << "IC_64BIT_REXW_XD"; 689 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && 690 (index & ATTR_OPSIZE)) 691 o << "IC_64BIT_REXW_OPSIZE"; 692 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE)) 693 o << "IC_64BIT_XD_OPSIZE"; 694 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE)) 695 o << "IC_64BIT_XS_OPSIZE"; 696 else if ((index & ATTR_64BIT) && (index & ATTR_XS)) 697 o << "IC_64BIT_XS"; 698 else if ((index & ATTR_64BIT) && (index & ATTR_XD)) 699 o << "IC_64BIT_XD"; 700 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE)) 701 o << "IC_64BIT_OPSIZE"; 702 else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE)) 703 o << "IC_64BIT_ADSIZE"; 704 else if ((index & ATTR_64BIT) && (index & ATTR_REXW)) 705 o << "IC_64BIT_REXW"; 706 else if ((index & ATTR_64BIT)) 707 o << "IC_64BIT"; 708 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE)) 709 o << "IC_XS_OPSIZE"; 710 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE)) 711 o << "IC_XD_OPSIZE"; 712 else if (index & ATTR_XS) 713 o << "IC_XS"; 714 else if (index & ATTR_XD) 715 o << "IC_XD"; 716 else if (index & ATTR_OPSIZE) 717 o << "IC_OPSIZE"; 718 else if (index & ATTR_ADSIZE) 719 o << "IC_ADSIZE"; 720 else 721 o << "IC"; 722 723 if (index < tableSize - 1) 724 o << ","; 725 else 726 o << " "; 727 728 o << " /* " << index << " */"; 729 730 o << "\n"; 731 } 732 733 i--; 734 o.indent(i * 2) << "};" << "\n"; 735 } 736 737 void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2, 738 unsigned &i1, unsigned &i2, 739 unsigned &ModRMTableNum) const { 740 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[0], ONEBYTE_STR); 741 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[1], TWOBYTE_STR); 742 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[2], THREEBYTE38_STR); 743 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[3], THREEBYTE3A_STR); 744 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[4], THREEBYTEA6_STR); 745 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[5], THREEBYTEA7_STR); 746 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[6], XOP8_MAP_STR); 747 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[7], XOP9_MAP_STR); 748 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[8], XOPA_MAP_STR); 749 } 750 751 void DisassemblerTables::emit(raw_ostream &o) const { 752 unsigned i1 = 0; 753 unsigned i2 = 0; 754 755 std::string s1; 756 std::string s2; 757 758 raw_string_ostream o1(s1); 759 raw_string_ostream o2(s2); 760 761 emitInstructionInfo(o, i2); 762 o << "\n"; 763 764 emitContextTable(o, i2); 765 o << "\n"; 766 767 unsigned ModRMTableNum = 0; 768 769 o << "static const InstrUID modRMTable[] = {\n"; 770 i1++; 771 std::vector<unsigned> EmptyTable(1, 0); 772 ModRMTable[EmptyTable] = ModRMTableNum; 773 ModRMTableNum += EmptyTable.size(); 774 o1 << "/* EmptyTable */\n"; 775 o1.indent(i1 * 2) << "0x0,\n"; 776 i1--; 777 emitContextDecisions(o1, o2, i1, i2, ModRMTableNum); 778 779 o << o1.str(); 780 o << " 0x0\n"; 781 o << "};\n"; 782 o << "\n"; 783 o << o2.str(); 784 o << "\n"; 785 o << "\n"; 786 } 787 788 void DisassemblerTables::setTableFields(ModRMDecision &decision, 789 const ModRMFilter &filter, 790 InstrUID uid, 791 uint8_t opcode) { 792 for (unsigned index = 0; index < 256; ++index) { 793 if (filter.accepts(index)) { 794 if (decision.instructionIDs[index] == uid) 795 continue; 796 797 if (decision.instructionIDs[index] != 0) { 798 InstructionSpecifier &newInfo = 799 InstructionSpecifiers[uid]; 800 InstructionSpecifier &previousInfo = 801 InstructionSpecifiers[decision.instructionIDs[index]]; 802 803 if(newInfo.filtered) 804 continue; // filtered instructions get lowest priority 805 806 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" || 807 newInfo.name == "XCHG32ar" || 808 newInfo.name == "XCHG32ar64" || 809 newInfo.name == "XCHG64ar")) 810 continue; // special case for XCHG*ar and NOOP 811 812 if (outranks(previousInfo.insnContext, newInfo.insnContext)) 813 continue; 814 815 if (previousInfo.insnContext == newInfo.insnContext && 816 !previousInfo.filtered) { 817 errs() << "Error: Primary decode conflict: "; 818 errs() << newInfo.name << " would overwrite " << previousInfo.name; 819 errs() << "\n"; 820 errs() << "ModRM " << index << "\n"; 821 errs() << "Opcode " << (uint16_t)opcode << "\n"; 822 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n"; 823 HasConflicts = true; 824 } 825 } 826 827 decision.instructionIDs[index] = uid; 828 } 829 } 830 } 831 832 void DisassemblerTables::setTableFields(OpcodeType type, 833 InstructionContext insnContext, 834 uint8_t opcode, 835 const ModRMFilter &filter, 836 InstrUID uid, 837 bool is32bit, 838 bool ignoresVEX_L) { 839 ContextDecision &decision = *Tables[type]; 840 841 for (unsigned index = 0; index < IC_max; ++index) { 842 if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT)) 843 continue; 844 845 if (inheritsFrom((InstructionContext)index, 846 InstructionSpecifiers[uid].insnContext, ignoresVEX_L)) 847 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode], 848 filter, 849 uid, 850 opcode); 851 } 852 } 853