1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler Emitter. 11 // It contains the implementation of the disassembler tables. 12 // Documentation for the disassembler emitter in general can be found in 13 // X86DisassemblerEmitter.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "X86DisassemblerTables.h" 18 #include "X86DisassemblerShared.h" 19 #include "llvm/ADT/STLExtras.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include "llvm/Support/Format.h" 22 #include <map> 23 24 using namespace llvm; 25 using namespace X86Disassembler; 26 27 /// stringForContext - Returns a string containing the name of a particular 28 /// InstructionContext, usually for diagnostic purposes. 29 /// 30 /// @param insnContext - The instruction class to transform to a string. 31 /// @return - A statically-allocated string constant that contains the 32 /// name of the instruction class. 33 static inline const char* stringForContext(InstructionContext insnContext) { 34 switch (insnContext) { 35 default: 36 llvm_unreachable("Unhandled instruction class"); 37 #define ENUM_ENTRY(n, r, d) case n: return #n; break; 38 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\ 39 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)\ 40 ENUM_ENTRY(n##_KZ_B, r, d) 41 INSTRUCTION_CONTEXTS 42 #undef ENUM_ENTRY 43 #undef ENUM_ENTRY_K_B 44 } 45 } 46 47 /// stringForOperandType - Like stringForContext, but for OperandTypes. 48 static inline const char* stringForOperandType(OperandType type) { 49 switch (type) { 50 default: 51 llvm_unreachable("Unhandled type"); 52 #define ENUM_ENTRY(i, d) case i: return #i; 53 TYPES 54 #undef ENUM_ENTRY 55 } 56 } 57 58 /// stringForOperandEncoding - like stringForContext, but for 59 /// OperandEncodings. 60 static inline const char* stringForOperandEncoding(OperandEncoding encoding) { 61 switch (encoding) { 62 default: 63 llvm_unreachable("Unhandled encoding"); 64 #define ENUM_ENTRY(i, d) case i: return #i; 65 ENCODINGS 66 #undef ENUM_ENTRY 67 } 68 } 69 70 /// inheritsFrom - Indicates whether all instructions in one class also belong 71 /// to another class. 72 /// 73 /// @param child - The class that may be the subset 74 /// @param parent - The class that may be the superset 75 /// @return - True if child is a subset of parent, false otherwise. 76 static inline bool inheritsFrom(InstructionContext child, 77 InstructionContext parent, 78 bool VEX_LIG = false, bool VEX_WIG = false, 79 bool AdSize64 = false) { 80 if (child == parent) 81 return true; 82 83 switch (parent) { 84 case IC: 85 return(inheritsFrom(child, IC_64BIT, AdSize64) || 86 inheritsFrom(child, IC_OPSIZE) || 87 inheritsFrom(child, IC_ADSIZE) || 88 inheritsFrom(child, IC_XD) || 89 inheritsFrom(child, IC_XS)); 90 case IC_64BIT: 91 return(inheritsFrom(child, IC_64BIT_REXW) || 92 inheritsFrom(child, IC_64BIT_OPSIZE) || 93 (!AdSize64 && inheritsFrom(child, IC_64BIT_ADSIZE)) || 94 inheritsFrom(child, IC_64BIT_XD) || 95 inheritsFrom(child, IC_64BIT_XS)); 96 case IC_OPSIZE: 97 return inheritsFrom(child, IC_64BIT_OPSIZE) || 98 inheritsFrom(child, IC_OPSIZE_ADSIZE); 99 case IC_ADSIZE: 100 return inheritsFrom(child, IC_OPSIZE_ADSIZE); 101 case IC_OPSIZE_ADSIZE: 102 return false; 103 case IC_64BIT_ADSIZE: 104 return inheritsFrom(child, IC_64BIT_OPSIZE_ADSIZE); 105 case IC_64BIT_OPSIZE_ADSIZE: 106 return false; 107 case IC_XD: 108 return inheritsFrom(child, IC_64BIT_XD); 109 case IC_XS: 110 return inheritsFrom(child, IC_64BIT_XS); 111 case IC_XD_OPSIZE: 112 return inheritsFrom(child, IC_64BIT_XD_OPSIZE); 113 case IC_XS_OPSIZE: 114 return inheritsFrom(child, IC_64BIT_XS_OPSIZE); 115 case IC_64BIT_REXW: 116 return(inheritsFrom(child, IC_64BIT_REXW_XS) || 117 inheritsFrom(child, IC_64BIT_REXW_XD) || 118 inheritsFrom(child, IC_64BIT_REXW_OPSIZE) || 119 (!AdSize64 && inheritsFrom(child, IC_64BIT_REXW_ADSIZE))); 120 case IC_64BIT_OPSIZE: 121 return inheritsFrom(child, IC_64BIT_REXW_OPSIZE) || 122 (!AdSize64 && inheritsFrom(child, IC_64BIT_OPSIZE_ADSIZE)) || 123 (!AdSize64 && inheritsFrom(child, IC_64BIT_REXW_ADSIZE)); 124 case IC_64BIT_XD: 125 return(inheritsFrom(child, IC_64BIT_REXW_XD)); 126 case IC_64BIT_XS: 127 return(inheritsFrom(child, IC_64BIT_REXW_XS)); 128 case IC_64BIT_XD_OPSIZE: 129 case IC_64BIT_XS_OPSIZE: 130 return false; 131 case IC_64BIT_REXW_XD: 132 case IC_64BIT_REXW_XS: 133 case IC_64BIT_REXW_OPSIZE: 134 case IC_64BIT_REXW_ADSIZE: 135 return false; 136 case IC_VEX: 137 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_VEX_L_W)) || 138 (VEX_WIG && inheritsFrom(child, IC_VEX_W)) || 139 (VEX_LIG && inheritsFrom(child, IC_VEX_L)); 140 case IC_VEX_XS: 141 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_VEX_L_W_XS)) || 142 (VEX_WIG && inheritsFrom(child, IC_VEX_W_XS)) || 143 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS)); 144 case IC_VEX_XD: 145 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_VEX_L_W_XD)) || 146 (VEX_WIG && inheritsFrom(child, IC_VEX_W_XD)) || 147 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD)); 148 case IC_VEX_OPSIZE: 149 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE)) || 150 (VEX_WIG && inheritsFrom(child, IC_VEX_W_OPSIZE)) || 151 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE)); 152 case IC_VEX_W: 153 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W); 154 case IC_VEX_W_XS: 155 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS); 156 case IC_VEX_W_XD: 157 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD); 158 case IC_VEX_W_OPSIZE: 159 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE); 160 case IC_VEX_L: 161 return VEX_WIG && inheritsFrom(child, IC_VEX_L_W); 162 case IC_VEX_L_XS: 163 return VEX_WIG && inheritsFrom(child, IC_VEX_L_W_XS); 164 case IC_VEX_L_XD: 165 return VEX_WIG && inheritsFrom(child, IC_VEX_L_W_XD); 166 case IC_VEX_L_OPSIZE: 167 return VEX_WIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE); 168 case IC_VEX_L_W: 169 case IC_VEX_L_W_XS: 170 case IC_VEX_L_W_XD: 171 case IC_VEX_L_W_OPSIZE: 172 return false; 173 case IC_EVEX: 174 return inheritsFrom(child, IC_EVEX_W) || 175 inheritsFrom(child, IC_EVEX_L_W); 176 case IC_EVEX_XS: 177 return inheritsFrom(child, IC_EVEX_W_XS) || 178 inheritsFrom(child, IC_EVEX_L_W_XS); 179 case IC_EVEX_XD: 180 return inheritsFrom(child, IC_EVEX_W_XD) || 181 inheritsFrom(child, IC_EVEX_L_W_XD); 182 case IC_EVEX_OPSIZE: 183 return inheritsFrom(child, IC_EVEX_W_OPSIZE) || 184 inheritsFrom(child, IC_EVEX_L_W_OPSIZE); 185 case IC_EVEX_B: 186 return false; 187 case IC_EVEX_W: 188 case IC_EVEX_W_XS: 189 case IC_EVEX_W_XD: 190 case IC_EVEX_W_OPSIZE: 191 return false; 192 case IC_EVEX_L: 193 case IC_EVEX_L_K_B: 194 case IC_EVEX_L_KZ_B: 195 case IC_EVEX_L_B: 196 case IC_EVEX_L_XS: 197 case IC_EVEX_L_XD: 198 case IC_EVEX_L_OPSIZE: 199 return false; 200 case IC_EVEX_L_W: 201 case IC_EVEX_L_W_XS: 202 case IC_EVEX_L_W_XD: 203 case IC_EVEX_L_W_OPSIZE: 204 return false; 205 case IC_EVEX_L2: 206 case IC_EVEX_L2_XS: 207 case IC_EVEX_L2_XD: 208 case IC_EVEX_L2_OPSIZE: 209 return false; 210 case IC_EVEX_L2_W: 211 case IC_EVEX_L2_W_XS: 212 case IC_EVEX_L2_W_XD: 213 case IC_EVEX_L2_W_OPSIZE: 214 return false; 215 case IC_EVEX_K: 216 return inheritsFrom(child, IC_EVEX_W_K) || 217 inheritsFrom(child, IC_EVEX_L_W_K); 218 case IC_EVEX_XS_K: 219 case IC_EVEX_XS_K_B: 220 case IC_EVEX_XS_KZ_B: 221 return inheritsFrom(child, IC_EVEX_W_XS_K) || 222 inheritsFrom(child, IC_EVEX_L_W_XS_K); 223 case IC_EVEX_XD_K: 224 case IC_EVEX_XD_K_B: 225 case IC_EVEX_XD_KZ_B: 226 return inheritsFrom(child, IC_EVEX_W_XD_K) || 227 inheritsFrom(child, IC_EVEX_L_W_XD_K); 228 case IC_EVEX_XS_B: 229 case IC_EVEX_XD_B: 230 case IC_EVEX_K_B: 231 case IC_EVEX_KZ: 232 return false; 233 case IC_EVEX_XS_KZ: 234 return inheritsFrom(child, IC_EVEX_W_XS_KZ) || 235 inheritsFrom(child, IC_EVEX_L_W_XS_KZ); 236 case IC_EVEX_XD_KZ: 237 return inheritsFrom(child, IC_EVEX_W_XD_KZ) || 238 inheritsFrom(child, IC_EVEX_L_W_XD_KZ); 239 case IC_EVEX_KZ_B: 240 case IC_EVEX_OPSIZE_K: 241 case IC_EVEX_OPSIZE_B: 242 case IC_EVEX_OPSIZE_K_B: 243 case IC_EVEX_OPSIZE_KZ: 244 case IC_EVEX_OPSIZE_KZ_B: 245 return false; 246 case IC_EVEX_W_K: 247 case IC_EVEX_W_B: 248 case IC_EVEX_W_K_B: 249 case IC_EVEX_W_KZ_B: 250 case IC_EVEX_W_XS_K: 251 case IC_EVEX_W_XD_K: 252 case IC_EVEX_W_OPSIZE_K: 253 case IC_EVEX_W_OPSIZE_B: 254 case IC_EVEX_W_OPSIZE_K_B: 255 return false; 256 case IC_EVEX_L_K: 257 case IC_EVEX_L_XS_K: 258 case IC_EVEX_L_XD_K: 259 case IC_EVEX_L_XD_B: 260 case IC_EVEX_L_XD_K_B: 261 case IC_EVEX_L_OPSIZE_K: 262 case IC_EVEX_L_OPSIZE_B: 263 case IC_EVEX_L_OPSIZE_K_B: 264 return false; 265 case IC_EVEX_W_KZ: 266 case IC_EVEX_W_XS_KZ: 267 case IC_EVEX_W_XD_KZ: 268 case IC_EVEX_W_XS_B: 269 case IC_EVEX_W_XD_B: 270 case IC_EVEX_W_XS_K_B: 271 case IC_EVEX_W_XD_K_B: 272 case IC_EVEX_W_XS_KZ_B: 273 case IC_EVEX_W_XD_KZ_B: 274 case IC_EVEX_W_OPSIZE_KZ: 275 case IC_EVEX_W_OPSIZE_KZ_B: 276 return false; 277 case IC_EVEX_L_KZ: 278 case IC_EVEX_L_XS_KZ: 279 case IC_EVEX_L_XS_B: 280 case IC_EVEX_L_XS_K_B: 281 case IC_EVEX_L_XS_KZ_B: 282 case IC_EVEX_L_XD_KZ: 283 case IC_EVEX_L_XD_KZ_B: 284 case IC_EVEX_L_OPSIZE_KZ: 285 case IC_EVEX_L_OPSIZE_KZ_B: 286 return false; 287 case IC_EVEX_L_W_K: 288 case IC_EVEX_L_W_B: 289 case IC_EVEX_L_W_K_B: 290 case IC_EVEX_L_W_XS_K: 291 case IC_EVEX_L_W_XS_B: 292 case IC_EVEX_L_W_XS_K_B: 293 case IC_EVEX_L_W_XS_KZ: 294 case IC_EVEX_L_W_XS_KZ_B: 295 case IC_EVEX_L_W_OPSIZE_K: 296 case IC_EVEX_L_W_OPSIZE_B: 297 case IC_EVEX_L_W_OPSIZE_K_B: 298 case IC_EVEX_L_W_KZ: 299 case IC_EVEX_L_W_KZ_B: 300 case IC_EVEX_L_W_XD_K: 301 case IC_EVEX_L_W_XD_B: 302 case IC_EVEX_L_W_XD_K_B: 303 case IC_EVEX_L_W_XD_KZ: 304 case IC_EVEX_L_W_XD_KZ_B: 305 case IC_EVEX_L_W_OPSIZE_KZ: 306 case IC_EVEX_L_W_OPSIZE_KZ_B: 307 return false; 308 case IC_EVEX_L2_K: 309 case IC_EVEX_L2_B: 310 case IC_EVEX_L2_K_B: 311 case IC_EVEX_L2_KZ_B: 312 case IC_EVEX_L2_XS_K: 313 case IC_EVEX_L2_XS_K_B: 314 case IC_EVEX_L2_XS_B: 315 case IC_EVEX_L2_XD_B: 316 case IC_EVEX_L2_XD_K: 317 case IC_EVEX_L2_XD_K_B: 318 case IC_EVEX_L2_OPSIZE_K: 319 case IC_EVEX_L2_OPSIZE_B: 320 case IC_EVEX_L2_OPSIZE_K_B: 321 case IC_EVEX_L2_KZ: 322 case IC_EVEX_L2_XS_KZ: 323 case IC_EVEX_L2_XS_KZ_B: 324 case IC_EVEX_L2_XD_KZ: 325 case IC_EVEX_L2_XD_KZ_B: 326 case IC_EVEX_L2_OPSIZE_KZ: 327 case IC_EVEX_L2_OPSIZE_KZ_B: 328 return false; 329 case IC_EVEX_L2_W_K: 330 case IC_EVEX_L2_W_B: 331 case IC_EVEX_L2_W_K_B: 332 case IC_EVEX_L2_W_KZ_B: 333 case IC_EVEX_L2_W_XS_K: 334 case IC_EVEX_L2_W_XS_B: 335 case IC_EVEX_L2_W_XS_K_B: 336 case IC_EVEX_L2_W_XD_K: 337 case IC_EVEX_L2_W_XD_B: 338 case IC_EVEX_L2_W_OPSIZE_K: 339 case IC_EVEX_L2_W_OPSIZE_B: 340 case IC_EVEX_L2_W_OPSIZE_K_B: 341 case IC_EVEX_L2_W_KZ: 342 case IC_EVEX_L2_W_XS_KZ: 343 case IC_EVEX_L2_W_XS_KZ_B: 344 case IC_EVEX_L2_W_XD_KZ: 345 case IC_EVEX_L2_W_XD_K_B: 346 case IC_EVEX_L2_W_XD_KZ_B: 347 case IC_EVEX_L2_W_OPSIZE_KZ: 348 case IC_EVEX_L2_W_OPSIZE_KZ_B: 349 return false; 350 default: 351 errs() << "Unknown instruction class: " << 352 stringForContext((InstructionContext)parent) << "\n"; 353 llvm_unreachable("Unknown instruction class"); 354 } 355 } 356 357 /// outranks - Indicates whether, if an instruction has two different applicable 358 /// classes, which class should be preferred when performing decode. This 359 /// imposes a total ordering (ties are resolved toward "lower") 360 /// 361 /// @param upper - The class that may be preferable 362 /// @param lower - The class that may be less preferable 363 /// @return - True if upper is to be preferred, false otherwise. 364 static inline bool outranks(InstructionContext upper, 365 InstructionContext lower) { 366 assert(upper < IC_max); 367 assert(lower < IC_max); 368 369 #define ENUM_ENTRY(n, r, d) r, 370 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) \ 371 ENUM_ENTRY(n##_K_B, r, d) ENUM_ENTRY(n##_KZ_B, r, d) \ 372 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d) 373 static int ranks[IC_max] = { 374 INSTRUCTION_CONTEXTS 375 }; 376 #undef ENUM_ENTRY 377 #undef ENUM_ENTRY_K_B 378 379 return (ranks[upper] > ranks[lower]); 380 } 381 382 /// getDecisionType - Determines whether a ModRM decision with 255 entries can 383 /// be compacted by eliminating redundant information. 384 /// 385 /// @param decision - The decision to be compacted. 386 /// @return - The compactest available representation for the decision. 387 static ModRMDecisionType getDecisionType(ModRMDecision &decision) { 388 bool satisfiesOneEntry = true; 389 bool satisfiesSplitRM = true; 390 bool satisfiesSplitReg = true; 391 bool satisfiesSplitMisc = true; 392 393 for (unsigned index = 0; index < 256; ++index) { 394 if (decision.instructionIDs[index] != decision.instructionIDs[0]) 395 satisfiesOneEntry = false; 396 397 if (((index & 0xc0) == 0xc0) && 398 (decision.instructionIDs[index] != decision.instructionIDs[0xc0])) 399 satisfiesSplitRM = false; 400 401 if (((index & 0xc0) != 0xc0) && 402 (decision.instructionIDs[index] != decision.instructionIDs[0x00])) 403 satisfiesSplitRM = false; 404 405 if (((index & 0xc0) == 0xc0) && 406 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8])) 407 satisfiesSplitReg = false; 408 409 if (((index & 0xc0) != 0xc0) && 410 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38])) 411 satisfiesSplitMisc = false; 412 } 413 414 if (satisfiesOneEntry) 415 return MODRM_ONEENTRY; 416 417 if (satisfiesSplitRM) 418 return MODRM_SPLITRM; 419 420 if (satisfiesSplitReg && satisfiesSplitMisc) 421 return MODRM_SPLITREG; 422 423 if (satisfiesSplitMisc) 424 return MODRM_SPLITMISC; 425 426 return MODRM_FULL; 427 } 428 429 /// stringForDecisionType - Returns a statically-allocated string corresponding 430 /// to a particular decision type. 431 /// 432 /// @param dt - The decision type. 433 /// @return - A pointer to the statically-allocated string (e.g., 434 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY). 435 static const char* stringForDecisionType(ModRMDecisionType dt) { 436 #define ENUM_ENTRY(n) case n: return #n; 437 switch (dt) { 438 default: 439 llvm_unreachable("Unknown decision type"); 440 MODRMTYPES 441 }; 442 #undef ENUM_ENTRY 443 } 444 445 DisassemblerTables::DisassemblerTables() { 446 unsigned i; 447 448 for (i = 0; i < array_lengthof(Tables); i++) { 449 Tables[i] = new ContextDecision; 450 memset(Tables[i], 0, sizeof(ContextDecision)); 451 } 452 453 HasConflicts = false; 454 } 455 456 DisassemblerTables::~DisassemblerTables() { 457 unsigned i; 458 459 for (i = 0; i < array_lengthof(Tables); i++) 460 delete Tables[i]; 461 } 462 463 void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2, 464 unsigned &i1, unsigned &i2, 465 unsigned &ModRMTableNum, 466 ModRMDecision &decision) const { 467 static uint32_t sTableNumber = 0; 468 static uint32_t sEntryNumber = 1; 469 ModRMDecisionType dt = getDecisionType(decision); 470 471 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0) 472 { 473 o2.indent(i2) << "{ /* ModRMDecision */" << "\n"; 474 i2++; 475 476 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n"; 477 o2.indent(i2) << 0 << " /* EmptyTable */\n"; 478 479 i2--; 480 o2.indent(i2) << "}"; 481 return; 482 } 483 484 std::vector<unsigned> ModRMDecision; 485 486 switch (dt) { 487 default: 488 llvm_unreachable("Unknown decision type"); 489 case MODRM_ONEENTRY: 490 ModRMDecision.push_back(decision.instructionIDs[0]); 491 break; 492 case MODRM_SPLITRM: 493 ModRMDecision.push_back(decision.instructionIDs[0x00]); 494 ModRMDecision.push_back(decision.instructionIDs[0xc0]); 495 break; 496 case MODRM_SPLITREG: 497 for (unsigned index = 0; index < 64; index += 8) 498 ModRMDecision.push_back(decision.instructionIDs[index]); 499 for (unsigned index = 0xc0; index < 256; index += 8) 500 ModRMDecision.push_back(decision.instructionIDs[index]); 501 break; 502 case MODRM_SPLITMISC: 503 for (unsigned index = 0; index < 64; index += 8) 504 ModRMDecision.push_back(decision.instructionIDs[index]); 505 for (unsigned index = 0xc0; index < 256; ++index) 506 ModRMDecision.push_back(decision.instructionIDs[index]); 507 break; 508 case MODRM_FULL: 509 for (unsigned index = 0; index < 256; ++index) 510 ModRMDecision.push_back(decision.instructionIDs[index]); 511 break; 512 } 513 514 unsigned &EntryNumber = ModRMTable[ModRMDecision]; 515 if (EntryNumber == 0) { 516 EntryNumber = ModRMTableNum; 517 518 ModRMTableNum += ModRMDecision.size(); 519 o1 << "/* Table" << EntryNumber << " */\n"; 520 i1++; 521 for (std::vector<unsigned>::const_iterator I = ModRMDecision.begin(), 522 E = ModRMDecision.end(); I != E; ++I) { 523 o1.indent(i1 * 2) << format("0x%hx", *I) << ", /* " 524 << InstructionSpecifiers[*I].name << " */\n"; 525 } 526 i1--; 527 } 528 529 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n"; 530 i2++; 531 532 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n"; 533 o2.indent(i2) << EntryNumber << " /* Table" << EntryNumber << " */\n"; 534 535 i2--; 536 o2.indent(i2) << "}"; 537 538 switch (dt) { 539 default: 540 llvm_unreachable("Unknown decision type"); 541 case MODRM_ONEENTRY: 542 sEntryNumber += 1; 543 break; 544 case MODRM_SPLITRM: 545 sEntryNumber += 2; 546 break; 547 case MODRM_SPLITREG: 548 sEntryNumber += 16; 549 break; 550 case MODRM_SPLITMISC: 551 sEntryNumber += 8 + 64; 552 break; 553 case MODRM_FULL: 554 sEntryNumber += 256; 555 break; 556 } 557 558 // We assume that the index can fit into uint16_t. 559 assert(sEntryNumber < 65536U && 560 "Index into ModRMDecision is too large for uint16_t!"); 561 562 ++sTableNumber; 563 } 564 565 void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2, 566 unsigned &i1, unsigned &i2, 567 unsigned &ModRMTableNum, 568 OpcodeDecision &decision) const { 569 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n"; 570 i2++; 571 o2.indent(i2) << "{" << "\n"; 572 i2++; 573 574 for (unsigned index = 0; index < 256; ++index) { 575 o2.indent(i2); 576 577 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n"; 578 579 emitModRMDecision(o1, o2, i1, i2, ModRMTableNum, 580 decision.modRMDecisions[index]); 581 582 if (index < 255) 583 o2 << ","; 584 585 o2 << "\n"; 586 } 587 588 i2--; 589 o2.indent(i2) << "}" << "\n"; 590 i2--; 591 o2.indent(i2) << "}" << "\n"; 592 } 593 594 void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2, 595 unsigned &i1, unsigned &i2, 596 unsigned &ModRMTableNum, 597 ContextDecision &decision, 598 const char* name) const { 599 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n"; 600 i2++; 601 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n"; 602 i2++; 603 604 for (unsigned index = 0; index < IC_max; ++index) { 605 o2.indent(i2) << "/* "; 606 o2 << stringForContext((InstructionContext)index); 607 o2 << " */"; 608 o2 << "\n"; 609 610 emitOpcodeDecision(o1, o2, i1, i2, ModRMTableNum, 611 decision.opcodeDecisions[index]); 612 613 if (index + 1 < IC_max) 614 o2 << ", "; 615 } 616 617 i2--; 618 o2.indent(i2) << "}" << "\n"; 619 i2--; 620 o2.indent(i2) << "};" << "\n"; 621 } 622 623 void DisassemblerTables::emitInstructionInfo(raw_ostream &o, 624 unsigned &i) const { 625 unsigned NumInstructions = InstructionSpecifiers.size(); 626 627 o << "static const struct OperandSpecifier x86OperandSets[][" 628 << X86_MAX_OPERANDS << "] = {\n"; 629 630 typedef SmallVector<std::pair<OperandEncoding, OperandType>, 631 X86_MAX_OPERANDS> OperandListTy; 632 std::map<OperandListTy, unsigned> OperandSets; 633 634 unsigned OperandSetNum = 0; 635 for (unsigned Index = 0; Index < NumInstructions; ++Index) { 636 OperandListTy OperandList; 637 638 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS; 639 ++OperandIndex) { 640 OperandEncoding Encoding = (OperandEncoding)InstructionSpecifiers[Index] 641 .operands[OperandIndex].encoding; 642 OperandType Type = (OperandType)InstructionSpecifiers[Index] 643 .operands[OperandIndex].type; 644 OperandList.push_back(std::make_pair(Encoding, Type)); 645 } 646 unsigned &N = OperandSets[OperandList]; 647 if (N != 0) continue; 648 649 N = ++OperandSetNum; 650 651 o << " { /* " << (OperandSetNum - 1) << " */\n"; 652 for (unsigned i = 0, e = OperandList.size(); i != e; ++i) { 653 const char *Encoding = stringForOperandEncoding(OperandList[i].first); 654 const char *Type = stringForOperandType(OperandList[i].second); 655 o << " { " << Encoding << ", " << Type << " },\n"; 656 } 657 o << " },\n"; 658 } 659 o << "};" << "\n\n"; 660 661 o.indent(i * 2) << "static const struct InstructionSpecifier "; 662 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n"; 663 664 i++; 665 666 for (unsigned index = 0; index < NumInstructions; ++index) { 667 o.indent(i * 2) << "{ /* " << index << " */\n"; 668 i++; 669 670 OperandListTy OperandList; 671 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS; 672 ++OperandIndex) { 673 OperandEncoding Encoding = (OperandEncoding)InstructionSpecifiers[index] 674 .operands[OperandIndex].encoding; 675 OperandType Type = (OperandType)InstructionSpecifiers[index] 676 .operands[OperandIndex].type; 677 OperandList.push_back(std::make_pair(Encoding, Type)); 678 } 679 o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n"; 680 681 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */\n"; 682 683 i--; 684 o.indent(i * 2) << "},\n"; 685 } 686 687 i--; 688 o.indent(i * 2) << "};" << "\n"; 689 } 690 691 void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const { 692 const unsigned int tableSize = 16384; 693 o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR 694 "[" << tableSize << "] = {\n"; 695 i++; 696 697 for (unsigned index = 0; index < tableSize; ++index) { 698 o.indent(i * 2); 699 700 if (index & ATTR_EVEX) { 701 o << "IC_EVEX"; 702 if (index & ATTR_EVEXL2) 703 o << "_L2"; 704 else if (index & ATTR_EVEXL) 705 o << "_L"; 706 if (index & ATTR_REXW) 707 o << "_W"; 708 if (index & ATTR_OPSIZE) 709 o << "_OPSIZE"; 710 else if (index & ATTR_XD) 711 o << "_XD"; 712 else if (index & ATTR_XS) 713 o << "_XS"; 714 if (index & ATTR_EVEXKZ) 715 o << "_KZ"; 716 else if (index & ATTR_EVEXK) 717 o << "_K"; 718 if (index & ATTR_EVEXB) 719 o << "_B"; 720 } 721 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE)) 722 o << "IC_VEX_L_W_OPSIZE"; 723 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XD)) 724 o << "IC_VEX_L_W_XD"; 725 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XS)) 726 o << "IC_VEX_L_W_XS"; 727 else if ((index & ATTR_VEXL) && (index & ATTR_REXW)) 728 o << "IC_VEX_L_W"; 729 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE)) 730 o << "IC_VEX_L_OPSIZE"; 731 else if ((index & ATTR_VEXL) && (index & ATTR_XD)) 732 o << "IC_VEX_L_XD"; 733 else if ((index & ATTR_VEXL) && (index & ATTR_XS)) 734 o << "IC_VEX_L_XS"; 735 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE)) 736 o << "IC_VEX_W_OPSIZE"; 737 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD)) 738 o << "IC_VEX_W_XD"; 739 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS)) 740 o << "IC_VEX_W_XS"; 741 else if (index & ATTR_VEXL) 742 o << "IC_VEX_L"; 743 else if ((index & ATTR_VEX) && (index & ATTR_REXW)) 744 o << "IC_VEX_W"; 745 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE)) 746 o << "IC_VEX_OPSIZE"; 747 else if ((index & ATTR_VEX) && (index & ATTR_XD)) 748 o << "IC_VEX_XD"; 749 else if ((index & ATTR_VEX) && (index & ATTR_XS)) 750 o << "IC_VEX_XS"; 751 else if (index & ATTR_VEX) 752 o << "IC_VEX"; 753 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS)) 754 o << "IC_64BIT_REXW_XS"; 755 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD)) 756 o << "IC_64BIT_REXW_XD"; 757 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && 758 (index & ATTR_OPSIZE)) 759 o << "IC_64BIT_REXW_OPSIZE"; 760 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && 761 (index & ATTR_ADSIZE)) 762 o << "IC_64BIT_REXW_ADSIZE"; 763 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE)) 764 o << "IC_64BIT_XD_OPSIZE"; 765 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE)) 766 o << "IC_64BIT_XS_OPSIZE"; 767 else if ((index & ATTR_64BIT) && (index & ATTR_XS)) 768 o << "IC_64BIT_XS"; 769 else if ((index & ATTR_64BIT) && (index & ATTR_XD)) 770 o << "IC_64BIT_XD"; 771 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE) && 772 (index & ATTR_ADSIZE)) 773 o << "IC_64BIT_OPSIZE_ADSIZE"; 774 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE)) 775 o << "IC_64BIT_OPSIZE"; 776 else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE)) 777 o << "IC_64BIT_ADSIZE"; 778 else if ((index & ATTR_64BIT) && (index & ATTR_REXW)) 779 o << "IC_64BIT_REXW"; 780 else if ((index & ATTR_64BIT)) 781 o << "IC_64BIT"; 782 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE)) 783 o << "IC_XS_OPSIZE"; 784 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE)) 785 o << "IC_XD_OPSIZE"; 786 else if (index & ATTR_XS) 787 o << "IC_XS"; 788 else if (index & ATTR_XD) 789 o << "IC_XD"; 790 else if ((index & ATTR_OPSIZE) && (index & ATTR_ADSIZE)) 791 o << "IC_OPSIZE_ADSIZE"; 792 else if (index & ATTR_OPSIZE) 793 o << "IC_OPSIZE"; 794 else if (index & ATTR_ADSIZE) 795 o << "IC_ADSIZE"; 796 else 797 o << "IC"; 798 799 if (index < tableSize - 1) 800 o << ","; 801 else 802 o << " "; 803 804 o << " /* " << index << " */"; 805 806 o << "\n"; 807 } 808 809 i--; 810 o.indent(i * 2) << "};" << "\n"; 811 } 812 813 void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2, 814 unsigned &i1, unsigned &i2, 815 unsigned &ModRMTableNum) const { 816 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[0], ONEBYTE_STR); 817 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[1], TWOBYTE_STR); 818 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[2], THREEBYTE38_STR); 819 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[3], THREEBYTE3A_STR); 820 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[4], XOP8_MAP_STR); 821 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[5], XOP9_MAP_STR); 822 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[6], XOPA_MAP_STR); 823 } 824 825 void DisassemblerTables::emit(raw_ostream &o) const { 826 unsigned i1 = 0; 827 unsigned i2 = 0; 828 829 std::string s1; 830 std::string s2; 831 832 raw_string_ostream o1(s1); 833 raw_string_ostream o2(s2); 834 835 emitInstructionInfo(o, i2); 836 o << "\n"; 837 838 emitContextTable(o, i2); 839 o << "\n"; 840 841 unsigned ModRMTableNum = 0; 842 843 o << "static const InstrUID modRMTable[] = {\n"; 844 i1++; 845 std::vector<unsigned> EmptyTable(1, 0); 846 ModRMTable[EmptyTable] = ModRMTableNum; 847 ModRMTableNum += EmptyTable.size(); 848 o1 << "/* EmptyTable */\n"; 849 o1.indent(i1 * 2) << "0x0,\n"; 850 i1--; 851 emitContextDecisions(o1, o2, i1, i2, ModRMTableNum); 852 853 o << o1.str(); 854 o << " 0x0\n"; 855 o << "};\n"; 856 o << "\n"; 857 o << o2.str(); 858 o << "\n"; 859 o << "\n"; 860 } 861 862 void DisassemblerTables::setTableFields(ModRMDecision &decision, 863 const ModRMFilter &filter, 864 InstrUID uid, 865 uint8_t opcode) { 866 for (unsigned index = 0; index < 256; ++index) { 867 if (filter.accepts(index)) { 868 if (decision.instructionIDs[index] == uid) 869 continue; 870 871 if (decision.instructionIDs[index] != 0) { 872 InstructionSpecifier &newInfo = 873 InstructionSpecifiers[uid]; 874 InstructionSpecifier &previousInfo = 875 InstructionSpecifiers[decision.instructionIDs[index]]; 876 877 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" || 878 newInfo.name == "XCHG32ar" || 879 newInfo.name == "XCHG32ar64" || 880 newInfo.name == "XCHG64ar")) 881 continue; // special case for XCHG*ar and NOOP 882 883 if (previousInfo.name == "DATA16_PREFIX" && 884 newInfo.name == "DATA32_PREFIX") 885 continue; // special case for data16 and data32 886 887 if (outranks(previousInfo.insnContext, newInfo.insnContext)) 888 continue; 889 890 if (previousInfo.insnContext == newInfo.insnContext) { 891 errs() << "Error: Primary decode conflict: "; 892 errs() << newInfo.name << " would overwrite " << previousInfo.name; 893 errs() << "\n"; 894 errs() << "ModRM " << index << "\n"; 895 errs() << "Opcode " << (uint16_t)opcode << "\n"; 896 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n"; 897 HasConflicts = true; 898 } 899 } 900 901 decision.instructionIDs[index] = uid; 902 } 903 } 904 } 905 906 void DisassemblerTables::setTableFields(OpcodeType type, 907 InstructionContext insnContext, 908 uint8_t opcode, 909 const ModRMFilter &filter, 910 InstrUID uid, 911 bool is32bit, 912 bool ignoresVEX_L, 913 bool ignoresVEX_W, 914 unsigned addressSize) { 915 ContextDecision &decision = *Tables[type]; 916 917 for (unsigned index = 0; index < IC_max; ++index) { 918 if ((is32bit || addressSize == 16) && 919 inheritsFrom((InstructionContext)index, IC_64BIT)) 920 continue; 921 922 bool adSize64 = addressSize == 64; 923 if (inheritsFrom((InstructionContext)index, 924 InstructionSpecifiers[uid].insnContext, ignoresVEX_L, 925 ignoresVEX_W, adSize64)) 926 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode], 927 filter, 928 uid, 929 opcode); 930 } 931 } 932