1 //===--- InfoByHwMode.cpp -------------------------------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // Classes that implement data parameterized by HW modes for instruction 10 // selection. Currently it is ValueTypeByHwMode (parameterized ValueType), 11 // and RegSizeInfoByHwMode (parameterized register/spill size and alignment 12 // data). 13 //===----------------------------------------------------------------------===// 14 15 #include "CodeGenTarget.h" 16 #include "InfoByHwMode.h" 17 #include "llvm/ADT/STLExtras.h" 18 #include "llvm/ADT/Twine.h" 19 #include "llvm/Support/Debug.h" 20 #include "llvm/Support/raw_ostream.h" 21 22 #include <set> 23 #include <sstream> 24 #include <string> 25 26 using namespace llvm; 27 28 std::string llvm::getModeName(unsigned Mode) { 29 if (Mode == DefaultMode) 30 return "*"; 31 return (Twine('m') + Twine(Mode)).str(); 32 } 33 34 ValueTypeByHwMode::ValueTypeByHwMode(Record *R, const CodeGenHwModes &CGH) { 35 const HwModeSelect &MS = CGH.getHwModeSelect(R); 36 for (const HwModeSelect::PairType &P : MS.Items) { 37 auto I = Map.insert({P.first, MVT(llvm::getValueType(P.second))}); 38 assert(I.second && "Duplicate entry?"); 39 (void)I; 40 } 41 } 42 43 bool ValueTypeByHwMode::operator== (const ValueTypeByHwMode &T) const { 44 assert(isValid() && T.isValid() && "Invalid type in assignment"); 45 bool Simple = isSimple(); 46 if (Simple != T.isSimple()) 47 return false; 48 if (Simple) 49 return getSimple() == T.getSimple(); 50 51 return Map == T.Map; 52 } 53 54 bool ValueTypeByHwMode::operator< (const ValueTypeByHwMode &T) const { 55 assert(isValid() && T.isValid() && "Invalid type in comparison"); 56 // Default order for maps. 57 return Map < T.Map; 58 } 59 60 MVT &ValueTypeByHwMode::getOrCreateTypeForMode(unsigned Mode, MVT Type) { 61 auto F = Map.find(Mode); 62 if (F != Map.end()) 63 return F->second; 64 // If Mode is not in the map, look up the default mode. If it exists, 65 // make a copy of it for Mode and return it. 66 auto D = Map.find(DefaultMode); 67 if (D != Map.end()) 68 return Map.insert(std::make_pair(Mode, D->second)).first->second; 69 // If default mode is not present either, use provided Type. 70 return Map.insert(std::make_pair(Mode, Type)).first->second; 71 } 72 73 StringRef ValueTypeByHwMode::getMVTName(MVT T) { 74 StringRef N = llvm::getEnumName(T.SimpleTy); 75 N.consume_front("MVT::"); 76 return N; 77 } 78 79 void ValueTypeByHwMode::writeToStream(raw_ostream &OS) const { 80 if (isSimple()) { 81 OS << getMVTName(getSimple()); 82 return; 83 } 84 85 std::vector<const PairType*> Pairs; 86 for (const auto &P : Map) 87 Pairs.push_back(&P); 88 std::sort(Pairs.begin(), Pairs.end(), deref<std::less<PairType>>()); 89 90 OS << '{'; 91 for (unsigned i = 0, e = Pairs.size(); i != e; ++i) { 92 const PairType *P = Pairs[i]; 93 OS << '(' << getModeName(P->first) 94 << ':' << getMVTName(P->second).str() << ')'; 95 if (i != e-1) 96 OS << ','; 97 } 98 OS << '}'; 99 } 100 101 LLVM_DUMP_METHOD 102 void ValueTypeByHwMode::dump() const { 103 dbgs() << *this << '\n'; 104 } 105 106 ValueTypeByHwMode llvm::getValueTypeByHwMode(Record *Rec, 107 const CodeGenHwModes &CGH) { 108 #ifndef NDEBUG 109 if (!Rec->isSubClassOf("ValueType")) 110 Rec->dump(); 111 #endif 112 assert(Rec->isSubClassOf("ValueType") && 113 "Record must be derived from ValueType"); 114 if (Rec->isSubClassOf("HwModeSelect")) 115 return ValueTypeByHwMode(Rec, CGH); 116 return ValueTypeByHwMode(llvm::getValueType(Rec)); 117 } 118 119 RegSizeInfo::RegSizeInfo(Record *R, const CodeGenHwModes &CGH) { 120 RegSize = R->getValueAsInt("RegSize"); 121 SpillSize = R->getValueAsInt("SpillSize"); 122 SpillAlignment = R->getValueAsInt("SpillAlignment"); 123 } 124 125 bool RegSizeInfo::operator< (const RegSizeInfo &I) const { 126 return std::tie(RegSize, SpillSize, SpillAlignment) < 127 std::tie(I.RegSize, I.SpillSize, I.SpillAlignment); 128 } 129 130 bool RegSizeInfo::isSubClassOf(const RegSizeInfo &I) const { 131 return RegSize <= I.RegSize && 132 SpillAlignment && I.SpillAlignment % SpillAlignment == 0 && 133 SpillSize <= I.SpillSize; 134 } 135 136 void RegSizeInfo::writeToStream(raw_ostream &OS) const { 137 OS << "[R=" << RegSize << ",S=" << SpillSize 138 << ",A=" << SpillAlignment << ']'; 139 } 140 141 RegSizeInfoByHwMode::RegSizeInfoByHwMode(Record *R, 142 const CodeGenHwModes &CGH) { 143 const HwModeSelect &MS = CGH.getHwModeSelect(R); 144 for (const HwModeSelect::PairType &P : MS.Items) { 145 auto I = Map.insert({P.first, RegSizeInfo(P.second, CGH)}); 146 assert(I.second && "Duplicate entry?"); 147 (void)I; 148 } 149 } 150 151 bool RegSizeInfoByHwMode::operator< (const RegSizeInfoByHwMode &I) const { 152 unsigned M0 = Map.begin()->first; 153 return get(M0) < I.get(M0); 154 } 155 156 bool RegSizeInfoByHwMode::operator== (const RegSizeInfoByHwMode &I) const { 157 unsigned M0 = Map.begin()->first; 158 return get(M0) == I.get(M0); 159 } 160 161 bool RegSizeInfoByHwMode::isSubClassOf(const RegSizeInfoByHwMode &I) const { 162 unsigned M0 = Map.begin()->first; 163 return get(M0).isSubClassOf(I.get(M0)); 164 } 165 166 bool RegSizeInfoByHwMode::hasStricterSpillThan(const RegSizeInfoByHwMode &I) 167 const { 168 unsigned M0 = Map.begin()->first; 169 const RegSizeInfo &A0 = get(M0); 170 const RegSizeInfo &B0 = I.get(M0); 171 return std::tie(A0.SpillSize, A0.SpillAlignment) > 172 std::tie(B0.SpillSize, B0.SpillAlignment); 173 } 174 175 void RegSizeInfoByHwMode::writeToStream(raw_ostream &OS) const { 176 typedef typename decltype(Map)::value_type PairType; 177 std::vector<const PairType*> Pairs; 178 for (const auto &P : Map) 179 Pairs.push_back(&P); 180 std::sort(Pairs.begin(), Pairs.end(), deref<std::less<PairType>>()); 181 182 OS << '{'; 183 for (unsigned i = 0, e = Pairs.size(); i != e; ++i) { 184 const PairType *P = Pairs[i]; 185 OS << '(' << getModeName(P->first) << ':' << P->second << ')'; 186 if (i != e-1) 187 OS << ','; 188 } 189 OS << '}'; 190 } 191 192 namespace llvm { 193 raw_ostream &operator<<(raw_ostream &OS, const ValueTypeByHwMode &T) { 194 T.writeToStream(OS); 195 return OS; 196 } 197 198 raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfo &T) { 199 T.writeToStream(OS); 200 return OS; 201 } 202 203 raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfoByHwMode &T) { 204 T.writeToStream(OS); 205 return OS; 206 } 207 } 208