1 //===- DisassemblerEmitter.cpp - Generate a disassembler ------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "DisassemblerEmitter.h" 11 #include "CodeGenTarget.h" 12 #include "Record.h" 13 #include "X86DisassemblerTables.h" 14 #include "X86RecognizableInstr.h" 15 #include "ARMDecoderEmitter.h" 16 17 using namespace llvm; 18 using namespace llvm::X86Disassembler; 19 20 /// DisassemblerEmitter - Contains disassembler table emitters for various 21 /// architectures. 22 23 /// X86 Disassembler Emitter 24 /// 25 /// *** IF YOU'RE HERE TO RESOLVE A "Primary decode conflict", LOOK DOWN NEAR 26 /// THE END OF THIS COMMENT! 27 /// 28 /// The X86 disassembler emitter is part of the X86 Disassembler, which is 29 /// documented in lib/Target/X86/X86Disassembler.h. 30 /// 31 /// The emitter produces the tables that the disassembler uses to translate 32 /// instructions. The emitter generates the following tables: 33 /// 34 /// - One table (CONTEXTS_SYM) that contains a mapping of attribute masks to 35 /// instruction contexts. Although for each attribute there are cases where 36 /// that attribute determines decoding, in the majority of cases decoding is 37 /// the same whether or not an attribute is present. For example, a 64-bit 38 /// instruction with an OPSIZE prefix and an XS prefix decodes the same way in 39 /// all cases as a 64-bit instruction with only OPSIZE set. (The XS prefix 40 /// may have effects on its execution, but does not change the instruction 41 /// returned.) This allows considerable space savings in other tables. 42 /// - Four tables (ONEBYTE_SYM, TWOBYTE_SYM, THREEBYTE38_SYM, and 43 /// THREEBYTE3A_SYM) contain the hierarchy that the decoder traverses while 44 /// decoding an instruction. At the lowest level of this hierarchy are 45 /// instruction UIDs, 16-bit integers that can be used to uniquely identify 46 /// the instruction and correspond exactly to its position in the list of 47 /// CodeGenInstructions for the target. 48 /// - One table (INSTRUCTIONS_SYM) contains information about the operands of 49 /// each instruction and how to decode them. 50 /// 51 /// During table generation, there may be conflicts between instructions that 52 /// occupy the same space in the decode tables. These conflicts are resolved as 53 /// follows in setTableFields() (X86DisassemblerTables.cpp) 54 /// 55 /// - If the current context is the native context for one of the instructions 56 /// (that is, the attributes specified for it in the LLVM tables specify 57 /// precisely the current context), then it has priority. 58 /// - If the current context isn't native for either of the instructions, then 59 /// the higher-priority context wins (that is, the one that is more specific). 60 /// That hierarchy is determined by outranks() (X86DisassemblerTables.cpp) 61 /// - If the current context is native for both instructions, then the table 62 /// emitter reports a conflict and dies. 63 /// 64 /// *** RESOLUTION FOR "Primary decode conflict"S 65 /// 66 /// If two instructions collide, typically the solution is (in order of 67 /// likelihood): 68 /// 69 /// (1) to filter out one of the instructions by editing filter() 70 /// (X86RecognizableInstr.cpp). This is the most common resolution, but 71 /// check the Intel manuals first to make sure that (2) and (3) are not the 72 /// problem. 73 /// (2) to fix the tables (X86.td and its subsidiaries) so the opcodes are 74 /// accurate. Sometimes they are not. 75 /// (3) to fix the tables to reflect the actual context (for example, required 76 /// prefixes), and possibly to add a new context by editing 77 /// lib/Target/X86/X86DisassemblerDecoderCommon.h. This is unlikely to be 78 /// the cause. 79 /// 80 /// DisassemblerEmitter.cpp contains the implementation for the emitter, 81 /// which simply pulls out instructions from the CodeGenTarget and pushes them 82 /// into X86DisassemblerTables. 83 /// X86DisassemblerTables.h contains the interface for the instruction tables, 84 /// which manage and emit the structures discussed above. 85 /// X86DisassemblerTables.cpp contains the implementation for the instruction 86 /// tables. 87 /// X86ModRMFilters.h contains filters that can be used to determine which 88 /// ModR/M values are valid for a particular instruction. These are used to 89 /// populate ModRMDecisions. 90 /// X86RecognizableInstr.h contains the interface for a single instruction, 91 /// which knows how to translate itself from a CodeGenInstruction and provide 92 /// the information necessary for integration into the tables. 93 /// X86RecognizableInstr.cpp contains the implementation for a single 94 /// instruction. 95 96 void DisassemblerEmitter::run(raw_ostream &OS) { 97 CodeGenTarget Target(Records); 98 99 OS << "/*===- TableGen'erated file " 100 << "---------------------------------------*- C -*-===*\n" 101 << " *\n" 102 << " * " << Target.getName() << " Disassembler\n" 103 << " *\n" 104 << " * Automatically generated file, do not edit!\n" 105 << " *\n" 106 << " *===---------------------------------------------------------------" 107 << "-------===*/\n"; 108 109 // X86 uses a custom disassembler. 110 if (Target.getName() == "X86") { 111 DisassemblerTables Tables; 112 113 const std::vector<const CodeGenInstruction*> &numberedInstructions = 114 Target.getInstructionsByEnumValue(); 115 116 for (unsigned i = 0, e = numberedInstructions.size(); i != e; ++i) 117 RecognizableInstr::processInstr(Tables, *numberedInstructions[i], i); 118 119 // FIXME: As long as we are using exceptions, might as well drop this to the 120 // actual conflict site. 121 if (Tables.hasConflicts()) 122 throw TGError(Target.getTargetRecord()->getLoc(), 123 "Primary decode conflict"); 124 125 Tables.emit(OS); 126 return; 127 } 128 129 // Fixed-instruction-length targets use a common disassembler. 130 if (Target.getName() == "ARM") { 131 ARMDecoderEmitter(Records).run(OS); 132 return; 133 } 134 135 throw TGError(Target.getTargetRecord()->getLoc(), 136 "Unable to generate disassembler for this target"); 137 } 138