1 //===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines wrappers for the Target class and related global
11 // functionality.  This makes it easier to access the data and provides a single
12 // place that needs to check it for validity.  All of these classes abort
13 // on error conditions.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_UTILS_TABLEGEN_CODEGENTARGET_H
18 #define LLVM_UTILS_TABLEGEN_CODEGENTARGET_H
19 
20 #include "CodeGenHwModes.h"
21 #include "CodeGenInstruction.h"
22 #include "CodeGenRegisters.h"
23 #include "InfoByHwMode.h"
24 #include "llvm/Support/raw_ostream.h"
25 #include "llvm/TableGen/Record.h"
26 #include <algorithm>
27 
28 namespace llvm {
29 
30 struct CodeGenRegister;
31 class CodeGenSchedModels;
32 class CodeGenTarget;
33 
34 // SelectionDAG node properties.
35 //  SDNPMemOperand: indicates that a node touches memory and therefore must
36 //                  have an associated memory operand that describes the access.
37 enum SDNP {
38   SDNPCommutative,
39   SDNPAssociative,
40   SDNPHasChain,
41   SDNPOutGlue,
42   SDNPInGlue,
43   SDNPOptInGlue,
44   SDNPMayLoad,
45   SDNPMayStore,
46   SDNPSideEffect,
47   SDNPMemOperand,
48   SDNPVariadic,
49   SDNPWantRoot,
50   SDNPWantParent
51 };
52 
53 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
54 /// record corresponds to.
55 MVT::SimpleValueType getValueType(Record *Rec);
56 
57 StringRef getName(MVT::SimpleValueType T);
58 StringRef getEnumName(MVT::SimpleValueType T);
59 
60 /// getQualifiedName - Return the name of the specified record, with a
61 /// namespace qualifier if the record contains one.
62 std::string getQualifiedName(const Record *R);
63 
64 /// CodeGenTarget - This class corresponds to the Target class in the .td files.
65 ///
66 class CodeGenTarget {
67   RecordKeeper &Records;
68   Record *TargetRec;
69 
70   mutable DenseMap<const Record*,
71                    std::unique_ptr<CodeGenInstruction>> Instructions;
72   mutable std::unique_ptr<CodeGenRegBank> RegBank;
73   mutable std::vector<Record*> RegAltNameIndices;
74   mutable SmallVector<ValueTypeByHwMode, 8> LegalValueTypes;
75   CodeGenHwModes CGH;
76   void ReadRegAltNameIndices() const;
77   void ReadInstructions() const;
78   void ReadLegalValueTypes() const;
79 
80   mutable std::unique_ptr<CodeGenSchedModels> SchedModels;
81 
82   mutable std::vector<const CodeGenInstruction*> InstrsByEnum;
83 public:
84   CodeGenTarget(RecordKeeper &Records);
85   ~CodeGenTarget();
86 
87   Record *getTargetRecord() const { return TargetRec; }
88   const StringRef getName() const;
89 
90   /// getInstNamespace - Return the target-specific instruction namespace.
91   ///
92   StringRef getInstNamespace() const;
93 
94   /// getInstructionSet - Return the InstructionSet object.
95   ///
96   Record *getInstructionSet() const;
97 
98   /// getAsmParser - Return the AssemblyParser definition for this target.
99   ///
100   Record *getAsmParser() const;
101 
102   /// getAsmParserVariant - Return the AssmblyParserVariant definition for
103   /// this target.
104   ///
105   Record *getAsmParserVariant(unsigned i) const;
106 
107   /// getAsmParserVariantCount - Return the AssmblyParserVariant definition
108   /// available for this target.
109   ///
110   unsigned getAsmParserVariantCount() const;
111 
112   /// getAsmWriter - Return the AssemblyWriter definition for this target.
113   ///
114   Record *getAsmWriter() const;
115 
116   /// getRegBank - Return the register bank description.
117   CodeGenRegBank &getRegBank() const;
118 
119   /// getRegisterByName - If there is a register with the specific AsmName,
120   /// return it.
121   const CodeGenRegister *getRegisterByName(StringRef Name) const;
122 
123   const std::vector<Record*> &getRegAltNameIndices() const {
124     if (RegAltNameIndices.empty()) ReadRegAltNameIndices();
125     return RegAltNameIndices;
126   }
127 
128   const CodeGenRegisterClass &getRegisterClass(Record *R) const {
129     return *getRegBank().getRegClass(R);
130   }
131 
132   /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the
133   /// specified physical register.
134   std::vector<ValueTypeByHwMode> getRegisterVTs(Record *R) const;
135 
136   ArrayRef<ValueTypeByHwMode> getLegalValueTypes() const {
137     if (LegalValueTypes.empty())
138       ReadLegalValueTypes();
139     return LegalValueTypes;
140   }
141 
142   CodeGenSchedModels &getSchedModels() const;
143 
144   const CodeGenHwModes &getHwModes() const { return CGH; }
145 
146 private:
147   DenseMap<const Record*, std::unique_ptr<CodeGenInstruction>> &
148   getInstructions() const {
149     if (Instructions.empty()) ReadInstructions();
150     return Instructions;
151   }
152 public:
153 
154   CodeGenInstruction &getInstruction(const Record *InstRec) const {
155     if (Instructions.empty()) ReadInstructions();
156     auto I = Instructions.find(InstRec);
157     assert(I != Instructions.end() && "Not an instruction");
158     return *I->second;
159   }
160 
161   /// getInstructionsByEnumValue - Return all of the instructions defined by the
162   /// target, ordered by their enum value.
163   ArrayRef<const CodeGenInstruction *>
164   getInstructionsByEnumValue() const {
165     if (InstrsByEnum.empty()) ComputeInstrsByEnum();
166     return InstrsByEnum;
167   }
168 
169   typedef ArrayRef<const CodeGenInstruction *>::const_iterator inst_iterator;
170   inst_iterator inst_begin() const{return getInstructionsByEnumValue().begin();}
171   inst_iterator inst_end() const { return getInstructionsByEnumValue().end(); }
172 
173 
174   /// isLittleEndianEncoding - are instruction bit patterns defined as  [0..n]?
175   ///
176   bool isLittleEndianEncoding() const;
177 
178   /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit
179   /// encodings, reverse the bit order of all instructions.
180   void reverseBitsForLittleEndianEncoding();
181 
182   /// guessInstructionProperties - should we just guess unset instruction
183   /// properties?
184   bool guessInstructionProperties() const;
185 
186 private:
187   void ComputeInstrsByEnum() const;
188 };
189 
190 /// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern
191 /// tablegen class in TargetSelectionDAG.td
192 class ComplexPattern {
193   MVT::SimpleValueType Ty;
194   unsigned NumOperands;
195   std::string SelectFunc;
196   std::vector<Record*> RootNodes;
197   unsigned Properties; // Node properties
198   unsigned Complexity;
199 public:
200   ComplexPattern(Record *R);
201 
202   MVT::SimpleValueType getValueType() const { return Ty; }
203   unsigned getNumOperands() const { return NumOperands; }
204   const std::string &getSelectFunc() const { return SelectFunc; }
205   const std::vector<Record*> &getRootNodes() const {
206     return RootNodes;
207   }
208   bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); }
209   unsigned getComplexity() const { return Complexity; }
210 };
211 
212 } // End llvm namespace
213 
214 #endif
215