1 //===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines wrappers for the Target class and related global
11 // functionality.  This makes it easier to access the data and provides a single
12 // place that needs to check it for validity.  All of these classes abort
13 // on error conditions.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_UTILS_TABLEGEN_CODEGENTARGET_H
18 #define LLVM_UTILS_TABLEGEN_CODEGENTARGET_H
19 
20 #include "CodeGenHwModes.h"
21 #include "CodeGenInstruction.h"
22 #include "CodeGenRegisters.h"
23 #include "InfoByHwMode.h"
24 #include "SDNodeProperties.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/TableGen/Record.h"
27 #include <algorithm>
28 
29 namespace llvm {
30 
31 struct CodeGenRegister;
32 class CodeGenSchedModels;
33 class CodeGenTarget;
34 
35 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
36 /// record corresponds to.
37 MVT::SimpleValueType getValueType(Record *Rec);
38 
39 StringRef getName(MVT::SimpleValueType T);
40 StringRef getEnumName(MVT::SimpleValueType T);
41 
42 /// getQualifiedName - Return the name of the specified record, with a
43 /// namespace qualifier if the record contains one.
44 std::string getQualifiedName(const Record *R);
45 
46 /// CodeGenTarget - This class corresponds to the Target class in the .td files.
47 ///
48 class CodeGenTarget {
49   RecordKeeper &Records;
50   Record *TargetRec;
51 
52   mutable DenseMap<const Record*,
53                    std::unique_ptr<CodeGenInstruction>> Instructions;
54   mutable std::unique_ptr<CodeGenRegBank> RegBank;
55   mutable std::vector<Record*> RegAltNameIndices;
56   mutable SmallVector<ValueTypeByHwMode, 8> LegalValueTypes;
57   CodeGenHwModes CGH;
58   void ReadRegAltNameIndices() const;
59   void ReadInstructions() const;
60   void ReadLegalValueTypes() const;
61 
62   mutable std::unique_ptr<CodeGenSchedModels> SchedModels;
63 
64   mutable std::vector<const CodeGenInstruction*> InstrsByEnum;
65 public:
66   CodeGenTarget(RecordKeeper &Records);
67   ~CodeGenTarget();
68 
69   Record *getTargetRecord() const { return TargetRec; }
70   const StringRef getName() const;
71 
72   /// getInstNamespace - Return the target-specific instruction namespace.
73   ///
74   StringRef getInstNamespace() const;
75 
76   /// getInstructionSet - Return the InstructionSet object.
77   ///
78   Record *getInstructionSet() const;
79 
80   /// getAllowRegisterRenaming - Return the AllowRegisterRenaming flag value for
81   /// this target.
82   ///
83   bool getAllowRegisterRenaming() const;
84 
85   /// getAsmParser - Return the AssemblyParser definition for this target.
86   ///
87   Record *getAsmParser() const;
88 
89   /// getAsmParserVariant - Return the AssmblyParserVariant definition for
90   /// this target.
91   ///
92   Record *getAsmParserVariant(unsigned i) const;
93 
94   /// getAsmParserVariantCount - Return the AssmblyParserVariant definition
95   /// available for this target.
96   ///
97   unsigned getAsmParserVariantCount() const;
98 
99   /// getAsmWriter - Return the AssemblyWriter definition for this target.
100   ///
101   Record *getAsmWriter() const;
102 
103   /// getRegBank - Return the register bank description.
104   CodeGenRegBank &getRegBank() const;
105 
106   /// getRegisterByName - If there is a register with the specific AsmName,
107   /// return it.
108   const CodeGenRegister *getRegisterByName(StringRef Name) const;
109 
110   const std::vector<Record*> &getRegAltNameIndices() const {
111     if (RegAltNameIndices.empty()) ReadRegAltNameIndices();
112     return RegAltNameIndices;
113   }
114 
115   const CodeGenRegisterClass &getRegisterClass(Record *R) const {
116     return *getRegBank().getRegClass(R);
117   }
118 
119   /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the
120   /// specified physical register.
121   std::vector<ValueTypeByHwMode> getRegisterVTs(Record *R) const;
122 
123   ArrayRef<ValueTypeByHwMode> getLegalValueTypes() const {
124     if (LegalValueTypes.empty())
125       ReadLegalValueTypes();
126     return LegalValueTypes;
127   }
128 
129   CodeGenSchedModels &getSchedModels() const;
130 
131   const CodeGenHwModes &getHwModes() const { return CGH; }
132 
133 private:
134   DenseMap<const Record*, std::unique_ptr<CodeGenInstruction>> &
135   getInstructions() const {
136     if (Instructions.empty()) ReadInstructions();
137     return Instructions;
138   }
139 public:
140 
141   CodeGenInstruction &getInstruction(const Record *InstRec) const {
142     if (Instructions.empty()) ReadInstructions();
143     auto I = Instructions.find(InstRec);
144     assert(I != Instructions.end() && "Not an instruction");
145     return *I->second;
146   }
147 
148   /// Returns the number of predefined instructions.
149   static unsigned getNumFixedInstructions();
150 
151   /// Return all of the instructions defined by the target, ordered by their
152   /// enum value.
153   ArrayRef<const CodeGenInstruction *> getInstructionsByEnumValue() const {
154     if (InstrsByEnum.empty())
155       ComputeInstrsByEnum();
156     return InstrsByEnum;
157   }
158 
159   typedef ArrayRef<const CodeGenInstruction *>::const_iterator inst_iterator;
160   inst_iterator inst_begin() const{return getInstructionsByEnumValue().begin();}
161   inst_iterator inst_end() const { return getInstructionsByEnumValue().end(); }
162 
163 
164   /// isLittleEndianEncoding - are instruction bit patterns defined as  [0..n]?
165   ///
166   bool isLittleEndianEncoding() const;
167 
168   /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit
169   /// encodings, reverse the bit order of all instructions.
170   void reverseBitsForLittleEndianEncoding();
171 
172   /// guessInstructionProperties - should we just guess unset instruction
173   /// properties?
174   bool guessInstructionProperties() const;
175 
176 private:
177   void ComputeInstrsByEnum() const;
178 };
179 
180 /// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern
181 /// tablegen class in TargetSelectionDAG.td
182 class ComplexPattern {
183   MVT::SimpleValueType Ty;
184   unsigned NumOperands;
185   std::string SelectFunc;
186   std::vector<Record*> RootNodes;
187   unsigned Properties; // Node properties
188   unsigned Complexity;
189 public:
190   ComplexPattern(Record *R);
191 
192   MVT::SimpleValueType getValueType() const { return Ty; }
193   unsigned getNumOperands() const { return NumOperands; }
194   const std::string &getSelectFunc() const { return SelectFunc; }
195   const std::vector<Record*> &getRootNodes() const {
196     return RootNodes;
197   }
198   bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); }
199   unsigned getComplexity() const { return Complexity; }
200 };
201 
202 } // End llvm namespace
203 
204 #endif
205