1 //===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines wrappers for the Target class and related global 10 // functionality. This makes it easier to access the data and provides a single 11 // place that needs to check it for validity. All of these classes abort 12 // on error conditions. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_UTILS_TABLEGEN_CODEGENTARGET_H 17 #define LLVM_UTILS_TABLEGEN_CODEGENTARGET_H 18 19 #include "CodeGenHwModes.h" 20 #include "CodeGenInstruction.h" 21 #include "CodeGenRegisters.h" 22 #include "InfoByHwMode.h" 23 #include "SDNodeProperties.h" 24 #include "llvm/Support/raw_ostream.h" 25 #include "llvm/TableGen/Record.h" 26 #include <algorithm> 27 28 namespace llvm { 29 30 struct CodeGenRegister; 31 class CodeGenSchedModels; 32 class CodeGenTarget; 33 34 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen 35 /// record corresponds to. 36 MVT::SimpleValueType getValueType(Record *Rec); 37 38 StringRef getName(MVT::SimpleValueType T); 39 StringRef getEnumName(MVT::SimpleValueType T); 40 41 /// getQualifiedName - Return the name of the specified record, with a 42 /// namespace qualifier if the record contains one. 43 std::string getQualifiedName(const Record *R); 44 45 /// CodeGenTarget - This class corresponds to the Target class in the .td files. 46 /// 47 class CodeGenTarget { 48 RecordKeeper &Records; 49 Record *TargetRec; 50 51 mutable DenseMap<const Record*, 52 std::unique_ptr<CodeGenInstruction>> Instructions; 53 mutable std::unique_ptr<CodeGenRegBank> RegBank; 54 mutable std::vector<Record*> RegAltNameIndices; 55 mutable SmallVector<ValueTypeByHwMode, 8> LegalValueTypes; 56 CodeGenHwModes CGH; 57 void ReadRegAltNameIndices() const; 58 void ReadInstructions() const; 59 void ReadLegalValueTypes() const; 60 61 mutable std::unique_ptr<CodeGenSchedModels> SchedModels; 62 63 mutable std::vector<const CodeGenInstruction*> InstrsByEnum; 64 mutable unsigned NumPseudoInstructions = 0; 65 public: 66 CodeGenTarget(RecordKeeper &Records); 67 ~CodeGenTarget(); 68 69 Record *getTargetRecord() const { return TargetRec; } 70 const StringRef getName() const; 71 72 /// getInstNamespace - Return the target-specific instruction namespace. 73 /// 74 StringRef getInstNamespace() const; 75 76 /// getRegNamespace - Return the target-specific register namespace. 77 StringRef getRegNamespace() const; 78 79 /// getInstructionSet - Return the InstructionSet object. 80 /// 81 Record *getInstructionSet() const; 82 83 /// getAllowRegisterRenaming - Return the AllowRegisterRenaming flag value for 84 /// this target. 85 /// 86 bool getAllowRegisterRenaming() const; 87 88 /// getAsmParser - Return the AssemblyParser definition for this target. 89 /// 90 Record *getAsmParser() const; 91 92 /// getAsmParserVariant - Return the AssemblyParserVariant definition for 93 /// this target. 94 /// 95 Record *getAsmParserVariant(unsigned i) const; 96 97 /// getAsmParserVariantCount - Return the AssemblyParserVariant definition 98 /// available for this target. 99 /// 100 unsigned getAsmParserVariantCount() const; 101 102 /// getAsmWriter - Return the AssemblyWriter definition for this target. 103 /// 104 Record *getAsmWriter() const; 105 106 /// getRegBank - Return the register bank description. 107 CodeGenRegBank &getRegBank() const; 108 109 /// Return the largest register class on \p RegBank which supports \p Ty and 110 /// covers \p SubIdx if it exists. 111 Optional<CodeGenRegisterClass *> 112 getSuperRegForSubReg(const ValueTypeByHwMode &Ty, CodeGenRegBank &RegBank, 113 const CodeGenSubRegIndex *SubIdx) const; 114 115 /// getRegisterByName - If there is a register with the specific AsmName, 116 /// return it. 117 const CodeGenRegister *getRegisterByName(StringRef Name) const; 118 119 const std::vector<Record*> &getRegAltNameIndices() const { 120 if (RegAltNameIndices.empty()) ReadRegAltNameIndices(); 121 return RegAltNameIndices; 122 } 123 124 const CodeGenRegisterClass &getRegisterClass(Record *R) const { 125 return *getRegBank().getRegClass(R); 126 } 127 128 /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the 129 /// specified physical register. 130 std::vector<ValueTypeByHwMode> getRegisterVTs(Record *R) const; 131 132 ArrayRef<ValueTypeByHwMode> getLegalValueTypes() const { 133 if (LegalValueTypes.empty()) 134 ReadLegalValueTypes(); 135 return LegalValueTypes; 136 } 137 138 CodeGenSchedModels &getSchedModels() const; 139 140 const CodeGenHwModes &getHwModes() const { return CGH; } 141 142 private: 143 DenseMap<const Record*, std::unique_ptr<CodeGenInstruction>> & 144 getInstructions() const { 145 if (Instructions.empty()) ReadInstructions(); 146 return Instructions; 147 } 148 public: 149 150 CodeGenInstruction &getInstruction(const Record *InstRec) const { 151 if (Instructions.empty()) ReadInstructions(); 152 auto I = Instructions.find(InstRec); 153 assert(I != Instructions.end() && "Not an instruction"); 154 return *I->second; 155 } 156 157 /// Returns the number of predefined instructions. 158 static unsigned getNumFixedInstructions(); 159 160 /// Returns the number of pseudo instructions. 161 unsigned getNumPseudoInstructions() const { 162 if (InstrsByEnum.empty()) 163 ComputeInstrsByEnum(); 164 return NumPseudoInstructions; 165 } 166 167 /// Return all of the instructions defined by the target, ordered by their 168 /// enum value. 169 /// The following order of instructions is also guaranteed: 170 /// - fixed / generic instructions as declared in TargetOpcodes.def, in order; 171 /// - pseudo instructions in lexicographical order sorted by name; 172 /// - other instructions in lexicographical order sorted by name. 173 ArrayRef<const CodeGenInstruction *> getInstructionsByEnumValue() const { 174 if (InstrsByEnum.empty()) 175 ComputeInstrsByEnum(); 176 return InstrsByEnum; 177 } 178 179 typedef ArrayRef<const CodeGenInstruction *>::const_iterator inst_iterator; 180 inst_iterator inst_begin() const{return getInstructionsByEnumValue().begin();} 181 inst_iterator inst_end() const { return getInstructionsByEnumValue().end(); } 182 183 184 /// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]? 185 /// 186 bool isLittleEndianEncoding() const; 187 188 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit 189 /// encodings, reverse the bit order of all instructions. 190 void reverseBitsForLittleEndianEncoding(); 191 192 /// guessInstructionProperties - should we just guess unset instruction 193 /// properties? 194 bool guessInstructionProperties() const; 195 196 private: 197 void ComputeInstrsByEnum() const; 198 }; 199 200 /// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern 201 /// tablegen class in TargetSelectionDAG.td 202 class ComplexPattern { 203 MVT::SimpleValueType Ty; 204 unsigned NumOperands; 205 std::string SelectFunc; 206 std::vector<Record*> RootNodes; 207 unsigned Properties; // Node properties 208 unsigned Complexity; 209 public: 210 ComplexPattern(Record *R); 211 212 MVT::SimpleValueType getValueType() const { return Ty; } 213 unsigned getNumOperands() const { return NumOperands; } 214 const std::string &getSelectFunc() const { return SelectFunc; } 215 const std::vector<Record*> &getRootNodes() const { 216 return RootNodes; 217 } 218 bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); } 219 unsigned getComplexity() const { return Complexity; } 220 }; 221 222 } // End llvm namespace 223 224 #endif 225