1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper ---------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file was developed by the LLVM research group and is distributed under 6 // the University of Illinois Open Source License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This class wrap target description classes used by the various code 11 // generation TableGen backends. This makes it easier to access the data and 12 // provides a single place that needs to check it for validity. All of these 13 // classes throw exceptions on error conditions. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "CodeGenTarget.h" 18 #include "Record.h" 19 #include "llvm/ADT/StringExtras.h" 20 #include "llvm/Support/CommandLine.h" 21 #include <set> 22 #include <algorithm> 23 using namespace llvm; 24 25 static cl::opt<unsigned> 26 AsmWriterNum("asmwriternum", cl::init(0), 27 cl::desc("Make -gen-asm-writer emit assembly writer #N")); 28 29 /// getValueType - Return the MCV::ValueType that the specified TableGen record 30 /// corresponds to. 31 MVT::ValueType llvm::getValueType(Record *Rec) { 32 return (MVT::ValueType)Rec->getValueAsInt("Value"); 33 } 34 35 std::string llvm::getName(MVT::ValueType T) { 36 switch (T) { 37 case MVT::Other: return "UNKNOWN"; 38 case MVT::i1: return "i1"; 39 case MVT::i8: return "i8"; 40 case MVT::i16: return "i16"; 41 case MVT::i32: return "i32"; 42 case MVT::i64: return "i64"; 43 case MVT::i128: return "i128"; 44 case MVT::f32: return "f32"; 45 case MVT::f64: return "f64"; 46 case MVT::f80: return "f80"; 47 case MVT::f128: return "f128"; 48 case MVT::isVoid:return "void"; 49 case MVT::v16i8: return "v16i8"; 50 case MVT::v8i16: return "v8i16"; 51 case MVT::v4i32: return "v4i32"; 52 case MVT::v2i64: return "v2i64"; 53 case MVT::v4f32: return "v4f32"; 54 case MVT::v2f64: return "v2f64"; 55 default: assert(0 && "ILLEGAL VALUE TYPE!"); return ""; 56 } 57 } 58 59 std::string llvm::getEnumName(MVT::ValueType T) { 60 switch (T) { 61 case MVT::Other: return "Other"; 62 case MVT::i1: return "i1"; 63 case MVT::i8: return "i8"; 64 case MVT::i16: return "i16"; 65 case MVT::i32: return "i32"; 66 case MVT::i64: return "i64"; 67 case MVT::i128: return "i128"; 68 case MVT::f32: return "f32"; 69 case MVT::f64: return "f64"; 70 case MVT::f80: return "f80"; 71 case MVT::f128: return "f128"; 72 case MVT::isVoid:return "isVoid"; 73 case MVT::v16i8: return "v16i8"; 74 case MVT::v8i16: return "v8i16"; 75 case MVT::v4i32: return "v4i32"; 76 case MVT::v2i64: return "v2i64"; 77 case MVT::v4f32: return "v4f32"; 78 case MVT::v2f64: return "v2f64"; 79 default: assert(0 && "ILLEGAL VALUE TYPE!"); return ""; 80 } 81 } 82 83 84 std::ostream &llvm::operator<<(std::ostream &OS, MVT::ValueType T) { 85 return OS << getName(T); 86 } 87 88 89 /// getTarget - Return the current instance of the Target class. 90 /// 91 CodeGenTarget::CodeGenTarget() : PointerType(MVT::Other) { 92 std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target"); 93 if (Targets.size() == 0) 94 throw std::string("ERROR: No 'Target' subclasses defined!"); 95 if (Targets.size() != 1) 96 throw std::string("ERROR: Multiple subclasses of Target defined!"); 97 TargetRec = Targets[0]; 98 99 // Read in all of the CalleeSavedRegisters. 100 CalleeSavedRegisters =TargetRec->getValueAsListOfDefs("CalleeSavedRegisters"); 101 PointerType = getValueType(TargetRec->getValueAsDef("PointerType")); 102 } 103 104 105 const std::string &CodeGenTarget::getName() const { 106 return TargetRec->getName(); 107 } 108 109 Record *CodeGenTarget::getInstructionSet() const { 110 return TargetRec->getValueAsDef("InstructionSet"); 111 } 112 113 /// getAsmWriter - Return the AssemblyWriter definition for this target. 114 /// 115 Record *CodeGenTarget::getAsmWriter() const { 116 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters"); 117 if (AsmWriterNum >= LI.size()) 118 throw "Target does not have an AsmWriter #" + utostr(AsmWriterNum) + "!"; 119 return LI[AsmWriterNum]; 120 } 121 122 void CodeGenTarget::ReadRegisters() const { 123 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); 124 if (Regs.empty()) 125 throw std::string("No 'Register' subclasses defined!"); 126 127 Registers.reserve(Regs.size()); 128 Registers.assign(Regs.begin(), Regs.end()); 129 } 130 131 CodeGenRegister::CodeGenRegister(Record *R) : TheDef(R) { 132 DeclaredSpillSize = R->getValueAsInt("SpillSize"); 133 DeclaredSpillAlignment = R->getValueAsInt("SpillAlignment"); 134 } 135 136 const std::string &CodeGenRegister::getName() const { 137 return TheDef->getName(); 138 } 139 140 void CodeGenTarget::ReadRegisterClasses() const { 141 std::vector<Record*> RegClasses = 142 Records.getAllDerivedDefinitions("RegisterClass"); 143 if (RegClasses.empty()) 144 throw std::string("No 'RegisterClass' subclasses defined!"); 145 146 RegisterClasses.reserve(RegClasses.size()); 147 RegisterClasses.assign(RegClasses.begin(), RegClasses.end()); 148 } 149 150 CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) { 151 // Rename anonymous register classes. 152 if (R->getName().size() > 9 && R->getName()[9] == '.') { 153 static unsigned AnonCounter = 0; 154 R->setName("AnonRegClass_"+utostr(AnonCounter++)); 155 } 156 157 Namespace = R->getValueAsString("Namespace"); 158 SpillSize = R->getValueAsInt("Size"); 159 SpillAlignment = R->getValueAsInt("Alignment"); 160 VT = getValueType(R->getValueAsDef("RegType")); 161 162 MethodBodies = R->getValueAsCode("MethodBodies"); 163 MethodProtos = R->getValueAsCode("MethodProtos"); 164 165 std::vector<Record*> RegList = R->getValueAsListOfDefs("MemberList"); 166 for (unsigned i = 0, e = RegList.size(); i != e; ++i) { 167 Record *Reg = RegList[i]; 168 if (!Reg->isSubClassOf("Register")) 169 throw "Register Class member '" + Reg->getName() + 170 "' does not derive from the Register class!"; 171 Elements.push_back(Reg); 172 } 173 } 174 175 const std::string &CodeGenRegisterClass::getName() const { 176 return TheDef->getName(); 177 } 178 179 void CodeGenTarget::ReadLegalValueTypes() const { 180 const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses(); 181 for (unsigned i = 0, e = RCs.size(); i != e; ++i) 182 LegalValueTypes.push_back(RCs[i].VT); 183 184 // Remove duplicates. 185 std::sort(LegalValueTypes.begin(), LegalValueTypes.end()); 186 LegalValueTypes.erase(std::unique(LegalValueTypes.begin(), 187 LegalValueTypes.end()), 188 LegalValueTypes.end()); 189 } 190 191 192 void CodeGenTarget::ReadInstructions() const { 193 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction"); 194 195 if (Insts.empty()) 196 throw std::string("No 'Instruction' subclasses defined!"); 197 198 std::string InstFormatName = 199 getAsmWriter()->getValueAsString("InstFormatName"); 200 201 for (unsigned i = 0, e = Insts.size(); i != e; ++i) { 202 std::string AsmStr = Insts[i]->getValueAsString(InstFormatName); 203 Instructions.insert(std::make_pair(Insts[i]->getName(), 204 CodeGenInstruction(Insts[i], AsmStr))); 205 } 206 } 207 208 /// getPHIInstruction - Return the designated PHI instruction. 209 /// 210 const CodeGenInstruction &CodeGenTarget::getPHIInstruction() const { 211 Record *PHI = getInstructionSet()->getValueAsDef("PHIInst"); 212 std::map<std::string, CodeGenInstruction>::const_iterator I = 213 getInstructions().find(PHI->getName()); 214 if (I == Instructions.end()) 215 throw "Could not find PHI instruction named '" + PHI->getName() + "'!"; 216 return I->second; 217 } 218 219 /// getInstructionsByEnumValue - Return all of the instructions defined by the 220 /// target, ordered by their enum value. 221 void CodeGenTarget:: 222 getInstructionsByEnumValue(std::vector<const CodeGenInstruction*> 223 &NumberedInstructions) { 224 225 // Print out the rest of the instructions now. 226 unsigned i = 0; 227 const CodeGenInstruction *PHI = &getPHIInstruction(); 228 NumberedInstructions.push_back(PHI); 229 for (inst_iterator II = inst_begin(), E = inst_end(); II != E; ++II) 230 if (&II->second != PHI) 231 NumberedInstructions.push_back(&II->second); 232 } 233 234 235 /// isLittleEndianEncoding - Return whether this target encodes its instruction 236 /// in little-endian format, i.e. bits laid out in the order [0..n] 237 /// 238 bool CodeGenTarget::isLittleEndianEncoding() const { 239 return getInstructionSet()->getValueAsBit("isLittleEndianEncoding"); 240 } 241 242 CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr) 243 : TheDef(R), AsmString(AsmStr) { 244 Name = R->getValueAsString("Name"); 245 Namespace = R->getValueAsString("Namespace"); 246 247 isReturn = R->getValueAsBit("isReturn"); 248 isBranch = R->getValueAsBit("isBranch"); 249 isBarrier = R->getValueAsBit("isBarrier"); 250 isCall = R->getValueAsBit("isCall"); 251 isLoad = R->getValueAsBit("isLoad"); 252 isStore = R->getValueAsBit("isStore"); 253 isTwoAddress = R->getValueAsBit("isTwoAddress"); 254 isConvertibleToThreeAddress = R->getValueAsBit("isConvertibleToThreeAddress"); 255 isCommutable = R->getValueAsBit("isCommutable"); 256 isTerminator = R->getValueAsBit("isTerminator"); 257 hasDelaySlot = R->getValueAsBit("hasDelaySlot"); 258 usesCustomDAGSchedInserter = R->getValueAsBit("usesCustomDAGSchedInserter"); 259 hasVariableNumberOfOperands = false; 260 261 DagInit *DI; 262 try { 263 DI = R->getValueAsDag("OperandList"); 264 } catch (...) { 265 // Error getting operand list, just ignore it (sparcv9). 266 AsmString.clear(); 267 OperandList.clear(); 268 return; 269 } 270 271 unsigned MIOperandNo = 0; 272 std::set<std::string> OperandNames; 273 for (unsigned i = 0, e = DI->getNumArgs(); i != e; ++i) { 274 DefInit *Arg = dynamic_cast<DefInit*>(DI->getArg(i)); 275 if (!Arg) 276 throw "Illegal operand for the '" + R->getName() + "' instruction!"; 277 278 Record *Rec = Arg->getDef(); 279 std::string PrintMethod = "printOperand"; 280 unsigned NumOps = 1; 281 DagInit *MIOpInfo = 0; 282 if (Rec->isSubClassOf("Operand")) { 283 PrintMethod = Rec->getValueAsString("PrintMethod"); 284 NumOps = Rec->getValueAsInt("NumMIOperands"); 285 MIOpInfo = Rec->getValueAsDag("MIOperandInfo"); 286 } else if (Rec->getName() == "variable_ops") { 287 hasVariableNumberOfOperands = true; 288 continue; 289 } else if (!Rec->isSubClassOf("RegisterClass")) 290 throw "Unknown operand class '" + Rec->getName() + 291 "' in instruction '" + R->getName() + "' instruction!"; 292 293 // Check that the operand has a name and that it's unique. 294 if (DI->getArgName(i).empty()) 295 throw "In instruction '" + R->getName() + "', operand #" + utostr(i) + 296 " has no name!"; 297 if (!OperandNames.insert(DI->getArgName(i)).second) 298 throw "In instruction '" + R->getName() + "', operand #" + utostr(i) + 299 " has the same name as a previous operand!"; 300 301 OperandList.push_back(OperandInfo(Rec, DI->getArgName(i), PrintMethod, 302 MIOperandNo, NumOps, MIOpInfo)); 303 MIOperandNo += NumOps; 304 } 305 } 306 307 308 309 /// getOperandNamed - Return the index of the operand with the specified 310 /// non-empty name. If the instruction does not have an operand with the 311 /// specified name, throw an exception. 312 /// 313 unsigned CodeGenInstruction::getOperandNamed(const std::string &Name) const { 314 assert(!Name.empty() && "Cannot search for operand with no name!"); 315 for (unsigned i = 0, e = OperandList.size(); i != e; ++i) 316 if (OperandList[i].Name == Name) return i; 317 throw "Instruction '" + TheDef->getName() + 318 "' does not have an operand named '$" + Name + "'!"; 319 } 320