1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper ---------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This class wrap target description classes used by the various code
11 // generation TableGen backends.  This makes it easier to access the data and
12 // provides a single place that needs to check it for validity.  All of these
13 // classes throw exceptions on error conditions.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "CodeGenTarget.h"
18 #include "Record.h"
19 #include "llvm/ADT/StringExtras.h"
20 #include "llvm/Support/CommandLine.h"
21 #include <set>
22 #include <algorithm>
23 using namespace llvm;
24 
25 static cl::opt<unsigned>
26 AsmWriterNum("asmwriternum", cl::init(0),
27              cl::desc("Make -gen-asm-writer emit assembly writer #N"));
28 
29 /// getValueType - Return the MCV::ValueType that the specified TableGen record
30 /// corresponds to.
31 MVT::ValueType llvm::getValueType(Record *Rec) {
32   return (MVT::ValueType)Rec->getValueAsInt("Value");
33 }
34 
35 std::string llvm::getName(MVT::ValueType T) {
36   switch (T) {
37   case MVT::Other: return "UNKNOWN";
38   case MVT::i1:    return "i1";
39   case MVT::i8:    return "i8";
40   case MVT::i16:   return "i16";
41   case MVT::i32:   return "i32";
42   case MVT::i64:   return "i64";
43   case MVT::i128:  return "i128";
44   case MVT::f32:   return "f32";
45   case MVT::f64:   return "f64";
46   case MVT::f80:   return "f80";
47   case MVT::f128:  return "f128";
48   case MVT::Flag:  return "Flag";
49   case MVT::isVoid:return "void";
50   case MVT::v8i8:  return "v8i8";
51   case MVT::v4i16: return "v4i16";
52   case MVT::v2i32: return "v2i32";
53   case MVT::v16i8: return "v16i8";
54   case MVT::v8i16: return "v8i16";
55   case MVT::v4i32: return "v4i32";
56   case MVT::v2i64: return "v2i64";
57   case MVT::v2f32: return "v2f32";
58   case MVT::v4f32: return "v4f32";
59   case MVT::v2f64: return "v2f64";
60   default: assert(0 && "ILLEGAL VALUE TYPE!"); return "";
61   }
62 }
63 
64 std::string llvm::getEnumName(MVT::ValueType T) {
65   switch (T) {
66   case MVT::Other: return "Other";
67   case MVT::i1:    return "i1";
68   case MVT::i8:    return "i8";
69   case MVT::i16:   return "i16";
70   case MVT::i32:   return "i32";
71   case MVT::i64:   return "i64";
72   case MVT::i128:  return "i128";
73   case MVT::f32:   return "f32";
74   case MVT::f64:   return "f64";
75   case MVT::f80:   return "f80";
76   case MVT::f128:  return "f128";
77   case MVT::Flag:  return "Flag";
78   case MVT::isVoid:return "isVoid";
79   case MVT::v8i8:  return "v8i8";
80   case MVT::v4i16: return "v4i16";
81   case MVT::v2i32: return "v2i32";
82   case MVT::v16i8: return "v16i8";
83   case MVT::v8i16: return "v8i16";
84   case MVT::v4i32: return "v4i32";
85   case MVT::v2i64: return "v2i64";
86   case MVT::v2f32: return "v2f32";
87   case MVT::v4f32: return "v4f32";
88   case MVT::v2f64: return "v2f64";
89   default: assert(0 && "ILLEGAL VALUE TYPE!"); return "";
90   }
91 }
92 
93 
94 std::ostream &llvm::operator<<(std::ostream &OS, MVT::ValueType T) {
95   return OS << getName(T);
96 }
97 
98 
99 /// getTarget - Return the current instance of the Target class.
100 ///
101 CodeGenTarget::CodeGenTarget() : PointerType(MVT::Other) {
102   std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
103   if (Targets.size() == 0)
104     throw std::string("ERROR: No 'Target' subclasses defined!");
105   if (Targets.size() != 1)
106     throw std::string("ERROR: Multiple subclasses of Target defined!");
107   TargetRec = Targets[0];
108 
109   // Read in all of the CalleeSavedRegisters.
110   CalleeSavedRegisters =TargetRec->getValueAsListOfDefs("CalleeSavedRegisters");
111   PointerType = getValueType(TargetRec->getValueAsDef("PointerType"));
112 }
113 
114 
115 const std::string &CodeGenTarget::getName() const {
116   return TargetRec->getName();
117 }
118 
119 Record *CodeGenTarget::getInstructionSet() const {
120   return TargetRec->getValueAsDef("InstructionSet");
121 }
122 
123 /// getAsmWriter - Return the AssemblyWriter definition for this target.
124 ///
125 Record *CodeGenTarget::getAsmWriter() const {
126   std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters");
127   if (AsmWriterNum >= LI.size())
128     throw "Target does not have an AsmWriter #" + utostr(AsmWriterNum) + "!";
129   return LI[AsmWriterNum];
130 }
131 
132 void CodeGenTarget::ReadRegisters() const {
133   std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
134   if (Regs.empty())
135     throw std::string("No 'Register' subclasses defined!");
136 
137   Registers.reserve(Regs.size());
138   Registers.assign(Regs.begin(), Regs.end());
139 }
140 
141 CodeGenRegister::CodeGenRegister(Record *R) : TheDef(R) {
142   DeclaredSpillSize = R->getValueAsInt("SpillSize");
143   DeclaredSpillAlignment = R->getValueAsInt("SpillAlignment");
144 }
145 
146 const std::string &CodeGenRegister::getName() const {
147   return TheDef->getName();
148 }
149 
150 void CodeGenTarget::ReadRegisterClasses() const {
151   std::vector<Record*> RegClasses =
152     Records.getAllDerivedDefinitions("RegisterClass");
153   if (RegClasses.empty())
154     throw std::string("No 'RegisterClass' subclasses defined!");
155 
156   RegisterClasses.reserve(RegClasses.size());
157   RegisterClasses.assign(RegClasses.begin(), RegClasses.end());
158 }
159 
160 CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) {
161   // Rename anonymous register classes.
162   if (R->getName().size() > 9 && R->getName()[9] == '.') {
163     static unsigned AnonCounter = 0;
164     R->setName("AnonRegClass_"+utostr(AnonCounter++));
165   }
166 
167   std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
168   for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
169     Record *Type = TypeList[i];
170     if (!Type->isSubClassOf("ValueType"))
171       throw "RegTypes list member '" + Type->getName() +
172         "' does not derive from the ValueType class!";
173     VTs.push_back(getValueType(Type));
174   }
175   assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
176 
177   std::vector<Record*> RegList = R->getValueAsListOfDefs("MemberList");
178   for (unsigned i = 0, e = RegList.size(); i != e; ++i) {
179     Record *Reg = RegList[i];
180     if (!Reg->isSubClassOf("Register"))
181       throw "Register Class member '" + Reg->getName() +
182             "' does not derive from the Register class!";
183     Elements.push_back(Reg);
184   }
185 
186   // Allow targets to override the size in bits of the RegisterClass.
187   unsigned Size = R->getValueAsInt("Size");
188 
189   Namespace = R->getValueAsString("Namespace");
190   SpillSize = Size ? Size : MVT::getSizeInBits(VTs[0]);
191   SpillAlignment = R->getValueAsInt("Alignment");
192   MethodBodies = R->getValueAsCode("MethodBodies");
193   MethodProtos = R->getValueAsCode("MethodProtos");
194 }
195 
196 const std::string &CodeGenRegisterClass::getName() const {
197   return TheDef->getName();
198 }
199 
200 void CodeGenTarget::ReadLegalValueTypes() const {
201   const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
202   for (unsigned i = 0, e = RCs.size(); i != e; ++i)
203     for (unsigned ri = 0, re = RCs[i].VTs.size(); ri != re; ++ri)
204       LegalValueTypes.push_back(RCs[i].VTs[ri]);
205 
206   // Remove duplicates.
207   std::sort(LegalValueTypes.begin(), LegalValueTypes.end());
208   LegalValueTypes.erase(std::unique(LegalValueTypes.begin(),
209                                     LegalValueTypes.end()),
210                         LegalValueTypes.end());
211 }
212 
213 
214 void CodeGenTarget::ReadInstructions() const {
215   std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
216   if (Insts.size() <= 2)
217     throw std::string("No 'Instruction' subclasses defined!");
218 
219   // Parse the instructions defined in the .td file.
220   std::string InstFormatName =
221     getAsmWriter()->getValueAsString("InstFormatName");
222 
223   for (unsigned i = 0, e = Insts.size(); i != e; ++i) {
224     std::string AsmStr = Insts[i]->getValueAsString(InstFormatName);
225     Instructions.insert(std::make_pair(Insts[i]->getName(),
226                                        CodeGenInstruction(Insts[i], AsmStr)));
227   }
228 }
229 
230 /// getInstructionsByEnumValue - Return all of the instructions defined by the
231 /// target, ordered by their enum value.
232 void CodeGenTarget::
233 getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
234                                                  &NumberedInstructions) {
235   std::map<std::string, CodeGenInstruction>::const_iterator I;
236   I = getInstructions().find("PHI");
237   if (I == Instructions.end()) throw "Could not find 'PHI' instruction!";
238   const CodeGenInstruction *PHI = &I->second;
239 
240   I = getInstructions().find("INLINEASM");
241   if (I == Instructions.end()) throw "Could not find 'INLINEASM' instruction!";
242   const CodeGenInstruction *INLINEASM = &I->second;
243 
244   // Print out the rest of the instructions now.
245   NumberedInstructions.push_back(PHI);
246   NumberedInstructions.push_back(INLINEASM);
247   for (inst_iterator II = inst_begin(), E = inst_end(); II != E; ++II)
248     if (&II->second != PHI &&&II->second != INLINEASM)
249       NumberedInstructions.push_back(&II->second);
250 }
251 
252 
253 /// isLittleEndianEncoding - Return whether this target encodes its instruction
254 /// in little-endian format, i.e. bits laid out in the order [0..n]
255 ///
256 bool CodeGenTarget::isLittleEndianEncoding() const {
257   return getInstructionSet()->getValueAsBit("isLittleEndianEncoding");
258 }
259 
260 CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
261   : TheDef(R), AsmString(AsmStr) {
262   Name      = R->getValueAsString("Name");
263   Namespace = R->getValueAsString("Namespace");
264 
265   isReturn     = R->getValueAsBit("isReturn");
266   isBranch     = R->getValueAsBit("isBranch");
267   isBarrier    = R->getValueAsBit("isBarrier");
268   isCall       = R->getValueAsBit("isCall");
269   isLoad       = R->getValueAsBit("isLoad");
270   isStore      = R->getValueAsBit("isStore");
271   isTwoAddress = R->getValueAsBit("isTwoAddress");
272   isConvertibleToThreeAddress = R->getValueAsBit("isConvertibleToThreeAddress");
273   isCommutable = R->getValueAsBit("isCommutable");
274   isTerminator = R->getValueAsBit("isTerminator");
275   hasDelaySlot = R->getValueAsBit("hasDelaySlot");
276   usesCustomDAGSchedInserter = R->getValueAsBit("usesCustomDAGSchedInserter");
277   hasCtrlDep   = R->getValueAsBit("hasCtrlDep");
278   noResults    = R->getValueAsBit("noResults");
279   hasVariableNumberOfOperands = false;
280 
281   DagInit *DI;
282   try {
283     DI = R->getValueAsDag("OperandList");
284   } catch (...) {
285     // Error getting operand list, just ignore it (sparcv9).
286     AsmString.clear();
287     OperandList.clear();
288     return;
289   }
290 
291   unsigned MIOperandNo = 0;
292   std::set<std::string> OperandNames;
293   for (unsigned i = 0, e = DI->getNumArgs(); i != e; ++i) {
294     DefInit *Arg = dynamic_cast<DefInit*>(DI->getArg(i));
295     if (!Arg)
296       throw "Illegal operand for the '" + R->getName() + "' instruction!";
297 
298     Record *Rec = Arg->getDef();
299     std::string PrintMethod = "printOperand";
300     unsigned NumOps = 1;
301     DagInit *MIOpInfo = 0;
302     if (Rec->isSubClassOf("Operand")) {
303       PrintMethod = Rec->getValueAsString("PrintMethod");
304       NumOps = Rec->getValueAsInt("NumMIOperands");
305       MIOpInfo = Rec->getValueAsDag("MIOperandInfo");
306     } else if (Rec->getName() == "variable_ops") {
307       hasVariableNumberOfOperands = true;
308       continue;
309     } else if (!Rec->isSubClassOf("RegisterClass"))
310       throw "Unknown operand class '" + Rec->getName() +
311             "' in instruction '" + R->getName() + "' instruction!";
312 
313     // Check that the operand has a name and that it's unique.
314     if (DI->getArgName(i).empty())
315       throw "In instruction '" + R->getName() + "', operand #" + utostr(i) +
316         " has no name!";
317     if (!OperandNames.insert(DI->getArgName(i)).second)
318       throw "In instruction '" + R->getName() + "', operand #" + utostr(i) +
319         " has the same name as a previous operand!";
320 
321     OperandList.push_back(OperandInfo(Rec, DI->getArgName(i), PrintMethod,
322                                       MIOperandNo, NumOps, MIOpInfo));
323     MIOperandNo += NumOps;
324   }
325 }
326 
327 
328 
329 /// getOperandNamed - Return the index of the operand with the specified
330 /// non-empty name.  If the instruction does not have an operand with the
331 /// specified name, throw an exception.
332 ///
333 unsigned CodeGenInstruction::getOperandNamed(const std::string &Name) const {
334   assert(!Name.empty() && "Cannot search for operand with no name!");
335   for (unsigned i = 0, e = OperandList.size(); i != e; ++i)
336     if (OperandList[i].Name == Name) return i;
337   throw "Instruction '" + TheDef->getName() +
338         "' does not have an operand named '$" + Name + "'!";
339 }
340 
341 //===----------------------------------------------------------------------===//
342 // ComplexPattern implementation
343 //
344 ComplexPattern::ComplexPattern(Record *R) {
345   Ty          = ::getValueType(R->getValueAsDef("Ty"));
346   NumOperands = R->getValueAsInt("NumOperands");
347   SelectFunc  = R->getValueAsString("SelectFunc");
348   RootNodes   = R->getValueAsListOfDefs("RootNodes");
349 }
350 
351