1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper ---------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This class wrap target description classes used by the various code
11 // generation TableGen backends.  This makes it easier to access the data and
12 // provides a single place that needs to check it for validity.  All of these
13 // classes throw exceptions on error conditions.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "CodeGenTarget.h"
18 #include "Record.h"
19 #include "llvm/ADT/StringExtras.h"
20 #include "llvm/Support/CommandLine.h"
21 #include <set>
22 #include <algorithm>
23 using namespace llvm;
24 
25 static cl::opt<unsigned>
26 AsmWriterNum("asmwriternum", cl::init(0),
27              cl::desc("Make -gen-asm-writer emit assembly writer #N"));
28 
29 /// getValueType - Return the MCV::ValueType that the specified TableGen record
30 /// corresponds to.
31 MVT::ValueType llvm::getValueType(Record *Rec) {
32   return (MVT::ValueType)Rec->getValueAsInt("Value");
33 }
34 
35 std::string llvm::getName(MVT::ValueType T) {
36   switch (T) {
37   case MVT::Other: return "UNKNOWN";
38   case MVT::i1:    return "i1";
39   case MVT::i8:    return "i8";
40   case MVT::i16:   return "i16";
41   case MVT::i32:   return "i32";
42   case MVT::i64:   return "i64";
43   case MVT::i128:  return "i128";
44   case MVT::f32:   return "f32";
45   case MVT::f64:   return "f64";
46   case MVT::f80:   return "f80";
47   case MVT::f128:  return "f128";
48   case MVT::isVoid:return "void";
49   case MVT::v16i8: return "v16i8";
50   case MVT::v8i16: return "v8i16";
51   case MVT::v4i32: return "v4i32";
52   case MVT::v2i64: return "v2i64";
53   case MVT::v4f32: return "v4f32";
54   case MVT::v2f64: return "v2f64";
55   default: assert(0 && "ILLEGAL VALUE TYPE!"); return "";
56   }
57 }
58 
59 std::string llvm::getEnumName(MVT::ValueType T) {
60   switch (T) {
61   case MVT::Other: return "Other";
62   case MVT::i1:    return "i1";
63   case MVT::i8:    return "i8";
64   case MVT::i16:   return "i16";
65   case MVT::i32:   return "i32";
66   case MVT::i64:   return "i64";
67   case MVT::i128:  return "i128";
68   case MVT::f32:   return "f32";
69   case MVT::f64:   return "f64";
70   case MVT::f80:   return "f80";
71   case MVT::f128:  return "f128";
72   case MVT::isVoid:return "isVoid";
73   case MVT::v16i8: return "v16i8";
74   case MVT::v8i16: return "v8i16";
75   case MVT::v4i32: return "v4i32";
76   case MVT::v2i64: return "v2i64";
77   case MVT::v4f32: return "v4f32";
78   case MVT::v2f64: return "v2f64";
79   default: assert(0 && "ILLEGAL VALUE TYPE!"); return "";
80   }
81 }
82 
83 
84 std::ostream &llvm::operator<<(std::ostream &OS, MVT::ValueType T) {
85   return OS << getName(T);
86 }
87 
88 
89 /// getTarget - Return the current instance of the Target class.
90 ///
91 CodeGenTarget::CodeGenTarget() : PointerType(MVT::Other) {
92   std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
93   if (Targets.size() == 0)
94     throw std::string("ERROR: No 'Target' subclasses defined!");
95   if (Targets.size() != 1)
96     throw std::string("ERROR: Multiple subclasses of Target defined!");
97   TargetRec = Targets[0];
98 
99   // Read in all of the CalleeSavedRegisters.
100   CalleeSavedRegisters =TargetRec->getValueAsListOfDefs("CalleeSavedRegisters");
101   PointerType = getValueType(TargetRec->getValueAsDef("PointerType"));
102 }
103 
104 
105 const std::string &CodeGenTarget::getName() const {
106   return TargetRec->getName();
107 }
108 
109 Record *CodeGenTarget::getInstructionSet() const {
110   return TargetRec->getValueAsDef("InstructionSet");
111 }
112 
113 /// getAsmWriter - Return the AssemblyWriter definition for this target.
114 ///
115 Record *CodeGenTarget::getAsmWriter() const {
116   std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters");
117   if (AsmWriterNum >= LI.size())
118     throw "Target does not have an AsmWriter #" + utostr(AsmWriterNum) + "!";
119   return LI[AsmWriterNum];
120 }
121 
122 void CodeGenTarget::ReadRegisters() const {
123   std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
124   if (Regs.empty())
125     throw std::string("No 'Register' subclasses defined!");
126 
127   Registers.reserve(Regs.size());
128   Registers.assign(Regs.begin(), Regs.end());
129 }
130 
131 CodeGenRegister::CodeGenRegister(Record *R) : TheDef(R) {
132   DeclaredSpillSize = R->getValueAsInt("SpillSize");
133   DeclaredSpillAlignment = R->getValueAsInt("SpillAlignment");
134 }
135 
136 const std::string &CodeGenRegister::getName() const {
137   return TheDef->getName();
138 }
139 
140 void CodeGenTarget::ReadRegisterClasses() const {
141   std::vector<Record*> RegClasses =
142     Records.getAllDerivedDefinitions("RegisterClass");
143   if (RegClasses.empty())
144     throw std::string("No 'RegisterClass' subclasses defined!");
145 
146   RegisterClasses.reserve(RegClasses.size());
147   RegisterClasses.assign(RegClasses.begin(), RegClasses.end());
148 }
149 
150 CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) {
151   // Rename anonymous register classes.
152   if (R->getName().size() > 9 && R->getName()[9] == '.') {
153     static unsigned AnonCounter = 0;
154     R->setName("AnonRegClass_"+utostr(AnonCounter++));
155   }
156 
157   std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
158   for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
159     Record *Type = TypeList[i];
160     if (!Type->isSubClassOf("ValueType"))
161       throw "RegTypes list member '" + Type->getName() +
162         "' does not derive from the ValueType class!";
163     VTs.push_back(getValueType(Type));
164   }
165   assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
166 
167   std::vector<Record*> RegList = R->getValueAsListOfDefs("MemberList");
168   for (unsigned i = 0, e = RegList.size(); i != e; ++i) {
169     Record *Reg = RegList[i];
170     if (!Reg->isSubClassOf("Register"))
171       throw "Register Class member '" + Reg->getName() +
172             "' does not derive from the Register class!";
173     Elements.push_back(Reg);
174   }
175 
176   // Allow targets to override the size in bits of the RegisterClass.
177   unsigned Size = R->getValueAsInt("Size");
178 
179   Namespace = R->getValueAsString("Namespace");
180   SpillSize = Size ? Size : MVT::getSizeInBits(VTs[0]);
181   SpillAlignment = R->getValueAsInt("Alignment");
182   MethodBodies = R->getValueAsCode("MethodBodies");
183   MethodProtos = R->getValueAsCode("MethodProtos");
184 }
185 
186 const std::string &CodeGenRegisterClass::getName() const {
187   return TheDef->getName();
188 }
189 
190 void CodeGenTarget::ReadLegalValueTypes() const {
191   const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
192   for (unsigned i = 0, e = RCs.size(); i != e; ++i)
193     for (unsigned ri = 0, re = RCs[i].VTs.size(); ri != re; ++ri)
194       LegalValueTypes.push_back(RCs[i].VTs[ri]);
195 
196   // Remove duplicates.
197   std::sort(LegalValueTypes.begin(), LegalValueTypes.end());
198   LegalValueTypes.erase(std::unique(LegalValueTypes.begin(),
199                                     LegalValueTypes.end()),
200                         LegalValueTypes.end());
201 }
202 
203 
204 void CodeGenTarget::ReadInstructions() const {
205   std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
206 
207   if (Insts.empty())
208     throw std::string("No 'Instruction' subclasses defined!");
209 
210   std::string InstFormatName =
211     getAsmWriter()->getValueAsString("InstFormatName");
212 
213   for (unsigned i = 0, e = Insts.size(); i != e; ++i) {
214     std::string AsmStr = Insts[i]->getValueAsString(InstFormatName);
215     Instructions.insert(std::make_pair(Insts[i]->getName(),
216                                        CodeGenInstruction(Insts[i], AsmStr)));
217   }
218 }
219 
220 /// getPHIInstruction - Return the designated PHI instruction.
221 ///
222 const CodeGenInstruction &CodeGenTarget::getPHIInstruction() const {
223   Record *PHI = getInstructionSet()->getValueAsDef("PHIInst");
224   std::map<std::string, CodeGenInstruction>::const_iterator I =
225     getInstructions().find(PHI->getName());
226   if (I == Instructions.end())
227     throw "Could not find PHI instruction named '" + PHI->getName() + "'!";
228   return I->second;
229 }
230 
231 /// getInstructionsByEnumValue - Return all of the instructions defined by the
232 /// target, ordered by their enum value.
233 void CodeGenTarget::
234 getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
235                                                  &NumberedInstructions) {
236 
237   // Print out the rest of the instructions now.
238   unsigned i = 0;
239   const CodeGenInstruction *PHI = &getPHIInstruction();
240   NumberedInstructions.push_back(PHI);
241   for (inst_iterator II = inst_begin(), E = inst_end(); II != E; ++II)
242     if (&II->second != PHI)
243       NumberedInstructions.push_back(&II->second);
244 }
245 
246 
247 /// isLittleEndianEncoding - Return whether this target encodes its instruction
248 /// in little-endian format, i.e. bits laid out in the order [0..n]
249 ///
250 bool CodeGenTarget::isLittleEndianEncoding() const {
251   return getInstructionSet()->getValueAsBit("isLittleEndianEncoding");
252 }
253 
254 CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
255   : TheDef(R), AsmString(AsmStr) {
256   Name      = R->getValueAsString("Name");
257   Namespace = R->getValueAsString("Namespace");
258 
259   isReturn     = R->getValueAsBit("isReturn");
260   isBranch     = R->getValueAsBit("isBranch");
261   isBarrier    = R->getValueAsBit("isBarrier");
262   isCall       = R->getValueAsBit("isCall");
263   isLoad       = R->getValueAsBit("isLoad");
264   isStore      = R->getValueAsBit("isStore");
265   isTwoAddress = R->getValueAsBit("isTwoAddress");
266   isConvertibleToThreeAddress = R->getValueAsBit("isConvertibleToThreeAddress");
267   isCommutable = R->getValueAsBit("isCommutable");
268   isTerminator = R->getValueAsBit("isTerminator");
269   hasDelaySlot = R->getValueAsBit("hasDelaySlot");
270   usesCustomDAGSchedInserter = R->getValueAsBit("usesCustomDAGSchedInserter");
271   hasCtrlDep   = R->getValueAsBit("hasCtrlDep");
272   hasVariableNumberOfOperands = false;
273 
274   DagInit *DI;
275   try {
276     DI = R->getValueAsDag("OperandList");
277   } catch (...) {
278     // Error getting operand list, just ignore it (sparcv9).
279     AsmString.clear();
280     OperandList.clear();
281     return;
282   }
283 
284   unsigned MIOperandNo = 0;
285   std::set<std::string> OperandNames;
286   for (unsigned i = 0, e = DI->getNumArgs(); i != e; ++i) {
287     DefInit *Arg = dynamic_cast<DefInit*>(DI->getArg(i));
288     if (!Arg)
289       throw "Illegal operand for the '" + R->getName() + "' instruction!";
290 
291     Record *Rec = Arg->getDef();
292     std::string PrintMethod = "printOperand";
293     unsigned NumOps = 1;
294     DagInit *MIOpInfo = 0;
295     if (Rec->isSubClassOf("Operand")) {
296       PrintMethod = Rec->getValueAsString("PrintMethod");
297       NumOps = Rec->getValueAsInt("NumMIOperands");
298       MIOpInfo = Rec->getValueAsDag("MIOperandInfo");
299     } else if (Rec->getName() == "variable_ops") {
300       hasVariableNumberOfOperands = true;
301       continue;
302     } else if (!Rec->isSubClassOf("RegisterClass"))
303       throw "Unknown operand class '" + Rec->getName() +
304             "' in instruction '" + R->getName() + "' instruction!";
305 
306     // Check that the operand has a name and that it's unique.
307     if (DI->getArgName(i).empty())
308       throw "In instruction '" + R->getName() + "', operand #" + utostr(i) +
309         " has no name!";
310     if (!OperandNames.insert(DI->getArgName(i)).second)
311       throw "In instruction '" + R->getName() + "', operand #" + utostr(i) +
312         " has the same name as a previous operand!";
313 
314     OperandList.push_back(OperandInfo(Rec, DI->getArgName(i), PrintMethod,
315                                       MIOperandNo, NumOps, MIOpInfo));
316     MIOperandNo += NumOps;
317   }
318 }
319 
320 
321 
322 /// getOperandNamed - Return the index of the operand with the specified
323 /// non-empty name.  If the instruction does not have an operand with the
324 /// specified name, throw an exception.
325 ///
326 unsigned CodeGenInstruction::getOperandNamed(const std::string &Name) const {
327   assert(!Name.empty() && "Cannot search for operand with no name!");
328   for (unsigned i = 0, e = OperandList.size(); i != e; ++i)
329     if (OperandList[i].Name == Name) return i;
330   throw "Instruction '" + TheDef->getName() +
331         "' does not have an operand named '$" + Name + "'!";
332 }
333