1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This class wraps target description classes used by the various code 11 // generation TableGen backends. This makes it easier to access the data and 12 // provides a single place that needs to check it for validity. All of these 13 // classes throw exceptions on error conditions. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "CodeGenTarget.h" 18 #include "CodeGenIntrinsics.h" 19 #include "Record.h" 20 #include "llvm/ADT/StringExtras.h" 21 #include "llvm/ADT/STLExtras.h" 22 #include "llvm/Support/CommandLine.h" 23 #include <algorithm> 24 using namespace llvm; 25 26 static cl::opt<unsigned> 27 AsmParserNum("asmparsernum", cl::init(0), 28 cl::desc("Make -gen-asm-parser emit assembly parser #N")); 29 30 static cl::opt<unsigned> 31 AsmWriterNum("asmwriternum", cl::init(0), 32 cl::desc("Make -gen-asm-writer emit assembly writer #N")); 33 34 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen 35 /// record corresponds to. 36 MVT::SimpleValueType llvm::getValueType(Record *Rec) { 37 return (MVT::SimpleValueType)Rec->getValueAsInt("Value"); 38 } 39 40 std::string llvm::getName(MVT::SimpleValueType T) { 41 switch (T) { 42 case MVT::Other: return "UNKNOWN"; 43 case MVT::iPTR: return "TLI.getPointerTy()"; 44 case MVT::iPTRAny: return "TLI.getPointerTy()"; 45 default: return getEnumName(T); 46 } 47 } 48 49 std::string llvm::getEnumName(MVT::SimpleValueType T) { 50 switch (T) { 51 case MVT::Other: return "MVT::Other"; 52 case MVT::i1: return "MVT::i1"; 53 case MVT::i8: return "MVT::i8"; 54 case MVT::i16: return "MVT::i16"; 55 case MVT::i32: return "MVT::i32"; 56 case MVT::i64: return "MVT::i64"; 57 case MVT::i128: return "MVT::i128"; 58 case MVT::iAny: return "MVT::iAny"; 59 case MVT::fAny: return "MVT::fAny"; 60 case MVT::vAny: return "MVT::vAny"; 61 case MVT::f32: return "MVT::f32"; 62 case MVT::f64: return "MVT::f64"; 63 case MVT::f80: return "MVT::f80"; 64 case MVT::f128: return "MVT::f128"; 65 case MVT::ppcf128: return "MVT::ppcf128"; 66 case MVT::x86mmx: return "MVT::x86mmx"; 67 case MVT::Glue: return "MVT::Glue"; 68 case MVT::isVoid: return "MVT::isVoid"; 69 case MVT::v2i8: return "MVT::v2i8"; 70 case MVT::v4i8: return "MVT::v4i8"; 71 case MVT::v8i8: return "MVT::v8i8"; 72 case MVT::v16i8: return "MVT::v16i8"; 73 case MVT::v32i8: return "MVT::v32i8"; 74 case MVT::v2i16: return "MVT::v2i16"; 75 case MVT::v4i16: return "MVT::v4i16"; 76 case MVT::v8i16: return "MVT::v8i16"; 77 case MVT::v16i16: return "MVT::v16i16"; 78 case MVT::v2i32: return "MVT::v2i32"; 79 case MVT::v4i32: return "MVT::v4i32"; 80 case MVT::v8i32: return "MVT::v8i32"; 81 case MVT::v1i64: return "MVT::v1i64"; 82 case MVT::v2i64: return "MVT::v2i64"; 83 case MVT::v4i64: return "MVT::v4i64"; 84 case MVT::v8i64: return "MVT::v8i64"; 85 case MVT::v2f32: return "MVT::v2f32"; 86 case MVT::v4f32: return "MVT::v4f32"; 87 case MVT::v8f32: return "MVT::v8f32"; 88 case MVT::v2f64: return "MVT::v2f64"; 89 case MVT::v4f64: return "MVT::v4f64"; 90 case MVT::Metadata: return "MVT::Metadata"; 91 case MVT::iPTR: return "MVT::iPTR"; 92 case MVT::iPTRAny: return "MVT::iPTRAny"; 93 default: assert(0 && "ILLEGAL VALUE TYPE!"); return ""; 94 } 95 } 96 97 /// getQualifiedName - Return the name of the specified record, with a 98 /// namespace qualifier if the record contains one. 99 /// 100 std::string llvm::getQualifiedName(const Record *R) { 101 std::string Namespace = R->getValueAsString("Namespace"); 102 if (Namespace.empty()) return R->getName(); 103 return Namespace + "::" + R->getName(); 104 } 105 106 107 108 109 /// getTarget - Return the current instance of the Target class. 110 /// 111 CodeGenTarget::CodeGenTarget(RecordKeeper &records) : Records(records) { 112 std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target"); 113 if (Targets.size() == 0) 114 throw std::string("ERROR: No 'Target' subclasses defined!"); 115 if (Targets.size() != 1) 116 throw std::string("ERROR: Multiple subclasses of Target defined!"); 117 TargetRec = Targets[0]; 118 } 119 120 121 const std::string &CodeGenTarget::getName() const { 122 return TargetRec->getName(); 123 } 124 125 std::string CodeGenTarget::getInstNamespace() const { 126 for (inst_iterator i = inst_begin(), e = inst_end(); i != e; ++i) { 127 // Make sure not to pick up "TargetOpcode" by accidentally getting 128 // the namespace off the PHI instruction or something. 129 if ((*i)->Namespace != "TargetOpcode") 130 return (*i)->Namespace; 131 } 132 133 return ""; 134 } 135 136 Record *CodeGenTarget::getInstructionSet() const { 137 return TargetRec->getValueAsDef("InstructionSet"); 138 } 139 140 141 /// getAsmParser - Return the AssemblyParser definition for this target. 142 /// 143 Record *CodeGenTarget::getAsmParser() const { 144 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers"); 145 if (AsmParserNum >= LI.size()) 146 throw "Target does not have an AsmParser #" + utostr(AsmParserNum) + "!"; 147 return LI[AsmParserNum]; 148 } 149 150 /// getAsmWriter - Return the AssemblyWriter definition for this target. 151 /// 152 Record *CodeGenTarget::getAsmWriter() const { 153 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters"); 154 if (AsmWriterNum >= LI.size()) 155 throw "Target does not have an AsmWriter #" + utostr(AsmWriterNum) + "!"; 156 return LI[AsmWriterNum]; 157 } 158 159 void CodeGenTarget::ReadRegisters() const { 160 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); 161 if (Regs.empty()) 162 throw std::string("No 'Register' subclasses defined!"); 163 std::sort(Regs.begin(), Regs.end(), LessRecord()); 164 165 Registers.reserve(Regs.size()); 166 Registers.assign(Regs.begin(), Regs.end()); 167 // Assign the enumeration values. 168 for (unsigned i = 0, e = Registers.size(); i != e; ++i) 169 Registers[i].EnumValue = i + 1; 170 } 171 172 CodeGenRegister::CodeGenRegister(Record *R) : TheDef(R) { 173 DeclaredSpillSize = R->getValueAsInt("SpillSize"); 174 DeclaredSpillAlignment = R->getValueAsInt("SpillAlignment"); 175 } 176 177 const std::string &CodeGenRegister::getName() const { 178 return TheDef->getName(); 179 } 180 181 void CodeGenTarget::ReadSubRegIndices() const { 182 SubRegIndices = Records.getAllDerivedDefinitions("SubRegIndex"); 183 std::sort(SubRegIndices.begin(), SubRegIndices.end(), LessRecord()); 184 } 185 186 void CodeGenTarget::ReadRegisterClasses() const { 187 std::vector<Record*> RegClasses = 188 Records.getAllDerivedDefinitions("RegisterClass"); 189 if (RegClasses.empty()) 190 throw std::string("No 'RegisterClass' subclasses defined!"); 191 192 RegisterClasses.reserve(RegClasses.size()); 193 RegisterClasses.assign(RegClasses.begin(), RegClasses.end()); 194 } 195 196 /// getRegisterByName - If there is a register with the specific AsmName, 197 /// return it. 198 const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const { 199 const std::vector<CodeGenRegister> &Regs = getRegisters(); 200 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 201 const CodeGenRegister &Reg = Regs[i]; 202 if (Reg.TheDef->getValueAsString("AsmName") == Name) 203 return &Reg; 204 } 205 206 return 0; 207 } 208 209 std::vector<MVT::SimpleValueType> CodeGenTarget:: 210 getRegisterVTs(Record *R) const { 211 std::vector<MVT::SimpleValueType> Result; 212 const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses(); 213 for (unsigned i = 0, e = RCs.size(); i != e; ++i) { 214 const CodeGenRegisterClass &RC = RegisterClasses[i]; 215 for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) { 216 if (R == RC.Elements[ei]) { 217 const std::vector<MVT::SimpleValueType> &InVTs = RC.getValueTypes(); 218 Result.insert(Result.end(), InVTs.begin(), InVTs.end()); 219 } 220 } 221 } 222 223 // Remove duplicates. 224 array_pod_sort(Result.begin(), Result.end()); 225 Result.erase(std::unique(Result.begin(), Result.end()), Result.end()); 226 return Result; 227 } 228 229 230 CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) { 231 // Rename anonymous register classes. 232 if (R->getName().size() > 9 && R->getName()[9] == '.') { 233 static unsigned AnonCounter = 0; 234 R->setName("AnonRegClass_"+utostr(AnonCounter++)); 235 } 236 237 std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes"); 238 for (unsigned i = 0, e = TypeList.size(); i != e; ++i) { 239 Record *Type = TypeList[i]; 240 if (!Type->isSubClassOf("ValueType")) 241 throw "RegTypes list member '" + Type->getName() + 242 "' does not derive from the ValueType class!"; 243 VTs.push_back(getValueType(Type)); 244 } 245 assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!"); 246 247 std::vector<Record*> RegList = R->getValueAsListOfDefs("MemberList"); 248 for (unsigned i = 0, e = RegList.size(); i != e; ++i) { 249 Record *Reg = RegList[i]; 250 if (!Reg->isSubClassOf("Register")) 251 throw "Register Class member '" + Reg->getName() + 252 "' does not derive from the Register class!"; 253 Elements.push_back(Reg); 254 } 255 256 // SubRegClasses is a list<dag> containing (RC, subregindex, ...) dags. 257 ListInit *SRC = R->getValueAsListInit("SubRegClasses"); 258 for (ListInit::const_iterator i = SRC->begin(), e = SRC->end(); i != e; ++i) { 259 DagInit *DAG = dynamic_cast<DagInit*>(*i); 260 if (!DAG) throw "SubRegClasses must contain DAGs"; 261 DefInit *DAGOp = dynamic_cast<DefInit*>(DAG->getOperator()); 262 Record *RCRec; 263 if (!DAGOp || !(RCRec = DAGOp->getDef())->isSubClassOf("RegisterClass")) 264 throw "Operator '" + DAG->getOperator()->getAsString() + 265 "' in SubRegClasses is not a RegisterClass"; 266 // Iterate over args, all SubRegIndex instances. 267 for (DagInit::const_arg_iterator ai = DAG->arg_begin(), ae = DAG->arg_end(); 268 ai != ae; ++ai) { 269 DefInit *Idx = dynamic_cast<DefInit*>(*ai); 270 Record *IdxRec; 271 if (!Idx || !(IdxRec = Idx->getDef())->isSubClassOf("SubRegIndex")) 272 throw "Argument '" + (*ai)->getAsString() + 273 "' in SubRegClasses is not a SubRegIndex"; 274 if (!SubRegClasses.insert(std::make_pair(IdxRec, RCRec)).second) 275 throw "SubRegIndex '" + IdxRec->getName() + "' mentioned twice"; 276 } 277 } 278 279 // Allow targets to override the size in bits of the RegisterClass. 280 unsigned Size = R->getValueAsInt("Size"); 281 282 Namespace = R->getValueAsString("Namespace"); 283 SpillSize = Size ? Size : EVT(VTs[0]).getSizeInBits(); 284 SpillAlignment = R->getValueAsInt("Alignment"); 285 CopyCost = R->getValueAsInt("CopyCost"); 286 MethodBodies = R->getValueAsCode("MethodBodies"); 287 MethodProtos = R->getValueAsCode("MethodProtos"); 288 } 289 290 const std::string &CodeGenRegisterClass::getName() const { 291 return TheDef->getName(); 292 } 293 294 void CodeGenTarget::ReadLegalValueTypes() const { 295 const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses(); 296 for (unsigned i = 0, e = RCs.size(); i != e; ++i) 297 for (unsigned ri = 0, re = RCs[i].VTs.size(); ri != re; ++ri) 298 LegalValueTypes.push_back(RCs[i].VTs[ri]); 299 300 // Remove duplicates. 301 std::sort(LegalValueTypes.begin(), LegalValueTypes.end()); 302 LegalValueTypes.erase(std::unique(LegalValueTypes.begin(), 303 LegalValueTypes.end()), 304 LegalValueTypes.end()); 305 } 306 307 308 void CodeGenTarget::ReadInstructions() const { 309 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction"); 310 if (Insts.size() <= 2) 311 throw std::string("No 'Instruction' subclasses defined!"); 312 313 // Parse the instructions defined in the .td file. 314 for (unsigned i = 0, e = Insts.size(); i != e; ++i) 315 Instructions[Insts[i]] = new CodeGenInstruction(Insts[i]); 316 } 317 318 static const CodeGenInstruction * 319 GetInstByName(const char *Name, 320 const DenseMap<const Record*, CodeGenInstruction*> &Insts, 321 RecordKeeper &Records) { 322 const Record *Rec = Records.getDef(Name); 323 324 DenseMap<const Record*, CodeGenInstruction*>::const_iterator 325 I = Insts.find(Rec); 326 if (Rec == 0 || I == Insts.end()) 327 throw std::string("Could not find '") + Name + "' instruction!"; 328 return I->second; 329 } 330 331 namespace { 332 /// SortInstByName - Sorting predicate to sort instructions by name. 333 /// 334 struct SortInstByName { 335 bool operator()(const CodeGenInstruction *Rec1, 336 const CodeGenInstruction *Rec2) const { 337 return Rec1->TheDef->getName() < Rec2->TheDef->getName(); 338 } 339 }; 340 } 341 342 /// getInstructionsByEnumValue - Return all of the instructions defined by the 343 /// target, ordered by their enum value. 344 void CodeGenTarget::ComputeInstrsByEnum() const { 345 // The ordering here must match the ordering in TargetOpcodes.h. 346 const char *const FixedInstrs[] = { 347 "PHI", 348 "INLINEASM", 349 "PROLOG_LABEL", 350 "EH_LABEL", 351 "GC_LABEL", 352 "KILL", 353 "EXTRACT_SUBREG", 354 "INSERT_SUBREG", 355 "IMPLICIT_DEF", 356 "SUBREG_TO_REG", 357 "COPY_TO_REGCLASS", 358 "DBG_VALUE", 359 "REG_SEQUENCE", 360 "COPY", 361 0 362 }; 363 const DenseMap<const Record*, CodeGenInstruction*> &Insts = getInstructions(); 364 for (const char *const *p = FixedInstrs; *p; ++p) { 365 const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records); 366 assert(Instr && "Missing target independent instruction"); 367 assert(Instr->Namespace == "TargetOpcode" && "Bad namespace"); 368 InstrsByEnum.push_back(Instr); 369 } 370 unsigned EndOfPredefines = InstrsByEnum.size(); 371 372 for (DenseMap<const Record*, CodeGenInstruction*>::const_iterator 373 I = Insts.begin(), E = Insts.end(); I != E; ++I) { 374 const CodeGenInstruction *CGI = I->second; 375 if (CGI->Namespace != "TargetOpcode") 376 InstrsByEnum.push_back(CGI); 377 } 378 379 assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr"); 380 381 // All of the instructions are now in random order based on the map iteration. 382 // Sort them by name. 383 std::sort(InstrsByEnum.begin()+EndOfPredefines, InstrsByEnum.end(), 384 SortInstByName()); 385 } 386 387 388 /// isLittleEndianEncoding - Return whether this target encodes its instruction 389 /// in little-endian format, i.e. bits laid out in the order [0..n] 390 /// 391 bool CodeGenTarget::isLittleEndianEncoding() const { 392 return getInstructionSet()->getValueAsBit("isLittleEndianEncoding"); 393 } 394 395 //===----------------------------------------------------------------------===// 396 // ComplexPattern implementation 397 // 398 ComplexPattern::ComplexPattern(Record *R) { 399 Ty = ::getValueType(R->getValueAsDef("Ty")); 400 NumOperands = R->getValueAsInt("NumOperands"); 401 SelectFunc = R->getValueAsString("SelectFunc"); 402 RootNodes = R->getValueAsListOfDefs("RootNodes"); 403 404 // Parse the properties. 405 Properties = 0; 406 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties"); 407 for (unsigned i = 0, e = PropList.size(); i != e; ++i) 408 if (PropList[i]->getName() == "SDNPHasChain") { 409 Properties |= 1 << SDNPHasChain; 410 } else if (PropList[i]->getName() == "SDNPOptInGlue") { 411 Properties |= 1 << SDNPOptInGlue; 412 } else if (PropList[i]->getName() == "SDNPMayStore") { 413 Properties |= 1 << SDNPMayStore; 414 } else if (PropList[i]->getName() == "SDNPMayLoad") { 415 Properties |= 1 << SDNPMayLoad; 416 } else if (PropList[i]->getName() == "SDNPSideEffect") { 417 Properties |= 1 << SDNPSideEffect; 418 } else if (PropList[i]->getName() == "SDNPMemOperand") { 419 Properties |= 1 << SDNPMemOperand; 420 } else if (PropList[i]->getName() == "SDNPVariadic") { 421 Properties |= 1 << SDNPVariadic; 422 } else if (PropList[i]->getName() == "SDNPWantRoot") { 423 Properties |= 1 << SDNPWantRoot; 424 } else if (PropList[i]->getName() == "SDNPWantParent") { 425 Properties |= 1 << SDNPWantParent; 426 } else { 427 errs() << "Unsupported SD Node property '" << PropList[i]->getName() 428 << "' on ComplexPattern '" << R->getName() << "'!\n"; 429 exit(1); 430 } 431 } 432 433 //===----------------------------------------------------------------------===// 434 // CodeGenIntrinsic Implementation 435 //===----------------------------------------------------------------------===// 436 437 std::vector<CodeGenIntrinsic> llvm::LoadIntrinsics(const RecordKeeper &RC, 438 bool TargetOnly) { 439 std::vector<Record*> I = RC.getAllDerivedDefinitions("Intrinsic"); 440 441 std::vector<CodeGenIntrinsic> Result; 442 443 for (unsigned i = 0, e = I.size(); i != e; ++i) { 444 bool isTarget = I[i]->getValueAsBit("isTarget"); 445 if (isTarget == TargetOnly) 446 Result.push_back(CodeGenIntrinsic(I[i])); 447 } 448 return Result; 449 } 450 451 CodeGenIntrinsic::CodeGenIntrinsic(Record *R) { 452 TheDef = R; 453 std::string DefName = R->getName(); 454 ModRef = ReadWriteMem; 455 isOverloaded = false; 456 isCommutative = false; 457 458 if (DefName.size() <= 4 || 459 std::string(DefName.begin(), DefName.begin() + 4) != "int_") 460 throw "Intrinsic '" + DefName + "' does not start with 'int_'!"; 461 462 EnumName = std::string(DefName.begin()+4, DefName.end()); 463 464 if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field. 465 GCCBuiltinName = R->getValueAsString("GCCBuiltinName"); 466 467 TargetPrefix = R->getValueAsString("TargetPrefix"); 468 Name = R->getValueAsString("LLVMName"); 469 470 if (Name == "") { 471 // If an explicit name isn't specified, derive one from the DefName. 472 Name = "llvm."; 473 474 for (unsigned i = 0, e = EnumName.size(); i != e; ++i) 475 Name += (EnumName[i] == '_') ? '.' : EnumName[i]; 476 } else { 477 // Verify it starts with "llvm.". 478 if (Name.size() <= 5 || 479 std::string(Name.begin(), Name.begin() + 5) != "llvm.") 480 throw "Intrinsic '" + DefName + "'s name does not start with 'llvm.'!"; 481 } 482 483 // If TargetPrefix is specified, make sure that Name starts with 484 // "llvm.<targetprefix>.". 485 if (!TargetPrefix.empty()) { 486 if (Name.size() < 6+TargetPrefix.size() || 487 std::string(Name.begin() + 5, Name.begin() + 6 + TargetPrefix.size()) 488 != (TargetPrefix + ".")) 489 throw "Intrinsic '" + DefName + "' does not start with 'llvm." + 490 TargetPrefix + ".'!"; 491 } 492 493 // Parse the list of return types. 494 std::vector<MVT::SimpleValueType> OverloadedVTs; 495 ListInit *TypeList = R->getValueAsListInit("RetTypes"); 496 for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) { 497 Record *TyEl = TypeList->getElementAsRecord(i); 498 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 499 MVT::SimpleValueType VT; 500 if (TyEl->isSubClassOf("LLVMMatchType")) { 501 unsigned MatchTy = TyEl->getValueAsInt("Number"); 502 assert(MatchTy < OverloadedVTs.size() && 503 "Invalid matching number!"); 504 VT = OverloadedVTs[MatchTy]; 505 // It only makes sense to use the extended and truncated vector element 506 // variants with iAny types; otherwise, if the intrinsic is not 507 // overloaded, all the types can be specified directly. 508 assert(((!TyEl->isSubClassOf("LLVMExtendedElementVectorType") && 509 !TyEl->isSubClassOf("LLVMTruncatedElementVectorType")) || 510 VT == MVT::iAny || VT == MVT::vAny) && 511 "Expected iAny or vAny type"); 512 } else { 513 VT = getValueType(TyEl->getValueAsDef("VT")); 514 } 515 if (EVT(VT).isOverloaded()) { 516 OverloadedVTs.push_back(VT); 517 isOverloaded = true; 518 } 519 520 // Reject invalid types. 521 if (VT == MVT::isVoid) 522 throw "Intrinsic '" + DefName + " has void in result type list!"; 523 524 IS.RetVTs.push_back(VT); 525 IS.RetTypeDefs.push_back(TyEl); 526 } 527 528 // Parse the list of parameter types. 529 TypeList = R->getValueAsListInit("ParamTypes"); 530 for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) { 531 Record *TyEl = TypeList->getElementAsRecord(i); 532 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 533 MVT::SimpleValueType VT; 534 if (TyEl->isSubClassOf("LLVMMatchType")) { 535 unsigned MatchTy = TyEl->getValueAsInt("Number"); 536 assert(MatchTy < OverloadedVTs.size() && 537 "Invalid matching number!"); 538 VT = OverloadedVTs[MatchTy]; 539 // It only makes sense to use the extended and truncated vector element 540 // variants with iAny types; otherwise, if the intrinsic is not 541 // overloaded, all the types can be specified directly. 542 assert(((!TyEl->isSubClassOf("LLVMExtendedElementVectorType") && 543 !TyEl->isSubClassOf("LLVMTruncatedElementVectorType")) || 544 VT == MVT::iAny || VT == MVT::vAny) && 545 "Expected iAny or vAny type"); 546 } else 547 VT = getValueType(TyEl->getValueAsDef("VT")); 548 549 if (EVT(VT).isOverloaded()) { 550 OverloadedVTs.push_back(VT); 551 isOverloaded = true; 552 } 553 554 // Reject invalid types. 555 if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/) 556 throw "Intrinsic '" + DefName + " has void in result type list!"; 557 558 IS.ParamVTs.push_back(VT); 559 IS.ParamTypeDefs.push_back(TyEl); 560 } 561 562 // Parse the intrinsic properties. 563 ListInit *PropList = R->getValueAsListInit("Properties"); 564 for (unsigned i = 0, e = PropList->getSize(); i != e; ++i) { 565 Record *Property = PropList->getElementAsRecord(i); 566 assert(Property->isSubClassOf("IntrinsicProperty") && 567 "Expected a property!"); 568 569 if (Property->getName() == "IntrNoMem") 570 ModRef = NoMem; 571 else if (Property->getName() == "IntrReadArgMem") 572 ModRef = ReadArgMem; 573 else if (Property->getName() == "IntrReadMem") 574 ModRef = ReadMem; 575 else if (Property->getName() == "IntrReadWriteArgMem") 576 ModRef = ReadWriteArgMem; 577 else if (Property->getName() == "Commutative") 578 isCommutative = true; 579 else if (Property->isSubClassOf("NoCapture")) { 580 unsigned ArgNo = Property->getValueAsInt("ArgNo"); 581 ArgumentAttributes.push_back(std::make_pair(ArgNo, NoCapture)); 582 } else 583 assert(0 && "Unknown property!"); 584 } 585 } 586