1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This class wraps target description classes used by the various code 10 // generation TableGen backends. This makes it easier to access the data and 11 // provides a single place that needs to check it for validity. All of these 12 // classes abort on error conditions. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "CodeGenTarget.h" 17 #include "CodeGenDAGPatterns.h" 18 #include "CodeGenIntrinsics.h" 19 #include "CodeGenSchedule.h" 20 #include "llvm/ADT/STLExtras.h" 21 #include "llvm/ADT/StringExtras.h" 22 #include "llvm/Support/CommandLine.h" 23 #include "llvm/Support/Timer.h" 24 #include "llvm/TableGen/Error.h" 25 #include "llvm/TableGen/Record.h" 26 #include "llvm/TableGen/TableGenBackend.h" 27 #include <algorithm> 28 using namespace llvm; 29 30 cl::OptionCategory AsmParserCat("Options for -gen-asm-parser"); 31 cl::OptionCategory AsmWriterCat("Options for -gen-asm-writer"); 32 33 static cl::opt<unsigned> 34 AsmParserNum("asmparsernum", cl::init(0), 35 cl::desc("Make -gen-asm-parser emit assembly parser #N"), 36 cl::cat(AsmParserCat)); 37 38 static cl::opt<unsigned> 39 AsmWriterNum("asmwriternum", cl::init(0), 40 cl::desc("Make -gen-asm-writer emit assembly writer #N"), 41 cl::cat(AsmWriterCat)); 42 43 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen 44 /// record corresponds to. 45 MVT::SimpleValueType llvm::getValueType(Record *Rec) { 46 return (MVT::SimpleValueType)Rec->getValueAsInt("Value"); 47 } 48 49 StringRef llvm::getName(MVT::SimpleValueType T) { 50 switch (T) { 51 case MVT::Other: return "UNKNOWN"; 52 case MVT::iPTR: return "TLI.getPointerTy()"; 53 case MVT::iPTRAny: return "TLI.getPointerTy()"; 54 default: return getEnumName(T); 55 } 56 } 57 58 StringRef llvm::getEnumName(MVT::SimpleValueType T) { 59 switch (T) { 60 case MVT::Other: return "MVT::Other"; 61 case MVT::i1: return "MVT::i1"; 62 case MVT::i8: return "MVT::i8"; 63 case MVT::i16: return "MVT::i16"; 64 case MVT::i32: return "MVT::i32"; 65 case MVT::i64: return "MVT::i64"; 66 case MVT::i128: return "MVT::i128"; 67 case MVT::Any: return "MVT::Any"; 68 case MVT::iAny: return "MVT::iAny"; 69 case MVT::fAny: return "MVT::fAny"; 70 case MVT::vAny: return "MVT::vAny"; 71 case MVT::f16: return "MVT::f16"; 72 case MVT::bf16: return "MVT::bf16"; 73 case MVT::f32: return "MVT::f32"; 74 case MVT::f64: return "MVT::f64"; 75 case MVT::f80: return "MVT::f80"; 76 case MVT::f128: return "MVT::f128"; 77 case MVT::ppcf128: return "MVT::ppcf128"; 78 case MVT::x86mmx: return "MVT::x86mmx"; 79 case MVT::Glue: return "MVT::Glue"; 80 case MVT::isVoid: return "MVT::isVoid"; 81 case MVT::v1i1: return "MVT::v1i1"; 82 case MVT::v2i1: return "MVT::v2i1"; 83 case MVT::v4i1: return "MVT::v4i1"; 84 case MVT::v8i1: return "MVT::v8i1"; 85 case MVT::v16i1: return "MVT::v16i1"; 86 case MVT::v32i1: return "MVT::v32i1"; 87 case MVT::v64i1: return "MVT::v64i1"; 88 case MVT::v128i1: return "MVT::v128i1"; 89 case MVT::v256i1: return "MVT::v256i1"; 90 case MVT::v512i1: return "MVT::v512i1"; 91 case MVT::v1024i1: return "MVT::v1024i1"; 92 case MVT::v1i8: return "MVT::v1i8"; 93 case MVT::v2i8: return "MVT::v2i8"; 94 case MVT::v4i8: return "MVT::v4i8"; 95 case MVT::v8i8: return "MVT::v8i8"; 96 case MVT::v16i8: return "MVT::v16i8"; 97 case MVT::v32i8: return "MVT::v32i8"; 98 case MVT::v64i8: return "MVT::v64i8"; 99 case MVT::v128i8: return "MVT::v128i8"; 100 case MVT::v256i8: return "MVT::v256i8"; 101 case MVT::v1i16: return "MVT::v1i16"; 102 case MVT::v2i16: return "MVT::v2i16"; 103 case MVT::v3i16: return "MVT::v3i16"; 104 case MVT::v4i16: return "MVT::v4i16"; 105 case MVT::v8i16: return "MVT::v8i16"; 106 case MVT::v16i16: return "MVT::v16i16"; 107 case MVT::v32i16: return "MVT::v32i16"; 108 case MVT::v64i16: return "MVT::v64i16"; 109 case MVT::v128i16: return "MVT::v128i16"; 110 case MVT::v1i32: return "MVT::v1i32"; 111 case MVT::v2i32: return "MVT::v2i32"; 112 case MVT::v3i32: return "MVT::v3i32"; 113 case MVT::v4i32: return "MVT::v4i32"; 114 case MVT::v5i32: return "MVT::v5i32"; 115 case MVT::v8i32: return "MVT::v8i32"; 116 case MVT::v16i32: return "MVT::v16i32"; 117 case MVT::v32i32: return "MVT::v32i32"; 118 case MVT::v64i32: return "MVT::v64i32"; 119 case MVT::v128i32: return "MVT::v128i32"; 120 case MVT::v256i32: return "MVT::v256i32"; 121 case MVT::v512i32: return "MVT::v512i32"; 122 case MVT::v1024i32: return "MVT::v1024i32"; 123 case MVT::v2048i32: return "MVT::v2048i32"; 124 case MVT::v1i64: return "MVT::v1i64"; 125 case MVT::v2i64: return "MVT::v2i64"; 126 case MVT::v4i64: return "MVT::v4i64"; 127 case MVT::v8i64: return "MVT::v8i64"; 128 case MVT::v16i64: return "MVT::v16i64"; 129 case MVT::v32i64: return "MVT::v32i64"; 130 case MVT::v1i128: return "MVT::v1i128"; 131 case MVT::v2f16: return "MVT::v2f16"; 132 case MVT::v3f16: return "MVT::v3f16"; 133 case MVT::v4f16: return "MVT::v4f16"; 134 case MVT::v8f16: return "MVT::v8f16"; 135 case MVT::v16f16: return "MVT::v16f16"; 136 case MVT::v32f16: return "MVT::v32f16"; 137 case MVT::v64f16: return "MVT::v64f16"; 138 case MVT::v128f16: return "MVT::v128f16"; 139 case MVT::v2bf16: return "MVT::v2bf16"; 140 case MVT::v3bf16: return "MVT::v3bf16"; 141 case MVT::v4bf16: return "MVT::v4bf16"; 142 case MVT::v8bf16: return "MVT::v8bf16"; 143 case MVT::v16bf16: return "MVT::v16bf16"; 144 case MVT::v32bf16: return "MVT::v32bf16"; 145 case MVT::v64bf16: return "MVT::v64bf16"; 146 case MVT::v128bf16: return "MVT::v128bf16"; 147 case MVT::v1f32: return "MVT::v1f32"; 148 case MVT::v2f32: return "MVT::v2f32"; 149 case MVT::v3f32: return "MVT::v3f32"; 150 case MVT::v4f32: return "MVT::v4f32"; 151 case MVT::v5f32: return "MVT::v5f32"; 152 case MVT::v8f32: return "MVT::v8f32"; 153 case MVT::v16f32: return "MVT::v16f32"; 154 case MVT::v32f32: return "MVT::v32f32"; 155 case MVT::v64f32: return "MVT::v64f32"; 156 case MVT::v128f32: return "MVT::v128f32"; 157 case MVT::v256f32: return "MVT::v256f32"; 158 case MVT::v512f32: return "MVT::v512f32"; 159 case MVT::v1024f32: return "MVT::v1024f32"; 160 case MVT::v2048f32: return "MVT::v2048f32"; 161 case MVT::v1f64: return "MVT::v1f64"; 162 case MVT::v2f64: return "MVT::v2f64"; 163 case MVT::v4f64: return "MVT::v4f64"; 164 case MVT::v8f64: return "MVT::v8f64"; 165 case MVT::v16f64: return "MVT::v16f64"; 166 case MVT::v32f64: return "MVT::v32f64"; 167 case MVT::nxv1i1: return "MVT::nxv1i1"; 168 case MVT::nxv2i1: return "MVT::nxv2i1"; 169 case MVT::nxv4i1: return "MVT::nxv4i1"; 170 case MVT::nxv8i1: return "MVT::nxv8i1"; 171 case MVT::nxv16i1: return "MVT::nxv16i1"; 172 case MVT::nxv32i1: return "MVT::nxv32i1"; 173 case MVT::nxv64i1: return "MVT::nxv64i1"; 174 case MVT::nxv1i8: return "MVT::nxv1i8"; 175 case MVT::nxv2i8: return "MVT::nxv2i8"; 176 case MVT::nxv4i8: return "MVT::nxv4i8"; 177 case MVT::nxv8i8: return "MVT::nxv8i8"; 178 case MVT::nxv16i8: return "MVT::nxv16i8"; 179 case MVT::nxv32i8: return "MVT::nxv32i8"; 180 case MVT::nxv64i8: return "MVT::nxv64i8"; 181 case MVT::nxv1i16: return "MVT::nxv1i16"; 182 case MVT::nxv2i16: return "MVT::nxv2i16"; 183 case MVT::nxv4i16: return "MVT::nxv4i16"; 184 case MVT::nxv8i16: return "MVT::nxv8i16"; 185 case MVT::nxv16i16: return "MVT::nxv16i16"; 186 case MVT::nxv32i16: return "MVT::nxv32i16"; 187 case MVT::nxv1i32: return "MVT::nxv1i32"; 188 case MVT::nxv2i32: return "MVT::nxv2i32"; 189 case MVT::nxv4i32: return "MVT::nxv4i32"; 190 case MVT::nxv8i32: return "MVT::nxv8i32"; 191 case MVT::nxv16i32: return "MVT::nxv16i32"; 192 case MVT::nxv32i32: return "MVT::nxv32i32"; 193 case MVT::nxv1i64: return "MVT::nxv1i64"; 194 case MVT::nxv2i64: return "MVT::nxv2i64"; 195 case MVT::nxv4i64: return "MVT::nxv4i64"; 196 case MVT::nxv8i64: return "MVT::nxv8i64"; 197 case MVT::nxv16i64: return "MVT::nxv16i64"; 198 case MVT::nxv32i64: return "MVT::nxv32i64"; 199 case MVT::nxv1f16: return "MVT::nxv1f16"; 200 case MVT::nxv2f16: return "MVT::nxv2f16"; 201 case MVT::nxv4f16: return "MVT::nxv4f16"; 202 case MVT::nxv8f16: return "MVT::nxv8f16"; 203 case MVT::nxv16f16: return "MVT::nxv16f16"; 204 case MVT::nxv32f16: return "MVT::nxv32f16"; 205 case MVT::nxv2bf16: return "MVT::nxv2bf16"; 206 case MVT::nxv4bf16: return "MVT::nxv4bf16"; 207 case MVT::nxv8bf16: return "MVT::nxv8bf16"; 208 case MVT::nxv1f32: return "MVT::nxv1f32"; 209 case MVT::nxv2f32: return "MVT::nxv2f32"; 210 case MVT::nxv4f32: return "MVT::nxv4f32"; 211 case MVT::nxv8f32: return "MVT::nxv8f32"; 212 case MVT::nxv16f32: return "MVT::nxv16f32"; 213 case MVT::nxv1f64: return "MVT::nxv1f64"; 214 case MVT::nxv2f64: return "MVT::nxv2f64"; 215 case MVT::nxv4f64: return "MVT::nxv4f64"; 216 case MVT::nxv8f64: return "MVT::nxv8f64"; 217 case MVT::token: return "MVT::token"; 218 case MVT::Metadata: return "MVT::Metadata"; 219 case MVT::iPTR: return "MVT::iPTR"; 220 case MVT::iPTRAny: return "MVT::iPTRAny"; 221 case MVT::Untyped: return "MVT::Untyped"; 222 case MVT::exnref: return "MVT::exnref"; 223 default: llvm_unreachable("ILLEGAL VALUE TYPE!"); 224 } 225 } 226 227 /// getQualifiedName - Return the name of the specified record, with a 228 /// namespace qualifier if the record contains one. 229 /// 230 std::string llvm::getQualifiedName(const Record *R) { 231 std::string Namespace; 232 if (R->getValue("Namespace")) 233 Namespace = std::string(R->getValueAsString("Namespace")); 234 if (Namespace.empty()) 235 return std::string(R->getName()); 236 return Namespace + "::" + R->getName().str(); 237 } 238 239 240 /// getTarget - Return the current instance of the Target class. 241 /// 242 CodeGenTarget::CodeGenTarget(RecordKeeper &records) 243 : Records(records), CGH(records) { 244 std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target"); 245 if (Targets.size() == 0) 246 PrintFatalError("ERROR: No 'Target' subclasses defined!"); 247 if (Targets.size() != 1) 248 PrintFatalError("ERROR: Multiple subclasses of Target defined!"); 249 TargetRec = Targets[0]; 250 } 251 252 CodeGenTarget::~CodeGenTarget() { 253 } 254 255 const StringRef CodeGenTarget::getName() const { 256 return TargetRec->getName(); 257 } 258 259 StringRef CodeGenTarget::getInstNamespace() const { 260 for (const CodeGenInstruction *Inst : getInstructionsByEnumValue()) { 261 // Make sure not to pick up "TargetOpcode" by accidentally getting 262 // the namespace off the PHI instruction or something. 263 if (Inst->Namespace != "TargetOpcode") 264 return Inst->Namespace; 265 } 266 267 return ""; 268 } 269 270 StringRef CodeGenTarget::getRegNamespace() const { 271 auto &RegClasses = RegBank->getRegClasses(); 272 return RegClasses.size() > 0 ? RegClasses.front().Namespace : ""; 273 } 274 275 Record *CodeGenTarget::getInstructionSet() const { 276 return TargetRec->getValueAsDef("InstructionSet"); 277 } 278 279 bool CodeGenTarget::getAllowRegisterRenaming() const { 280 return TargetRec->getValueAsInt("AllowRegisterRenaming"); 281 } 282 283 /// getAsmParser - Return the AssemblyParser definition for this target. 284 /// 285 Record *CodeGenTarget::getAsmParser() const { 286 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers"); 287 if (AsmParserNum >= LI.size()) 288 PrintFatalError("Target does not have an AsmParser #" + 289 Twine(AsmParserNum) + "!"); 290 return LI[AsmParserNum]; 291 } 292 293 /// getAsmParserVariant - Return the AssemblyParserVariant definition for 294 /// this target. 295 /// 296 Record *CodeGenTarget::getAsmParserVariant(unsigned i) const { 297 std::vector<Record*> LI = 298 TargetRec->getValueAsListOfDefs("AssemblyParserVariants"); 299 if (i >= LI.size()) 300 PrintFatalError("Target does not have an AsmParserVariant #" + Twine(i) + 301 "!"); 302 return LI[i]; 303 } 304 305 /// getAsmParserVariantCount - Return the AssemblyParserVariant definition 306 /// available for this target. 307 /// 308 unsigned CodeGenTarget::getAsmParserVariantCount() const { 309 std::vector<Record*> LI = 310 TargetRec->getValueAsListOfDefs("AssemblyParserVariants"); 311 return LI.size(); 312 } 313 314 /// getAsmWriter - Return the AssemblyWriter definition for this target. 315 /// 316 Record *CodeGenTarget::getAsmWriter() const { 317 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters"); 318 if (AsmWriterNum >= LI.size()) 319 PrintFatalError("Target does not have an AsmWriter #" + 320 Twine(AsmWriterNum) + "!"); 321 return LI[AsmWriterNum]; 322 } 323 324 CodeGenRegBank &CodeGenTarget::getRegBank() const { 325 if (!RegBank) 326 RegBank = std::make_unique<CodeGenRegBank>(Records, getHwModes()); 327 return *RegBank; 328 } 329 330 Optional<CodeGenRegisterClass *> 331 CodeGenTarget::getSuperRegForSubReg(const ValueTypeByHwMode &ValueTy, 332 CodeGenRegBank &RegBank, 333 const CodeGenSubRegIndex *SubIdx) const { 334 std::vector<CodeGenRegisterClass *> Candidates; 335 auto &RegClasses = RegBank.getRegClasses(); 336 337 // Try to find a register class which supports ValueTy, and also contains 338 // SubIdx. 339 for (CodeGenRegisterClass &RC : RegClasses) { 340 // Is there a subclass of this class which contains this subregister index? 341 CodeGenRegisterClass *SubClassWithSubReg = RC.getSubClassWithSubReg(SubIdx); 342 if (!SubClassWithSubReg) 343 continue; 344 345 // We have a class. Check if it supports this value type. 346 if (llvm::none_of(SubClassWithSubReg->VTs, 347 [&ValueTy](const ValueTypeByHwMode &ClassVT) { 348 return ClassVT == ValueTy; 349 })) 350 continue; 351 352 // We have a register class which supports both the value type and 353 // subregister index. Remember it. 354 Candidates.push_back(SubClassWithSubReg); 355 } 356 357 // If we didn't find anything, we're done. 358 if (Candidates.empty()) 359 return None; 360 361 // Find and return the largest of our candidate classes. 362 llvm::stable_sort(Candidates, [&](const CodeGenRegisterClass *A, 363 const CodeGenRegisterClass *B) { 364 if (A->getMembers().size() > B->getMembers().size()) 365 return true; 366 367 if (A->getMembers().size() < B->getMembers().size()) 368 return false; 369 370 // Order by name as a tie-breaker. 371 return StringRef(A->getName()) < B->getName(); 372 }); 373 374 return Candidates[0]; 375 } 376 377 void CodeGenTarget::ReadRegAltNameIndices() const { 378 RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex"); 379 llvm::sort(RegAltNameIndices, LessRecord()); 380 } 381 382 /// getRegisterByName - If there is a register with the specific AsmName, 383 /// return it. 384 const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const { 385 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName(); 386 StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name); 387 if (I == Regs.end()) 388 return nullptr; 389 return I->second; 390 } 391 392 std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R) 393 const { 394 const CodeGenRegister *Reg = getRegBank().getReg(R); 395 std::vector<ValueTypeByHwMode> Result; 396 for (const auto &RC : getRegBank().getRegClasses()) { 397 if (RC.contains(Reg)) { 398 ArrayRef<ValueTypeByHwMode> InVTs = RC.getValueTypes(); 399 Result.insert(Result.end(), InVTs.begin(), InVTs.end()); 400 } 401 } 402 403 // Remove duplicates. 404 llvm::sort(Result); 405 Result.erase(std::unique(Result.begin(), Result.end()), Result.end()); 406 return Result; 407 } 408 409 410 void CodeGenTarget::ReadLegalValueTypes() const { 411 for (const auto &RC : getRegBank().getRegClasses()) 412 LegalValueTypes.insert(LegalValueTypes.end(), RC.VTs.begin(), RC.VTs.end()); 413 414 // Remove duplicates. 415 llvm::sort(LegalValueTypes); 416 LegalValueTypes.erase(std::unique(LegalValueTypes.begin(), 417 LegalValueTypes.end()), 418 LegalValueTypes.end()); 419 } 420 421 CodeGenSchedModels &CodeGenTarget::getSchedModels() const { 422 if (!SchedModels) 423 SchedModels = std::make_unique<CodeGenSchedModels>(Records, *this); 424 return *SchedModels; 425 } 426 427 void CodeGenTarget::ReadInstructions() const { 428 NamedRegionTimer T("Read Instructions", "Time spent reading instructions", 429 "CodeGenTarget", "CodeGenTarget", TimeRegions); 430 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction"); 431 if (Insts.size() <= 2) 432 PrintFatalError("No 'Instruction' subclasses defined!"); 433 434 // Parse the instructions defined in the .td file. 435 for (unsigned i = 0, e = Insts.size(); i != e; ++i) 436 Instructions[Insts[i]] = std::make_unique<CodeGenInstruction>(Insts[i]); 437 } 438 439 static const CodeGenInstruction * 440 GetInstByName(const char *Name, 441 const DenseMap<const Record*, 442 std::unique_ptr<CodeGenInstruction>> &Insts, 443 RecordKeeper &Records) { 444 const Record *Rec = Records.getDef(Name); 445 446 const auto I = Insts.find(Rec); 447 if (!Rec || I == Insts.end()) 448 PrintFatalError(Twine("Could not find '") + Name + "' instruction!"); 449 return I->second.get(); 450 } 451 452 static const char *const FixedInstrs[] = { 453 #define HANDLE_TARGET_OPCODE(OPC) #OPC, 454 #include "llvm/Support/TargetOpcodes.def" 455 nullptr}; 456 457 unsigned CodeGenTarget::getNumFixedInstructions() { 458 return array_lengthof(FixedInstrs) - 1; 459 } 460 461 /// Return all of the instructions defined by the target, ordered by 462 /// their enum value. 463 void CodeGenTarget::ComputeInstrsByEnum() const { 464 const auto &Insts = getInstructions(); 465 for (const char *const *p = FixedInstrs; *p; ++p) { 466 const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records); 467 assert(Instr && "Missing target independent instruction"); 468 assert(Instr->Namespace == "TargetOpcode" && "Bad namespace"); 469 InstrsByEnum.push_back(Instr); 470 } 471 unsigned EndOfPredefines = InstrsByEnum.size(); 472 assert(EndOfPredefines == getNumFixedInstructions() && 473 "Missing generic opcode"); 474 475 for (const auto &I : Insts) { 476 const CodeGenInstruction *CGI = I.second.get(); 477 if (CGI->Namespace != "TargetOpcode") { 478 InstrsByEnum.push_back(CGI); 479 if (CGI->TheDef->getValueAsBit("isPseudo")) 480 ++NumPseudoInstructions; 481 } 482 } 483 484 assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr"); 485 486 // All of the instructions are now in random order based on the map iteration. 487 llvm::sort( 488 InstrsByEnum.begin() + EndOfPredefines, InstrsByEnum.end(), 489 [](const CodeGenInstruction *Rec1, const CodeGenInstruction *Rec2) { 490 const auto &D1 = *Rec1->TheDef; 491 const auto &D2 = *Rec2->TheDef; 492 return std::make_tuple(!D1.getValueAsBit("isPseudo"), D1.getName()) < 493 std::make_tuple(!D2.getValueAsBit("isPseudo"), D2.getName()); 494 }); 495 } 496 497 498 /// isLittleEndianEncoding - Return whether this target encodes its instruction 499 /// in little-endian format, i.e. bits laid out in the order [0..n] 500 /// 501 bool CodeGenTarget::isLittleEndianEncoding() const { 502 return getInstructionSet()->getValueAsBit("isLittleEndianEncoding"); 503 } 504 505 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit 506 /// encodings, reverse the bit order of all instructions. 507 void CodeGenTarget::reverseBitsForLittleEndianEncoding() { 508 if (!isLittleEndianEncoding()) 509 return; 510 511 std::vector<Record *> Insts = 512 Records.getAllDerivedDefinitions("InstructionEncoding"); 513 for (Record *R : Insts) { 514 if (R->getValueAsString("Namespace") == "TargetOpcode" || 515 R->getValueAsBit("isPseudo")) 516 continue; 517 518 BitsInit *BI = R->getValueAsBitsInit("Inst"); 519 520 unsigned numBits = BI->getNumBits(); 521 522 SmallVector<Init *, 16> NewBits(numBits); 523 524 for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) { 525 unsigned bitSwapIdx = numBits - bit - 1; 526 Init *OrigBit = BI->getBit(bit); 527 Init *BitSwap = BI->getBit(bitSwapIdx); 528 NewBits[bit] = BitSwap; 529 NewBits[bitSwapIdx] = OrigBit; 530 } 531 if (numBits % 2) { 532 unsigned middle = (numBits + 1) / 2; 533 NewBits[middle] = BI->getBit(middle); 534 } 535 536 BitsInit *NewBI = BitsInit::get(NewBits); 537 538 // Update the bits in reversed order so that emitInstrOpBits will get the 539 // correct endianness. 540 R->getValue("Inst")->setValue(NewBI); 541 } 542 } 543 544 /// guessInstructionProperties - Return true if it's OK to guess instruction 545 /// properties instead of raising an error. 546 /// 547 /// This is configurable as a temporary migration aid. It will eventually be 548 /// permanently false. 549 bool CodeGenTarget::guessInstructionProperties() const { 550 return getInstructionSet()->getValueAsBit("guessInstructionProperties"); 551 } 552 553 //===----------------------------------------------------------------------===// 554 // ComplexPattern implementation 555 // 556 ComplexPattern::ComplexPattern(Record *R) { 557 Ty = ::getValueType(R->getValueAsDef("Ty")); 558 NumOperands = R->getValueAsInt("NumOperands"); 559 SelectFunc = std::string(R->getValueAsString("SelectFunc")); 560 RootNodes = R->getValueAsListOfDefs("RootNodes"); 561 562 // FIXME: This is a hack to statically increase the priority of patterns which 563 // maps a sub-dag to a complex pattern. e.g. favors LEA over ADD. To get best 564 // possible pattern match we'll need to dynamically calculate the complexity 565 // of all patterns a dag can potentially map to. 566 int64_t RawComplexity = R->getValueAsInt("Complexity"); 567 if (RawComplexity == -1) 568 Complexity = NumOperands * 3; 569 else 570 Complexity = RawComplexity; 571 572 // FIXME: Why is this different from parseSDPatternOperatorProperties? 573 // Parse the properties. 574 Properties = 0; 575 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties"); 576 for (unsigned i = 0, e = PropList.size(); i != e; ++i) 577 if (PropList[i]->getName() == "SDNPHasChain") { 578 Properties |= 1 << SDNPHasChain; 579 } else if (PropList[i]->getName() == "SDNPOptInGlue") { 580 Properties |= 1 << SDNPOptInGlue; 581 } else if (PropList[i]->getName() == "SDNPMayStore") { 582 Properties |= 1 << SDNPMayStore; 583 } else if (PropList[i]->getName() == "SDNPMayLoad") { 584 Properties |= 1 << SDNPMayLoad; 585 } else if (PropList[i]->getName() == "SDNPSideEffect") { 586 Properties |= 1 << SDNPSideEffect; 587 } else if (PropList[i]->getName() == "SDNPMemOperand") { 588 Properties |= 1 << SDNPMemOperand; 589 } else if (PropList[i]->getName() == "SDNPVariadic") { 590 Properties |= 1 << SDNPVariadic; 591 } else if (PropList[i]->getName() == "SDNPWantRoot") { 592 Properties |= 1 << SDNPWantRoot; 593 } else if (PropList[i]->getName() == "SDNPWantParent") { 594 Properties |= 1 << SDNPWantParent; 595 } else { 596 PrintFatalError(R->getLoc(), "Unsupported SD Node property '" + 597 PropList[i]->getName() + 598 "' on ComplexPattern '" + R->getName() + 599 "'!"); 600 } 601 } 602 603 //===----------------------------------------------------------------------===// 604 // CodeGenIntrinsic Implementation 605 //===----------------------------------------------------------------------===// 606 607 CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC) { 608 std::vector<Record *> IntrProperties = 609 RC.getAllDerivedDefinitions("IntrinsicProperty"); 610 611 std::vector<Record *> DefaultProperties; 612 for (Record *Rec : IntrProperties) 613 if (Rec->getValueAsBit("IsDefault")) 614 DefaultProperties.push_back(Rec); 615 616 std::vector<Record *> Defs = RC.getAllDerivedDefinitions("Intrinsic"); 617 Intrinsics.reserve(Defs.size()); 618 619 for (unsigned I = 0, e = Defs.size(); I != e; ++I) 620 Intrinsics.push_back(CodeGenIntrinsic(Defs[I], DefaultProperties)); 621 622 llvm::sort(Intrinsics, 623 [](const CodeGenIntrinsic &LHS, const CodeGenIntrinsic &RHS) { 624 return std::tie(LHS.TargetPrefix, LHS.Name) < 625 std::tie(RHS.TargetPrefix, RHS.Name); 626 }); 627 Targets.push_back({"", 0, 0}); 628 for (size_t I = 0, E = Intrinsics.size(); I < E; ++I) 629 if (Intrinsics[I].TargetPrefix != Targets.back().Name) { 630 Targets.back().Count = I - Targets.back().Offset; 631 Targets.push_back({Intrinsics[I].TargetPrefix, I, 0}); 632 } 633 Targets.back().Count = Intrinsics.size() - Targets.back().Offset; 634 } 635 636 CodeGenIntrinsic::CodeGenIntrinsic(Record *R, 637 std::vector<Record *> DefaultProperties) { 638 TheDef = R; 639 std::string DefName = std::string(R->getName()); 640 ArrayRef<SMLoc> DefLoc = R->getLoc(); 641 ModRef = ReadWriteMem; 642 Properties = 0; 643 isOverloaded = false; 644 isCommutative = false; 645 canThrow = false; 646 isNoReturn = false; 647 isNoSync = false; 648 isNoFree = false; 649 isWillReturn = false; 650 isCold = false; 651 isNoDuplicate = false; 652 isConvergent = false; 653 isSpeculatable = false; 654 hasSideEffects = false; 655 656 if (DefName.size() <= 4 || 657 std::string(DefName.begin(), DefName.begin() + 4) != "int_") 658 PrintFatalError(DefLoc, 659 "Intrinsic '" + DefName + "' does not start with 'int_'!"); 660 661 EnumName = std::string(DefName.begin()+4, DefName.end()); 662 663 if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field. 664 GCCBuiltinName = std::string(R->getValueAsString("GCCBuiltinName")); 665 if (R->getValue("MSBuiltinName")) // Ignore a missing MSBuiltinName field. 666 MSBuiltinName = std::string(R->getValueAsString("MSBuiltinName")); 667 668 TargetPrefix = std::string(R->getValueAsString("TargetPrefix")); 669 Name = std::string(R->getValueAsString("LLVMName")); 670 671 if (Name == "") { 672 // If an explicit name isn't specified, derive one from the DefName. 673 Name = "llvm."; 674 675 for (unsigned i = 0, e = EnumName.size(); i != e; ++i) 676 Name += (EnumName[i] == '_') ? '.' : EnumName[i]; 677 } else { 678 // Verify it starts with "llvm.". 679 if (Name.size() <= 5 || 680 std::string(Name.begin(), Name.begin() + 5) != "llvm.") 681 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 682 "'s name does not start with 'llvm.'!"); 683 } 684 685 // If TargetPrefix is specified, make sure that Name starts with 686 // "llvm.<targetprefix>.". 687 if (!TargetPrefix.empty()) { 688 if (Name.size() < 6+TargetPrefix.size() || 689 std::string(Name.begin() + 5, Name.begin() + 6 + TargetPrefix.size()) 690 != (TargetPrefix + ".")) 691 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 692 "' does not start with 'llvm." + 693 TargetPrefix + ".'!"); 694 } 695 696 ListInit *RetTypes = R->getValueAsListInit("RetTypes"); 697 ListInit *ParamTypes = R->getValueAsListInit("ParamTypes"); 698 699 // First collate a list of overloaded types. 700 std::vector<MVT::SimpleValueType> OverloadedVTs; 701 for (ListInit *TypeList : {RetTypes, ParamTypes}) { 702 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 703 Record *TyEl = TypeList->getElementAsRecord(i); 704 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 705 706 if (TyEl->isSubClassOf("LLVMMatchType")) 707 continue; 708 709 MVT::SimpleValueType VT = getValueType(TyEl->getValueAsDef("VT")); 710 if (MVT(VT).isOverloaded()) { 711 OverloadedVTs.push_back(VT); 712 isOverloaded = true; 713 } 714 } 715 } 716 717 // Parse the list of return types. 718 ListInit *TypeList = RetTypes; 719 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 720 Record *TyEl = TypeList->getElementAsRecord(i); 721 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 722 MVT::SimpleValueType VT; 723 if (TyEl->isSubClassOf("LLVMMatchType")) { 724 unsigned MatchTy = TyEl->getValueAsInt("Number"); 725 assert(MatchTy < OverloadedVTs.size() && 726 "Invalid matching number!"); 727 VT = OverloadedVTs[MatchTy]; 728 // It only makes sense to use the extended and truncated vector element 729 // variants with iAny types; otherwise, if the intrinsic is not 730 // overloaded, all the types can be specified directly. 731 assert(((!TyEl->isSubClassOf("LLVMExtendedType") && 732 !TyEl->isSubClassOf("LLVMTruncatedType")) || 733 VT == MVT::iAny || VT == MVT::vAny) && 734 "Expected iAny or vAny type"); 735 } else { 736 VT = getValueType(TyEl->getValueAsDef("VT")); 737 } 738 739 // Reject invalid types. 740 if (VT == MVT::isVoid) 741 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 742 " has void in result type list!"); 743 744 IS.RetVTs.push_back(VT); 745 IS.RetTypeDefs.push_back(TyEl); 746 } 747 748 // Parse the list of parameter types. 749 TypeList = ParamTypes; 750 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 751 Record *TyEl = TypeList->getElementAsRecord(i); 752 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 753 MVT::SimpleValueType VT; 754 if (TyEl->isSubClassOf("LLVMMatchType")) { 755 unsigned MatchTy = TyEl->getValueAsInt("Number"); 756 if (MatchTy >= OverloadedVTs.size()) { 757 PrintError(R->getLoc(), 758 "Parameter #" + Twine(i) + " has out of bounds matching " 759 "number " + Twine(MatchTy)); 760 PrintFatalError(DefLoc, 761 Twine("ParamTypes is ") + TypeList->getAsString()); 762 } 763 VT = OverloadedVTs[MatchTy]; 764 // It only makes sense to use the extended and truncated vector element 765 // variants with iAny types; otherwise, if the intrinsic is not 766 // overloaded, all the types can be specified directly. 767 assert(((!TyEl->isSubClassOf("LLVMExtendedType") && 768 !TyEl->isSubClassOf("LLVMTruncatedType")) || 769 VT == MVT::iAny || VT == MVT::vAny) && 770 "Expected iAny or vAny type"); 771 } else 772 VT = getValueType(TyEl->getValueAsDef("VT")); 773 774 // Reject invalid types. 775 if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/) 776 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 777 " has void in result type list!"); 778 779 IS.ParamVTs.push_back(VT); 780 IS.ParamTypeDefs.push_back(TyEl); 781 } 782 783 // Set default properties to true. 784 setDefaultProperties(R, DefaultProperties); 785 786 // Parse the intrinsic properties. 787 ListInit *PropList = R->getValueAsListInit("IntrProperties"); 788 for (unsigned i = 0, e = PropList->size(); i != e; ++i) { 789 Record *Property = PropList->getElementAsRecord(i); 790 assert(Property->isSubClassOf("IntrinsicProperty") && 791 "Expected a property!"); 792 793 setProperty(Property); 794 } 795 796 // Also record the SDPatternOperator Properties. 797 Properties = parseSDPatternOperatorProperties(R); 798 799 // Sort the argument attributes for later benefit. 800 llvm::sort(ArgumentAttributes); 801 } 802 803 void CodeGenIntrinsic::setDefaultProperties( 804 Record *R, std::vector<Record *> DefaultProperties) { 805 // opt-out of using default attributes. 806 if (R->getValueAsBit("DisableDefaultAttributes")) 807 return; 808 809 for (Record *Rec : DefaultProperties) 810 setProperty(Rec); 811 } 812 813 void CodeGenIntrinsic::setProperty(Record *R) { 814 if (R->getName() == "IntrNoMem") 815 ModRef = NoMem; 816 else if (R->getName() == "IntrReadMem") 817 ModRef = ModRefBehavior(ModRef & ~MR_Mod); 818 else if (R->getName() == "IntrWriteMem") 819 ModRef = ModRefBehavior(ModRef & ~MR_Ref); 820 else if (R->getName() == "IntrArgMemOnly") 821 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem); 822 else if (R->getName() == "IntrInaccessibleMemOnly") 823 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_InaccessibleMem); 824 else if (R->getName() == "IntrInaccessibleMemOrArgMemOnly") 825 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem | 826 MR_InaccessibleMem); 827 else if (R->getName() == "Commutative") 828 isCommutative = true; 829 else if (R->getName() == "Throws") 830 canThrow = true; 831 else if (R->getName() == "IntrNoDuplicate") 832 isNoDuplicate = true; 833 else if (R->getName() == "IntrConvergent") 834 isConvergent = true; 835 else if (R->getName() == "IntrNoReturn") 836 isNoReturn = true; 837 else if (R->getName() == "IntrNoSync") 838 isNoSync = true; 839 else if (R->getName() == "IntrNoFree") 840 isNoFree = true; 841 else if (R->getName() == "IntrWillReturn") 842 isWillReturn = true; 843 else if (R->getName() == "IntrCold") 844 isCold = true; 845 else if (R->getName() == "IntrSpeculatable") 846 isSpeculatable = true; 847 else if (R->getName() == "IntrHasSideEffects") 848 hasSideEffects = true; 849 else if (R->isSubClassOf("NoCapture")) { 850 unsigned ArgNo = R->getValueAsInt("ArgNo"); 851 ArgumentAttributes.emplace_back(ArgNo, NoCapture, 0); 852 } else if (R->isSubClassOf("NoAlias")) { 853 unsigned ArgNo = R->getValueAsInt("ArgNo"); 854 ArgumentAttributes.emplace_back(ArgNo, NoAlias, 0); 855 } else if (R->isSubClassOf("NoUndef")) { 856 unsigned ArgNo = R->getValueAsInt("ArgNo"); 857 ArgumentAttributes.emplace_back(ArgNo, NoUndef, 0); 858 } else if (R->isSubClassOf("Returned")) { 859 unsigned ArgNo = R->getValueAsInt("ArgNo"); 860 ArgumentAttributes.emplace_back(ArgNo, Returned, 0); 861 } else if (R->isSubClassOf("ReadOnly")) { 862 unsigned ArgNo = R->getValueAsInt("ArgNo"); 863 ArgumentAttributes.emplace_back(ArgNo, ReadOnly, 0); 864 } else if (R->isSubClassOf("WriteOnly")) { 865 unsigned ArgNo = R->getValueAsInt("ArgNo"); 866 ArgumentAttributes.emplace_back(ArgNo, WriteOnly, 0); 867 } else if (R->isSubClassOf("ReadNone")) { 868 unsigned ArgNo = R->getValueAsInt("ArgNo"); 869 ArgumentAttributes.emplace_back(ArgNo, ReadNone, 0); 870 } else if (R->isSubClassOf("ImmArg")) { 871 unsigned ArgNo = R->getValueAsInt("ArgNo"); 872 ArgumentAttributes.emplace_back(ArgNo, ImmArg, 0); 873 } else if (R->isSubClassOf("Align")) { 874 unsigned ArgNo = R->getValueAsInt("ArgNo"); 875 uint64_t Align = R->getValueAsInt("Align"); 876 ArgumentAttributes.emplace_back(ArgNo, Alignment, Align); 877 } else 878 llvm_unreachable("Unknown property!"); 879 } 880 881 bool CodeGenIntrinsic::isParamAPointer(unsigned ParamIdx) const { 882 if (ParamIdx >= IS.ParamVTs.size()) 883 return false; 884 MVT ParamType = MVT(IS.ParamVTs[ParamIdx]); 885 return ParamType == MVT::iPTR || ParamType == MVT::iPTRAny; 886 } 887 888 bool CodeGenIntrinsic::isParamImmArg(unsigned ParamIdx) const { 889 // Convert argument index to attribute index starting from `FirstArgIndex`. 890 ArgAttribute Val{ParamIdx + 1, ImmArg, 0}; 891 return std::binary_search(ArgumentAttributes.begin(), 892 ArgumentAttributes.end(), Val); 893 } 894