1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This class wraps target description classes used by the various code 10 // generation TableGen backends. This makes it easier to access the data and 11 // provides a single place that needs to check it for validity. All of these 12 // classes abort on error conditions. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "CodeGenTarget.h" 17 #include "CodeGenDAGPatterns.h" 18 #include "CodeGenIntrinsics.h" 19 #include "CodeGenSchedule.h" 20 #include "llvm/ADT/STLExtras.h" 21 #include "llvm/ADT/StringExtras.h" 22 #include "llvm/Support/CommandLine.h" 23 #include "llvm/Support/Timer.h" 24 #include "llvm/TableGen/Error.h" 25 #include "llvm/TableGen/Record.h" 26 #include "llvm/TableGen/TableGenBackend.h" 27 #include <algorithm> 28 using namespace llvm; 29 30 cl::OptionCategory AsmParserCat("Options for -gen-asm-parser"); 31 cl::OptionCategory AsmWriterCat("Options for -gen-asm-writer"); 32 33 static cl::opt<unsigned> 34 AsmParserNum("asmparsernum", cl::init(0), 35 cl::desc("Make -gen-asm-parser emit assembly parser #N"), 36 cl::cat(AsmParserCat)); 37 38 static cl::opt<unsigned> 39 AsmWriterNum("asmwriternum", cl::init(0), 40 cl::desc("Make -gen-asm-writer emit assembly writer #N"), 41 cl::cat(AsmWriterCat)); 42 43 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen 44 /// record corresponds to. 45 MVT::SimpleValueType llvm::getValueType(Record *Rec) { 46 return (MVT::SimpleValueType)Rec->getValueAsInt("Value"); 47 } 48 49 StringRef llvm::getName(MVT::SimpleValueType T) { 50 switch (T) { 51 case MVT::Other: return "UNKNOWN"; 52 case MVT::iPTR: return "TLI.getPointerTy()"; 53 case MVT::iPTRAny: return "TLI.getPointerTy()"; 54 default: return getEnumName(T); 55 } 56 } 57 58 StringRef llvm::getEnumName(MVT::SimpleValueType T) { 59 switch (T) { 60 case MVT::Other: return "MVT::Other"; 61 case MVT::i1: return "MVT::i1"; 62 case MVT::i8: return "MVT::i8"; 63 case MVT::i16: return "MVT::i16"; 64 case MVT::i32: return "MVT::i32"; 65 case MVT::i64: return "MVT::i64"; 66 case MVT::i128: return "MVT::i128"; 67 case MVT::Any: return "MVT::Any"; 68 case MVT::iAny: return "MVT::iAny"; 69 case MVT::fAny: return "MVT::fAny"; 70 case MVT::vAny: return "MVT::vAny"; 71 case MVT::f16: return "MVT::f16"; 72 case MVT::bf16: return "MVT::bf16"; 73 case MVT::f32: return "MVT::f32"; 74 case MVT::f64: return "MVT::f64"; 75 case MVT::f80: return "MVT::f80"; 76 case MVT::f128: return "MVT::f128"; 77 case MVT::ppcf128: return "MVT::ppcf128"; 78 case MVT::x86mmx: return "MVT::x86mmx"; 79 case MVT::x86amx: return "MVT::x86amx"; 80 case MVT::Glue: return "MVT::Glue"; 81 case MVT::isVoid: return "MVT::isVoid"; 82 case MVT::v1i1: return "MVT::v1i1"; 83 case MVT::v2i1: return "MVT::v2i1"; 84 case MVT::v4i1: return "MVT::v4i1"; 85 case MVT::v8i1: return "MVT::v8i1"; 86 case MVT::v16i1: return "MVT::v16i1"; 87 case MVT::v32i1: return "MVT::v32i1"; 88 case MVT::v64i1: return "MVT::v64i1"; 89 case MVT::v128i1: return "MVT::v128i1"; 90 case MVT::v256i1: return "MVT::v256i1"; 91 case MVT::v512i1: return "MVT::v512i1"; 92 case MVT::v1024i1: return "MVT::v1024i1"; 93 case MVT::v1i8: return "MVT::v1i8"; 94 case MVT::v2i8: return "MVT::v2i8"; 95 case MVT::v4i8: return "MVT::v4i8"; 96 case MVT::v8i8: return "MVT::v8i8"; 97 case MVT::v16i8: return "MVT::v16i8"; 98 case MVT::v32i8: return "MVT::v32i8"; 99 case MVT::v64i8: return "MVT::v64i8"; 100 case MVT::v128i8: return "MVT::v128i8"; 101 case MVT::v256i8: return "MVT::v256i8"; 102 case MVT::v1i16: return "MVT::v1i16"; 103 case MVT::v2i16: return "MVT::v2i16"; 104 case MVT::v3i16: return "MVT::v3i16"; 105 case MVT::v4i16: return "MVT::v4i16"; 106 case MVT::v8i16: return "MVT::v8i16"; 107 case MVT::v16i16: return "MVT::v16i16"; 108 case MVT::v32i16: return "MVT::v32i16"; 109 case MVT::v64i16: return "MVT::v64i16"; 110 case MVT::v128i16: return "MVT::v128i16"; 111 case MVT::v1i32: return "MVT::v1i32"; 112 case MVT::v2i32: return "MVT::v2i32"; 113 case MVT::v3i32: return "MVT::v3i32"; 114 case MVT::v4i32: return "MVT::v4i32"; 115 case MVT::v5i32: return "MVT::v5i32"; 116 case MVT::v8i32: return "MVT::v8i32"; 117 case MVT::v16i32: return "MVT::v16i32"; 118 case MVT::v32i32: return "MVT::v32i32"; 119 case MVT::v64i32: return "MVT::v64i32"; 120 case MVT::v128i32: return "MVT::v128i32"; 121 case MVT::v256i32: return "MVT::v256i32"; 122 case MVT::v512i32: return "MVT::v512i32"; 123 case MVT::v1024i32: return "MVT::v1024i32"; 124 case MVT::v2048i32: return "MVT::v2048i32"; 125 case MVT::v1i64: return "MVT::v1i64"; 126 case MVT::v2i64: return "MVT::v2i64"; 127 case MVT::v4i64: return "MVT::v4i64"; 128 case MVT::v8i64: return "MVT::v8i64"; 129 case MVT::v16i64: return "MVT::v16i64"; 130 case MVT::v32i64: return "MVT::v32i64"; 131 case MVT::v64i64: return "MVT::v64i64"; 132 case MVT::v128i64: return "MVT::v128i64"; 133 case MVT::v256i64: return "MVT::v256i64"; 134 case MVT::v1i128: return "MVT::v1i128"; 135 case MVT::v2f16: return "MVT::v2f16"; 136 case MVT::v3f16: return "MVT::v3f16"; 137 case MVT::v4f16: return "MVT::v4f16"; 138 case MVT::v8f16: return "MVT::v8f16"; 139 case MVT::v16f16: return "MVT::v16f16"; 140 case MVT::v32f16: return "MVT::v32f16"; 141 case MVT::v64f16: return "MVT::v64f16"; 142 case MVT::v128f16: return "MVT::v128f16"; 143 case MVT::v2bf16: return "MVT::v2bf16"; 144 case MVT::v3bf16: return "MVT::v3bf16"; 145 case MVT::v4bf16: return "MVT::v4bf16"; 146 case MVT::v8bf16: return "MVT::v8bf16"; 147 case MVT::v16bf16: return "MVT::v16bf16"; 148 case MVT::v32bf16: return "MVT::v32bf16"; 149 case MVT::v64bf16: return "MVT::v64bf16"; 150 case MVT::v128bf16: return "MVT::v128bf16"; 151 case MVT::v1f32: return "MVT::v1f32"; 152 case MVT::v2f32: return "MVT::v2f32"; 153 case MVT::v3f32: return "MVT::v3f32"; 154 case MVT::v4f32: return "MVT::v4f32"; 155 case MVT::v5f32: return "MVT::v5f32"; 156 case MVT::v8f32: return "MVT::v8f32"; 157 case MVT::v16f32: return "MVT::v16f32"; 158 case MVT::v32f32: return "MVT::v32f32"; 159 case MVT::v64f32: return "MVT::v64f32"; 160 case MVT::v128f32: return "MVT::v128f32"; 161 case MVT::v256f32: return "MVT::v256f32"; 162 case MVT::v512f32: return "MVT::v512f32"; 163 case MVT::v1024f32: return "MVT::v1024f32"; 164 case MVT::v2048f32: return "MVT::v2048f32"; 165 case MVT::v1f64: return "MVT::v1f64"; 166 case MVT::v2f64: return "MVT::v2f64"; 167 case MVT::v4f64: return "MVT::v4f64"; 168 case MVT::v8f64: return "MVT::v8f64"; 169 case MVT::v16f64: return "MVT::v16f64"; 170 case MVT::v32f64: return "MVT::v32f64"; 171 case MVT::v64f64: return "MVT::v64f64"; 172 case MVT::v128f64: return "MVT::v128f64"; 173 case MVT::v256f64: return "MVT::v256f64"; 174 case MVT::nxv1i1: return "MVT::nxv1i1"; 175 case MVT::nxv2i1: return "MVT::nxv2i1"; 176 case MVT::nxv4i1: return "MVT::nxv4i1"; 177 case MVT::nxv8i1: return "MVT::nxv8i1"; 178 case MVT::nxv16i1: return "MVT::nxv16i1"; 179 case MVT::nxv32i1: return "MVT::nxv32i1"; 180 case MVT::nxv64i1: return "MVT::nxv64i1"; 181 case MVT::nxv1i8: return "MVT::nxv1i8"; 182 case MVT::nxv2i8: return "MVT::nxv2i8"; 183 case MVT::nxv4i8: return "MVT::nxv4i8"; 184 case MVT::nxv8i8: return "MVT::nxv8i8"; 185 case MVT::nxv16i8: return "MVT::nxv16i8"; 186 case MVT::nxv32i8: return "MVT::nxv32i8"; 187 case MVT::nxv64i8: return "MVT::nxv64i8"; 188 case MVT::nxv1i16: return "MVT::nxv1i16"; 189 case MVT::nxv2i16: return "MVT::nxv2i16"; 190 case MVT::nxv4i16: return "MVT::nxv4i16"; 191 case MVT::nxv8i16: return "MVT::nxv8i16"; 192 case MVT::nxv16i16: return "MVT::nxv16i16"; 193 case MVT::nxv32i16: return "MVT::nxv32i16"; 194 case MVT::nxv1i32: return "MVT::nxv1i32"; 195 case MVT::nxv2i32: return "MVT::nxv2i32"; 196 case MVT::nxv4i32: return "MVT::nxv4i32"; 197 case MVT::nxv8i32: return "MVT::nxv8i32"; 198 case MVT::nxv16i32: return "MVT::nxv16i32"; 199 case MVT::nxv32i32: return "MVT::nxv32i32"; 200 case MVT::nxv1i64: return "MVT::nxv1i64"; 201 case MVT::nxv2i64: return "MVT::nxv2i64"; 202 case MVT::nxv4i64: return "MVT::nxv4i64"; 203 case MVT::nxv8i64: return "MVT::nxv8i64"; 204 case MVT::nxv16i64: return "MVT::nxv16i64"; 205 case MVT::nxv32i64: return "MVT::nxv32i64"; 206 case MVT::nxv1f16: return "MVT::nxv1f16"; 207 case MVT::nxv2f16: return "MVT::nxv2f16"; 208 case MVT::nxv4f16: return "MVT::nxv4f16"; 209 case MVT::nxv8f16: return "MVT::nxv8f16"; 210 case MVT::nxv16f16: return "MVT::nxv16f16"; 211 case MVT::nxv32f16: return "MVT::nxv32f16"; 212 case MVT::nxv2bf16: return "MVT::nxv2bf16"; 213 case MVT::nxv4bf16: return "MVT::nxv4bf16"; 214 case MVT::nxv8bf16: return "MVT::nxv8bf16"; 215 case MVT::nxv1f32: return "MVT::nxv1f32"; 216 case MVT::nxv2f32: return "MVT::nxv2f32"; 217 case MVT::nxv4f32: return "MVT::nxv4f32"; 218 case MVT::nxv8f32: return "MVT::nxv8f32"; 219 case MVT::nxv16f32: return "MVT::nxv16f32"; 220 case MVT::nxv1f64: return "MVT::nxv1f64"; 221 case MVT::nxv2f64: return "MVT::nxv2f64"; 222 case MVT::nxv4f64: return "MVT::nxv4f64"; 223 case MVT::nxv8f64: return "MVT::nxv8f64"; 224 case MVT::token: return "MVT::token"; 225 case MVT::Metadata: return "MVT::Metadata"; 226 case MVT::iPTR: return "MVT::iPTR"; 227 case MVT::iPTRAny: return "MVT::iPTRAny"; 228 case MVT::Untyped: return "MVT::Untyped"; 229 case MVT::exnref: return "MVT::exnref"; 230 case MVT::funcref: return "MVT::funcref"; 231 case MVT::externref: return "MVT::externref"; 232 default: llvm_unreachable("ILLEGAL VALUE TYPE!"); 233 } 234 } 235 236 /// getQualifiedName - Return the name of the specified record, with a 237 /// namespace qualifier if the record contains one. 238 /// 239 std::string llvm::getQualifiedName(const Record *R) { 240 std::string Namespace; 241 if (R->getValue("Namespace")) 242 Namespace = std::string(R->getValueAsString("Namespace")); 243 if (Namespace.empty()) 244 return std::string(R->getName()); 245 return Namespace + "::" + R->getName().str(); 246 } 247 248 249 /// getTarget - Return the current instance of the Target class. 250 /// 251 CodeGenTarget::CodeGenTarget(RecordKeeper &records) 252 : Records(records), CGH(records) { 253 std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target"); 254 if (Targets.size() == 0) 255 PrintFatalError("ERROR: No 'Target' subclasses defined!"); 256 if (Targets.size() != 1) 257 PrintFatalError("ERROR: Multiple subclasses of Target defined!"); 258 TargetRec = Targets[0]; 259 } 260 261 CodeGenTarget::~CodeGenTarget() { 262 } 263 264 const StringRef CodeGenTarget::getName() const { 265 return TargetRec->getName(); 266 } 267 268 /// getInstNamespace - Find and return the target machine's instruction 269 /// namespace. The namespace is cached because it is requested multiple times. 270 StringRef CodeGenTarget::getInstNamespace() const { 271 if (InstNamespace.empty()) { 272 for (const CodeGenInstruction *Inst : getInstructionsByEnumValue()) { 273 // We are not interested in the "TargetOpcode" namespace. 274 if (Inst->Namespace != "TargetOpcode") { 275 InstNamespace = Inst->Namespace; 276 break; 277 } 278 } 279 } 280 281 return InstNamespace; 282 } 283 284 StringRef CodeGenTarget::getRegNamespace() const { 285 auto &RegClasses = RegBank->getRegClasses(); 286 return RegClasses.size() > 0 ? RegClasses.front().Namespace : ""; 287 } 288 289 Record *CodeGenTarget::getInstructionSet() const { 290 return TargetRec->getValueAsDef("InstructionSet"); 291 } 292 293 bool CodeGenTarget::getAllowRegisterRenaming() const { 294 return TargetRec->getValueAsInt("AllowRegisterRenaming"); 295 } 296 297 /// getAsmParser - Return the AssemblyParser definition for this target. 298 /// 299 Record *CodeGenTarget::getAsmParser() const { 300 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers"); 301 if (AsmParserNum >= LI.size()) 302 PrintFatalError("Target does not have an AsmParser #" + 303 Twine(AsmParserNum) + "!"); 304 return LI[AsmParserNum]; 305 } 306 307 /// getAsmParserVariant - Return the AssemblyParserVariant definition for 308 /// this target. 309 /// 310 Record *CodeGenTarget::getAsmParserVariant(unsigned i) const { 311 std::vector<Record*> LI = 312 TargetRec->getValueAsListOfDefs("AssemblyParserVariants"); 313 if (i >= LI.size()) 314 PrintFatalError("Target does not have an AsmParserVariant #" + Twine(i) + 315 "!"); 316 return LI[i]; 317 } 318 319 /// getAsmParserVariantCount - Return the AssemblyParserVariant definition 320 /// available for this target. 321 /// 322 unsigned CodeGenTarget::getAsmParserVariantCount() const { 323 std::vector<Record*> LI = 324 TargetRec->getValueAsListOfDefs("AssemblyParserVariants"); 325 return LI.size(); 326 } 327 328 /// getAsmWriter - Return the AssemblyWriter definition for this target. 329 /// 330 Record *CodeGenTarget::getAsmWriter() const { 331 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters"); 332 if (AsmWriterNum >= LI.size()) 333 PrintFatalError("Target does not have an AsmWriter #" + 334 Twine(AsmWriterNum) + "!"); 335 return LI[AsmWriterNum]; 336 } 337 338 CodeGenRegBank &CodeGenTarget::getRegBank() const { 339 if (!RegBank) 340 RegBank = std::make_unique<CodeGenRegBank>(Records, getHwModes()); 341 return *RegBank; 342 } 343 344 Optional<CodeGenRegisterClass *> 345 CodeGenTarget::getSuperRegForSubReg(const ValueTypeByHwMode &ValueTy, 346 CodeGenRegBank &RegBank, 347 const CodeGenSubRegIndex *SubIdx, 348 bool MustBeAllocatable) const { 349 std::vector<CodeGenRegisterClass *> Candidates; 350 auto &RegClasses = RegBank.getRegClasses(); 351 352 // Try to find a register class which supports ValueTy, and also contains 353 // SubIdx. 354 for (CodeGenRegisterClass &RC : RegClasses) { 355 // Is there a subclass of this class which contains this subregister index? 356 CodeGenRegisterClass *SubClassWithSubReg = RC.getSubClassWithSubReg(SubIdx); 357 if (!SubClassWithSubReg) 358 continue; 359 360 // We have a class. Check if it supports this value type. 361 if (!llvm::is_contained(SubClassWithSubReg->VTs, ValueTy)) 362 continue; 363 364 // If necessary, check that it is allocatable. 365 if (MustBeAllocatable && !SubClassWithSubReg->Allocatable) 366 continue; 367 368 // We have a register class which supports both the value type and 369 // subregister index. Remember it. 370 Candidates.push_back(SubClassWithSubReg); 371 } 372 373 // If we didn't find anything, we're done. 374 if (Candidates.empty()) 375 return None; 376 377 // Find and return the largest of our candidate classes. 378 llvm::stable_sort(Candidates, [&](const CodeGenRegisterClass *A, 379 const CodeGenRegisterClass *B) { 380 if (A->getMembers().size() > B->getMembers().size()) 381 return true; 382 383 if (A->getMembers().size() < B->getMembers().size()) 384 return false; 385 386 // Order by name as a tie-breaker. 387 return StringRef(A->getName()) < B->getName(); 388 }); 389 390 return Candidates[0]; 391 } 392 393 void CodeGenTarget::ReadRegAltNameIndices() const { 394 RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex"); 395 llvm::sort(RegAltNameIndices, LessRecord()); 396 } 397 398 /// getRegisterByName - If there is a register with the specific AsmName, 399 /// return it. 400 const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const { 401 return getRegBank().getRegistersByName().lookup(Name); 402 } 403 404 std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R) 405 const { 406 const CodeGenRegister *Reg = getRegBank().getReg(R); 407 std::vector<ValueTypeByHwMode> Result; 408 for (const auto &RC : getRegBank().getRegClasses()) { 409 if (RC.contains(Reg)) { 410 ArrayRef<ValueTypeByHwMode> InVTs = RC.getValueTypes(); 411 llvm::append_range(Result, InVTs); 412 } 413 } 414 415 // Remove duplicates. 416 llvm::sort(Result); 417 Result.erase(std::unique(Result.begin(), Result.end()), Result.end()); 418 return Result; 419 } 420 421 422 void CodeGenTarget::ReadLegalValueTypes() const { 423 for (const auto &RC : getRegBank().getRegClasses()) 424 llvm::append_range(LegalValueTypes, RC.VTs); 425 426 // Remove duplicates. 427 llvm::sort(LegalValueTypes); 428 LegalValueTypes.erase(std::unique(LegalValueTypes.begin(), 429 LegalValueTypes.end()), 430 LegalValueTypes.end()); 431 } 432 433 CodeGenSchedModels &CodeGenTarget::getSchedModels() const { 434 if (!SchedModels) 435 SchedModels = std::make_unique<CodeGenSchedModels>(Records, *this); 436 return *SchedModels; 437 } 438 439 void CodeGenTarget::ReadInstructions() const { 440 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction"); 441 if (Insts.size() <= 2) 442 PrintFatalError("No 'Instruction' subclasses defined!"); 443 444 // Parse the instructions defined in the .td file. 445 for (unsigned i = 0, e = Insts.size(); i != e; ++i) 446 Instructions[Insts[i]] = std::make_unique<CodeGenInstruction>(Insts[i]); 447 } 448 449 static const CodeGenInstruction * 450 GetInstByName(const char *Name, 451 const DenseMap<const Record*, 452 std::unique_ptr<CodeGenInstruction>> &Insts, 453 RecordKeeper &Records) { 454 const Record *Rec = Records.getDef(Name); 455 456 const auto I = Insts.find(Rec); 457 if (!Rec || I == Insts.end()) 458 PrintFatalError(Twine("Could not find '") + Name + "' instruction!"); 459 return I->second.get(); 460 } 461 462 static const char *const FixedInstrs[] = { 463 #define HANDLE_TARGET_OPCODE(OPC) #OPC, 464 #include "llvm/Support/TargetOpcodes.def" 465 nullptr}; 466 467 unsigned CodeGenTarget::getNumFixedInstructions() { 468 return array_lengthof(FixedInstrs) - 1; 469 } 470 471 /// Return all of the instructions defined by the target, ordered by 472 /// their enum value. 473 void CodeGenTarget::ComputeInstrsByEnum() const { 474 const auto &Insts = getInstructions(); 475 for (const char *const *p = FixedInstrs; *p; ++p) { 476 const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records); 477 assert(Instr && "Missing target independent instruction"); 478 assert(Instr->Namespace == "TargetOpcode" && "Bad namespace"); 479 InstrsByEnum.push_back(Instr); 480 } 481 unsigned EndOfPredefines = InstrsByEnum.size(); 482 assert(EndOfPredefines == getNumFixedInstructions() && 483 "Missing generic opcode"); 484 485 for (const auto &I : Insts) { 486 const CodeGenInstruction *CGI = I.second.get(); 487 if (CGI->Namespace != "TargetOpcode") { 488 InstrsByEnum.push_back(CGI); 489 if (CGI->TheDef->getValueAsBit("isPseudo")) 490 ++NumPseudoInstructions; 491 } 492 } 493 494 assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr"); 495 496 // All of the instructions are now in random order based on the map iteration. 497 llvm::sort( 498 InstrsByEnum.begin() + EndOfPredefines, InstrsByEnum.end(), 499 [](const CodeGenInstruction *Rec1, const CodeGenInstruction *Rec2) { 500 const auto &D1 = *Rec1->TheDef; 501 const auto &D2 = *Rec2->TheDef; 502 return std::make_tuple(!D1.getValueAsBit("isPseudo"), D1.getName()) < 503 std::make_tuple(!D2.getValueAsBit("isPseudo"), D2.getName()); 504 }); 505 } 506 507 508 /// isLittleEndianEncoding - Return whether this target encodes its instruction 509 /// in little-endian format, i.e. bits laid out in the order [0..n] 510 /// 511 bool CodeGenTarget::isLittleEndianEncoding() const { 512 return getInstructionSet()->getValueAsBit("isLittleEndianEncoding"); 513 } 514 515 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit 516 /// encodings, reverse the bit order of all instructions. 517 void CodeGenTarget::reverseBitsForLittleEndianEncoding() { 518 if (!isLittleEndianEncoding()) 519 return; 520 521 std::vector<Record *> Insts = 522 Records.getAllDerivedDefinitions("InstructionEncoding"); 523 for (Record *R : Insts) { 524 if (R->getValueAsString("Namespace") == "TargetOpcode" || 525 R->getValueAsBit("isPseudo")) 526 continue; 527 528 BitsInit *BI = R->getValueAsBitsInit("Inst"); 529 530 unsigned numBits = BI->getNumBits(); 531 532 SmallVector<Init *, 16> NewBits(numBits); 533 534 for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) { 535 unsigned bitSwapIdx = numBits - bit - 1; 536 Init *OrigBit = BI->getBit(bit); 537 Init *BitSwap = BI->getBit(bitSwapIdx); 538 NewBits[bit] = BitSwap; 539 NewBits[bitSwapIdx] = OrigBit; 540 } 541 if (numBits % 2) { 542 unsigned middle = (numBits + 1) / 2; 543 NewBits[middle] = BI->getBit(middle); 544 } 545 546 BitsInit *NewBI = BitsInit::get(NewBits); 547 548 // Update the bits in reversed order so that emitInstrOpBits will get the 549 // correct endianness. 550 R->getValue("Inst")->setValue(NewBI); 551 } 552 } 553 554 /// guessInstructionProperties - Return true if it's OK to guess instruction 555 /// properties instead of raising an error. 556 /// 557 /// This is configurable as a temporary migration aid. It will eventually be 558 /// permanently false. 559 bool CodeGenTarget::guessInstructionProperties() const { 560 return getInstructionSet()->getValueAsBit("guessInstructionProperties"); 561 } 562 563 //===----------------------------------------------------------------------===// 564 // ComplexPattern implementation 565 // 566 ComplexPattern::ComplexPattern(Record *R) { 567 Ty = ::getValueType(R->getValueAsDef("Ty")); 568 NumOperands = R->getValueAsInt("NumOperands"); 569 SelectFunc = std::string(R->getValueAsString("SelectFunc")); 570 RootNodes = R->getValueAsListOfDefs("RootNodes"); 571 572 // FIXME: This is a hack to statically increase the priority of patterns which 573 // maps a sub-dag to a complex pattern. e.g. favors LEA over ADD. To get best 574 // possible pattern match we'll need to dynamically calculate the complexity 575 // of all patterns a dag can potentially map to. 576 int64_t RawComplexity = R->getValueAsInt("Complexity"); 577 if (RawComplexity == -1) 578 Complexity = NumOperands * 3; 579 else 580 Complexity = RawComplexity; 581 582 // FIXME: Why is this different from parseSDPatternOperatorProperties? 583 // Parse the properties. 584 Properties = 0; 585 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties"); 586 for (unsigned i = 0, e = PropList.size(); i != e; ++i) 587 if (PropList[i]->getName() == "SDNPHasChain") { 588 Properties |= 1 << SDNPHasChain; 589 } else if (PropList[i]->getName() == "SDNPOptInGlue") { 590 Properties |= 1 << SDNPOptInGlue; 591 } else if (PropList[i]->getName() == "SDNPMayStore") { 592 Properties |= 1 << SDNPMayStore; 593 } else if (PropList[i]->getName() == "SDNPMayLoad") { 594 Properties |= 1 << SDNPMayLoad; 595 } else if (PropList[i]->getName() == "SDNPSideEffect") { 596 Properties |= 1 << SDNPSideEffect; 597 } else if (PropList[i]->getName() == "SDNPMemOperand") { 598 Properties |= 1 << SDNPMemOperand; 599 } else if (PropList[i]->getName() == "SDNPVariadic") { 600 Properties |= 1 << SDNPVariadic; 601 } else if (PropList[i]->getName() == "SDNPWantRoot") { 602 Properties |= 1 << SDNPWantRoot; 603 } else if (PropList[i]->getName() == "SDNPWantParent") { 604 Properties |= 1 << SDNPWantParent; 605 } else { 606 PrintFatalError(R->getLoc(), "Unsupported SD Node property '" + 607 PropList[i]->getName() + 608 "' on ComplexPattern '" + R->getName() + 609 "'!"); 610 } 611 } 612 613 //===----------------------------------------------------------------------===// 614 // CodeGenIntrinsic Implementation 615 //===----------------------------------------------------------------------===// 616 617 CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC) { 618 std::vector<Record *> IntrProperties = 619 RC.getAllDerivedDefinitions("IntrinsicProperty"); 620 621 std::vector<Record *> DefaultProperties; 622 for (Record *Rec : IntrProperties) 623 if (Rec->getValueAsBit("IsDefault")) 624 DefaultProperties.push_back(Rec); 625 626 std::vector<Record *> Defs = RC.getAllDerivedDefinitions("Intrinsic"); 627 Intrinsics.reserve(Defs.size()); 628 629 for (unsigned I = 0, e = Defs.size(); I != e; ++I) 630 Intrinsics.push_back(CodeGenIntrinsic(Defs[I], DefaultProperties)); 631 632 llvm::sort(Intrinsics, 633 [](const CodeGenIntrinsic &LHS, const CodeGenIntrinsic &RHS) { 634 return std::tie(LHS.TargetPrefix, LHS.Name) < 635 std::tie(RHS.TargetPrefix, RHS.Name); 636 }); 637 Targets.push_back({"", 0, 0}); 638 for (size_t I = 0, E = Intrinsics.size(); I < E; ++I) 639 if (Intrinsics[I].TargetPrefix != Targets.back().Name) { 640 Targets.back().Count = I - Targets.back().Offset; 641 Targets.push_back({Intrinsics[I].TargetPrefix, I, 0}); 642 } 643 Targets.back().Count = Intrinsics.size() - Targets.back().Offset; 644 } 645 646 CodeGenIntrinsic::CodeGenIntrinsic(Record *R, 647 std::vector<Record *> DefaultProperties) { 648 TheDef = R; 649 std::string DefName = std::string(R->getName()); 650 ArrayRef<SMLoc> DefLoc = R->getLoc(); 651 ModRef = ReadWriteMem; 652 Properties = 0; 653 isOverloaded = false; 654 isCommutative = false; 655 canThrow = false; 656 isNoReturn = false; 657 isNoSync = false; 658 isNoFree = false; 659 isWillReturn = false; 660 isCold = false; 661 isNoDuplicate = false; 662 isConvergent = false; 663 isSpeculatable = false; 664 hasSideEffects = false; 665 666 if (DefName.size() <= 4 || 667 std::string(DefName.begin(), DefName.begin() + 4) != "int_") 668 PrintFatalError(DefLoc, 669 "Intrinsic '" + DefName + "' does not start with 'int_'!"); 670 671 EnumName = std::string(DefName.begin()+4, DefName.end()); 672 673 if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field. 674 GCCBuiltinName = std::string(R->getValueAsString("GCCBuiltinName")); 675 if (R->getValue("MSBuiltinName")) // Ignore a missing MSBuiltinName field. 676 MSBuiltinName = std::string(R->getValueAsString("MSBuiltinName")); 677 678 TargetPrefix = std::string(R->getValueAsString("TargetPrefix")); 679 Name = std::string(R->getValueAsString("LLVMName")); 680 681 if (Name == "") { 682 // If an explicit name isn't specified, derive one from the DefName. 683 Name = "llvm."; 684 685 for (unsigned i = 0, e = EnumName.size(); i != e; ++i) 686 Name += (EnumName[i] == '_') ? '.' : EnumName[i]; 687 } else { 688 // Verify it starts with "llvm.". 689 if (Name.size() <= 5 || 690 std::string(Name.begin(), Name.begin() + 5) != "llvm.") 691 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 692 "'s name does not start with 'llvm.'!"); 693 } 694 695 // If TargetPrefix is specified, make sure that Name starts with 696 // "llvm.<targetprefix>.". 697 if (!TargetPrefix.empty()) { 698 if (Name.size() < 6+TargetPrefix.size() || 699 std::string(Name.begin() + 5, Name.begin() + 6 + TargetPrefix.size()) 700 != (TargetPrefix + ".")) 701 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 702 "' does not start with 'llvm." + 703 TargetPrefix + ".'!"); 704 } 705 706 ListInit *RetTypes = R->getValueAsListInit("RetTypes"); 707 ListInit *ParamTypes = R->getValueAsListInit("ParamTypes"); 708 709 // First collate a list of overloaded types. 710 std::vector<MVT::SimpleValueType> OverloadedVTs; 711 for (ListInit *TypeList : {RetTypes, ParamTypes}) { 712 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 713 Record *TyEl = TypeList->getElementAsRecord(i); 714 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 715 716 if (TyEl->isSubClassOf("LLVMMatchType")) 717 continue; 718 719 MVT::SimpleValueType VT = getValueType(TyEl->getValueAsDef("VT")); 720 if (MVT(VT).isOverloaded()) { 721 OverloadedVTs.push_back(VT); 722 isOverloaded = true; 723 } 724 } 725 } 726 727 // Parse the list of return types. 728 ListInit *TypeList = RetTypes; 729 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 730 Record *TyEl = TypeList->getElementAsRecord(i); 731 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 732 MVT::SimpleValueType VT; 733 if (TyEl->isSubClassOf("LLVMMatchType")) { 734 unsigned MatchTy = TyEl->getValueAsInt("Number"); 735 assert(MatchTy < OverloadedVTs.size() && 736 "Invalid matching number!"); 737 VT = OverloadedVTs[MatchTy]; 738 // It only makes sense to use the extended and truncated vector element 739 // variants with iAny types; otherwise, if the intrinsic is not 740 // overloaded, all the types can be specified directly. 741 assert(((!TyEl->isSubClassOf("LLVMExtendedType") && 742 !TyEl->isSubClassOf("LLVMTruncatedType")) || 743 VT == MVT::iAny || VT == MVT::vAny) && 744 "Expected iAny or vAny type"); 745 } else { 746 VT = getValueType(TyEl->getValueAsDef("VT")); 747 } 748 749 // Reject invalid types. 750 if (VT == MVT::isVoid) 751 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 752 " has void in result type list!"); 753 754 IS.RetVTs.push_back(VT); 755 IS.RetTypeDefs.push_back(TyEl); 756 } 757 758 // Parse the list of parameter types. 759 TypeList = ParamTypes; 760 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 761 Record *TyEl = TypeList->getElementAsRecord(i); 762 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 763 MVT::SimpleValueType VT; 764 if (TyEl->isSubClassOf("LLVMMatchType")) { 765 unsigned MatchTy = TyEl->getValueAsInt("Number"); 766 if (MatchTy >= OverloadedVTs.size()) { 767 PrintError(R->getLoc(), 768 "Parameter #" + Twine(i) + " has out of bounds matching " 769 "number " + Twine(MatchTy)); 770 PrintFatalError(DefLoc, 771 Twine("ParamTypes is ") + TypeList->getAsString()); 772 } 773 VT = OverloadedVTs[MatchTy]; 774 // It only makes sense to use the extended and truncated vector element 775 // variants with iAny types; otherwise, if the intrinsic is not 776 // overloaded, all the types can be specified directly. 777 assert(((!TyEl->isSubClassOf("LLVMExtendedType") && 778 !TyEl->isSubClassOf("LLVMTruncatedType")) || 779 VT == MVT::iAny || VT == MVT::vAny) && 780 "Expected iAny or vAny type"); 781 } else 782 VT = getValueType(TyEl->getValueAsDef("VT")); 783 784 // Reject invalid types. 785 if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/) 786 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 787 " has void in result type list!"); 788 789 IS.ParamVTs.push_back(VT); 790 IS.ParamTypeDefs.push_back(TyEl); 791 } 792 793 // Parse the intrinsic properties. 794 ListInit *PropList = R->getValueAsListInit("IntrProperties"); 795 for (unsigned i = 0, e = PropList->size(); i != e; ++i) { 796 Record *Property = PropList->getElementAsRecord(i); 797 assert(Property->isSubClassOf("IntrinsicProperty") && 798 "Expected a property!"); 799 800 setProperty(Property); 801 } 802 803 // Set default properties to true. 804 setDefaultProperties(R, DefaultProperties); 805 806 // Also record the SDPatternOperator Properties. 807 Properties = parseSDPatternOperatorProperties(R); 808 809 // Sort the argument attributes for later benefit. 810 llvm::sort(ArgumentAttributes); 811 } 812 813 void CodeGenIntrinsic::setDefaultProperties( 814 Record *R, std::vector<Record *> DefaultProperties) { 815 // opt-out of using default attributes. 816 if (R->getValueAsBit("DisableDefaultAttributes")) 817 return; 818 819 for (Record *Rec : DefaultProperties) 820 setProperty(Rec); 821 } 822 823 void CodeGenIntrinsic::setProperty(Record *R) { 824 if (R->getName() == "IntrNoMem") 825 ModRef = NoMem; 826 else if (R->getName() == "IntrReadMem") { 827 if (!(ModRef & MR_Ref)) 828 PrintFatalError(TheDef->getLoc(), 829 Twine("IntrReadMem cannot be used after IntrNoMem or " 830 "IntrWriteMem. Default is ReadWrite")); 831 ModRef = ModRefBehavior(ModRef & ~MR_Mod); 832 } else if (R->getName() == "IntrWriteMem") { 833 if (!(ModRef & MR_Mod)) 834 PrintFatalError(TheDef->getLoc(), 835 Twine("IntrWriteMem cannot be used after IntrNoMem or " 836 "IntrReadMem. Default is ReadWrite")); 837 ModRef = ModRefBehavior(ModRef & ~MR_Ref); 838 } else if (R->getName() == "IntrArgMemOnly") 839 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem); 840 else if (R->getName() == "IntrInaccessibleMemOnly") 841 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_InaccessibleMem); 842 else if (R->getName() == "IntrInaccessibleMemOrArgMemOnly") 843 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem | 844 MR_InaccessibleMem); 845 else if (R->getName() == "Commutative") 846 isCommutative = true; 847 else if (R->getName() == "Throws") 848 canThrow = true; 849 else if (R->getName() == "IntrNoDuplicate") 850 isNoDuplicate = true; 851 else if (R->getName() == "IntrConvergent") 852 isConvergent = true; 853 else if (R->getName() == "IntrNoReturn") 854 isNoReturn = true; 855 else if (R->getName() == "IntrNoSync") 856 isNoSync = true; 857 else if (R->getName() == "IntrNoFree") 858 isNoFree = true; 859 else if (R->getName() == "IntrWillReturn") 860 isWillReturn = !isNoReturn; 861 else if (R->getName() == "IntrCold") 862 isCold = true; 863 else if (R->getName() == "IntrSpeculatable") 864 isSpeculatable = true; 865 else if (R->getName() == "IntrHasSideEffects") 866 hasSideEffects = true; 867 else if (R->isSubClassOf("NoCapture")) { 868 unsigned ArgNo = R->getValueAsInt("ArgNo"); 869 ArgumentAttributes.emplace_back(ArgNo, NoCapture, 0); 870 } else if (R->isSubClassOf("NoAlias")) { 871 unsigned ArgNo = R->getValueAsInt("ArgNo"); 872 ArgumentAttributes.emplace_back(ArgNo, NoAlias, 0); 873 } else if (R->isSubClassOf("NoUndef")) { 874 unsigned ArgNo = R->getValueAsInt("ArgNo"); 875 ArgumentAttributes.emplace_back(ArgNo, NoUndef, 0); 876 } else if (R->isSubClassOf("Returned")) { 877 unsigned ArgNo = R->getValueAsInt("ArgNo"); 878 ArgumentAttributes.emplace_back(ArgNo, Returned, 0); 879 } else if (R->isSubClassOf("ReadOnly")) { 880 unsigned ArgNo = R->getValueAsInt("ArgNo"); 881 ArgumentAttributes.emplace_back(ArgNo, ReadOnly, 0); 882 } else if (R->isSubClassOf("WriteOnly")) { 883 unsigned ArgNo = R->getValueAsInt("ArgNo"); 884 ArgumentAttributes.emplace_back(ArgNo, WriteOnly, 0); 885 } else if (R->isSubClassOf("ReadNone")) { 886 unsigned ArgNo = R->getValueAsInt("ArgNo"); 887 ArgumentAttributes.emplace_back(ArgNo, ReadNone, 0); 888 } else if (R->isSubClassOf("ImmArg")) { 889 unsigned ArgNo = R->getValueAsInt("ArgNo"); 890 ArgumentAttributes.emplace_back(ArgNo, ImmArg, 0); 891 } else if (R->isSubClassOf("Align")) { 892 unsigned ArgNo = R->getValueAsInt("ArgNo"); 893 uint64_t Align = R->getValueAsInt("Align"); 894 ArgumentAttributes.emplace_back(ArgNo, Alignment, Align); 895 } else 896 llvm_unreachable("Unknown property!"); 897 } 898 899 bool CodeGenIntrinsic::isParamAPointer(unsigned ParamIdx) const { 900 if (ParamIdx >= IS.ParamVTs.size()) 901 return false; 902 MVT ParamType = MVT(IS.ParamVTs[ParamIdx]); 903 return ParamType == MVT::iPTR || ParamType == MVT::iPTRAny; 904 } 905 906 bool CodeGenIntrinsic::isParamImmArg(unsigned ParamIdx) const { 907 // Convert argument index to attribute index starting from `FirstArgIndex`. 908 ArgAttribute Val{ParamIdx + 1, ImmArg, 0}; 909 return std::binary_search(ArgumentAttributes.begin(), 910 ArgumentAttributes.end(), Val); 911 } 912