1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This class wraps target description classes used by the various code 10 // generation TableGen backends. This makes it easier to access the data and 11 // provides a single place that needs to check it for validity. All of these 12 // classes abort on error conditions. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "CodeGenTarget.h" 17 #include "CodeGenDAGPatterns.h" 18 #include "CodeGenIntrinsics.h" 19 #include "CodeGenSchedule.h" 20 #include "llvm/ADT/STLExtras.h" 21 #include "llvm/ADT/StringExtras.h" 22 #include "llvm/Support/CommandLine.h" 23 #include "llvm/Support/Timer.h" 24 #include "llvm/TableGen/Error.h" 25 #include "llvm/TableGen/Record.h" 26 #include "llvm/TableGen/TableGenBackend.h" 27 #include <algorithm> 28 using namespace llvm; 29 30 cl::OptionCategory AsmParserCat("Options for -gen-asm-parser"); 31 cl::OptionCategory AsmWriterCat("Options for -gen-asm-writer"); 32 33 static cl::opt<unsigned> 34 AsmParserNum("asmparsernum", cl::init(0), 35 cl::desc("Make -gen-asm-parser emit assembly parser #N"), 36 cl::cat(AsmParserCat)); 37 38 static cl::opt<unsigned> 39 AsmWriterNum("asmwriternum", cl::init(0), 40 cl::desc("Make -gen-asm-writer emit assembly writer #N"), 41 cl::cat(AsmWriterCat)); 42 43 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen 44 /// record corresponds to. 45 MVT::SimpleValueType llvm::getValueType(Record *Rec) { 46 return (MVT::SimpleValueType)Rec->getValueAsInt("Value"); 47 } 48 49 StringRef llvm::getName(MVT::SimpleValueType T) { 50 switch (T) { 51 case MVT::Other: return "UNKNOWN"; 52 case MVT::iPTR: return "TLI.getPointerTy()"; 53 case MVT::iPTRAny: return "TLI.getPointerTy()"; 54 default: return getEnumName(T); 55 } 56 } 57 58 StringRef llvm::getEnumName(MVT::SimpleValueType T) { 59 switch (T) { 60 case MVT::Other: return "MVT::Other"; 61 case MVT::i1: return "MVT::i1"; 62 case MVT::i8: return "MVT::i8"; 63 case MVT::i16: return "MVT::i16"; 64 case MVT::i32: return "MVT::i32"; 65 case MVT::i64: return "MVT::i64"; 66 case MVT::i128: return "MVT::i128"; 67 case MVT::Any: return "MVT::Any"; 68 case MVT::iAny: return "MVT::iAny"; 69 case MVT::fAny: return "MVT::fAny"; 70 case MVT::vAny: return "MVT::vAny"; 71 case MVT::f16: return "MVT::f16"; 72 case MVT::bf16: return "MVT::bf16"; 73 case MVT::f32: return "MVT::f32"; 74 case MVT::f64: return "MVT::f64"; 75 case MVT::f80: return "MVT::f80"; 76 case MVT::f128: return "MVT::f128"; 77 case MVT::ppcf128: return "MVT::ppcf128"; 78 case MVT::x86mmx: return "MVT::x86mmx"; 79 case MVT::Glue: return "MVT::Glue"; 80 case MVT::isVoid: return "MVT::isVoid"; 81 case MVT::v1i1: return "MVT::v1i1"; 82 case MVT::v2i1: return "MVT::v2i1"; 83 case MVT::v4i1: return "MVT::v4i1"; 84 case MVT::v8i1: return "MVT::v8i1"; 85 case MVT::v16i1: return "MVT::v16i1"; 86 case MVT::v32i1: return "MVT::v32i1"; 87 case MVT::v64i1: return "MVT::v64i1"; 88 case MVT::v128i1: return "MVT::v128i1"; 89 case MVT::v256i1: return "MVT::v256i1"; 90 case MVT::v512i1: return "MVT::v512i1"; 91 case MVT::v1024i1: return "MVT::v1024i1"; 92 case MVT::v1i8: return "MVT::v1i8"; 93 case MVT::v2i8: return "MVT::v2i8"; 94 case MVT::v4i8: return "MVT::v4i8"; 95 case MVT::v8i8: return "MVT::v8i8"; 96 case MVT::v16i8: return "MVT::v16i8"; 97 case MVT::v32i8: return "MVT::v32i8"; 98 case MVT::v64i8: return "MVT::v64i8"; 99 case MVT::v128i8: return "MVT::v128i8"; 100 case MVT::v256i8: return "MVT::v256i8"; 101 case MVT::v1i16: return "MVT::v1i16"; 102 case MVT::v2i16: return "MVT::v2i16"; 103 case MVT::v3i16: return "MVT::v3i16"; 104 case MVT::v4i16: return "MVT::v4i16"; 105 case MVT::v8i16: return "MVT::v8i16"; 106 case MVT::v16i16: return "MVT::v16i16"; 107 case MVT::v32i16: return "MVT::v32i16"; 108 case MVT::v64i16: return "MVT::v64i16"; 109 case MVT::v128i16: return "MVT::v128i16"; 110 case MVT::v1i32: return "MVT::v1i32"; 111 case MVT::v2i32: return "MVT::v2i32"; 112 case MVT::v3i32: return "MVT::v3i32"; 113 case MVT::v4i32: return "MVT::v4i32"; 114 case MVT::v5i32: return "MVT::v5i32"; 115 case MVT::v8i32: return "MVT::v8i32"; 116 case MVT::v16i32: return "MVT::v16i32"; 117 case MVT::v32i32: return "MVT::v32i32"; 118 case MVT::v64i32: return "MVT::v64i32"; 119 case MVT::v128i32: return "MVT::v128i32"; 120 case MVT::v256i32: return "MVT::v256i32"; 121 case MVT::v512i32: return "MVT::v512i32"; 122 case MVT::v1024i32: return "MVT::v1024i32"; 123 case MVT::v2048i32: return "MVT::v2048i32"; 124 case MVT::v1i64: return "MVT::v1i64"; 125 case MVT::v2i64: return "MVT::v2i64"; 126 case MVT::v4i64: return "MVT::v4i64"; 127 case MVT::v8i64: return "MVT::v8i64"; 128 case MVT::v16i64: return "MVT::v16i64"; 129 case MVT::v32i64: return "MVT::v32i64"; 130 case MVT::v64i64: return "MVT::v64i64"; 131 case MVT::v128i64: return "MVT::v128i64"; 132 case MVT::v256i64: return "MVT::v256i64"; 133 case MVT::v1i128: return "MVT::v1i128"; 134 case MVT::v2f16: return "MVT::v2f16"; 135 case MVT::v3f16: return "MVT::v3f16"; 136 case MVT::v4f16: return "MVT::v4f16"; 137 case MVT::v8f16: return "MVT::v8f16"; 138 case MVT::v16f16: return "MVT::v16f16"; 139 case MVT::v32f16: return "MVT::v32f16"; 140 case MVT::v64f16: return "MVT::v64f16"; 141 case MVT::v128f16: return "MVT::v128f16"; 142 case MVT::v2bf16: return "MVT::v2bf16"; 143 case MVT::v3bf16: return "MVT::v3bf16"; 144 case MVT::v4bf16: return "MVT::v4bf16"; 145 case MVT::v8bf16: return "MVT::v8bf16"; 146 case MVT::v16bf16: return "MVT::v16bf16"; 147 case MVT::v32bf16: return "MVT::v32bf16"; 148 case MVT::v64bf16: return "MVT::v64bf16"; 149 case MVT::v128bf16: return "MVT::v128bf16"; 150 case MVT::v1f32: return "MVT::v1f32"; 151 case MVT::v2f32: return "MVT::v2f32"; 152 case MVT::v3f32: return "MVT::v3f32"; 153 case MVT::v4f32: return "MVT::v4f32"; 154 case MVT::v5f32: return "MVT::v5f32"; 155 case MVT::v8f32: return "MVT::v8f32"; 156 case MVT::v16f32: return "MVT::v16f32"; 157 case MVT::v32f32: return "MVT::v32f32"; 158 case MVT::v64f32: return "MVT::v64f32"; 159 case MVT::v128f32: return "MVT::v128f32"; 160 case MVT::v256f32: return "MVT::v256f32"; 161 case MVT::v512f32: return "MVT::v512f32"; 162 case MVT::v1024f32: return "MVT::v1024f32"; 163 case MVT::v2048f32: return "MVT::v2048f32"; 164 case MVT::v1f64: return "MVT::v1f64"; 165 case MVT::v2f64: return "MVT::v2f64"; 166 case MVT::v4f64: return "MVT::v4f64"; 167 case MVT::v8f64: return "MVT::v8f64"; 168 case MVT::v16f64: return "MVT::v16f64"; 169 case MVT::v32f64: return "MVT::v32f64"; 170 case MVT::v64f64: return "MVT::v64f64"; 171 case MVT::v128f64: return "MVT::v128f64"; 172 case MVT::v256f64: return "MVT::v256f64"; 173 case MVT::nxv1i1: return "MVT::nxv1i1"; 174 case MVT::nxv2i1: return "MVT::nxv2i1"; 175 case MVT::nxv4i1: return "MVT::nxv4i1"; 176 case MVT::nxv8i1: return "MVT::nxv8i1"; 177 case MVT::nxv16i1: return "MVT::nxv16i1"; 178 case MVT::nxv32i1: return "MVT::nxv32i1"; 179 case MVT::nxv64i1: return "MVT::nxv64i1"; 180 case MVT::nxv1i8: return "MVT::nxv1i8"; 181 case MVT::nxv2i8: return "MVT::nxv2i8"; 182 case MVT::nxv4i8: return "MVT::nxv4i8"; 183 case MVT::nxv8i8: return "MVT::nxv8i8"; 184 case MVT::nxv16i8: return "MVT::nxv16i8"; 185 case MVT::nxv32i8: return "MVT::nxv32i8"; 186 case MVT::nxv64i8: return "MVT::nxv64i8"; 187 case MVT::nxv1i16: return "MVT::nxv1i16"; 188 case MVT::nxv2i16: return "MVT::nxv2i16"; 189 case MVT::nxv4i16: return "MVT::nxv4i16"; 190 case MVT::nxv8i16: return "MVT::nxv8i16"; 191 case MVT::nxv16i16: return "MVT::nxv16i16"; 192 case MVT::nxv32i16: return "MVT::nxv32i16"; 193 case MVT::nxv1i32: return "MVT::nxv1i32"; 194 case MVT::nxv2i32: return "MVT::nxv2i32"; 195 case MVT::nxv4i32: return "MVT::nxv4i32"; 196 case MVT::nxv8i32: return "MVT::nxv8i32"; 197 case MVT::nxv16i32: return "MVT::nxv16i32"; 198 case MVT::nxv32i32: return "MVT::nxv32i32"; 199 case MVT::nxv1i64: return "MVT::nxv1i64"; 200 case MVT::nxv2i64: return "MVT::nxv2i64"; 201 case MVT::nxv4i64: return "MVT::nxv4i64"; 202 case MVT::nxv8i64: return "MVT::nxv8i64"; 203 case MVT::nxv16i64: return "MVT::nxv16i64"; 204 case MVT::nxv32i64: return "MVT::nxv32i64"; 205 case MVT::nxv1f16: return "MVT::nxv1f16"; 206 case MVT::nxv2f16: return "MVT::nxv2f16"; 207 case MVT::nxv4f16: return "MVT::nxv4f16"; 208 case MVT::nxv8f16: return "MVT::nxv8f16"; 209 case MVT::nxv16f16: return "MVT::nxv16f16"; 210 case MVT::nxv32f16: return "MVT::nxv32f16"; 211 case MVT::nxv2bf16: return "MVT::nxv2bf16"; 212 case MVT::nxv4bf16: return "MVT::nxv4bf16"; 213 case MVT::nxv8bf16: return "MVT::nxv8bf16"; 214 case MVT::nxv1f32: return "MVT::nxv1f32"; 215 case MVT::nxv2f32: return "MVT::nxv2f32"; 216 case MVT::nxv4f32: return "MVT::nxv4f32"; 217 case MVT::nxv8f32: return "MVT::nxv8f32"; 218 case MVT::nxv16f32: return "MVT::nxv16f32"; 219 case MVT::nxv1f64: return "MVT::nxv1f64"; 220 case MVT::nxv2f64: return "MVT::nxv2f64"; 221 case MVT::nxv4f64: return "MVT::nxv4f64"; 222 case MVT::nxv8f64: return "MVT::nxv8f64"; 223 case MVT::token: return "MVT::token"; 224 case MVT::Metadata: return "MVT::Metadata"; 225 case MVT::iPTR: return "MVT::iPTR"; 226 case MVT::iPTRAny: return "MVT::iPTRAny"; 227 case MVT::Untyped: return "MVT::Untyped"; 228 case MVT::exnref: return "MVT::exnref"; 229 case MVT::funcref: return "MVT::funcref"; 230 case MVT::externref: return "MVT::externref"; 231 default: llvm_unreachable("ILLEGAL VALUE TYPE!"); 232 } 233 } 234 235 /// getQualifiedName - Return the name of the specified record, with a 236 /// namespace qualifier if the record contains one. 237 /// 238 std::string llvm::getQualifiedName(const Record *R) { 239 std::string Namespace; 240 if (R->getValue("Namespace")) 241 Namespace = std::string(R->getValueAsString("Namespace")); 242 if (Namespace.empty()) 243 return std::string(R->getName()); 244 return Namespace + "::" + R->getName().str(); 245 } 246 247 248 /// getTarget - Return the current instance of the Target class. 249 /// 250 CodeGenTarget::CodeGenTarget(RecordKeeper &records) 251 : Records(records), CGH(records) { 252 std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target"); 253 if (Targets.size() == 0) 254 PrintFatalError("ERROR: No 'Target' subclasses defined!"); 255 if (Targets.size() != 1) 256 PrintFatalError("ERROR: Multiple subclasses of Target defined!"); 257 TargetRec = Targets[0]; 258 } 259 260 CodeGenTarget::~CodeGenTarget() { 261 } 262 263 const StringRef CodeGenTarget::getName() const { 264 return TargetRec->getName(); 265 } 266 267 StringRef CodeGenTarget::getInstNamespace() const { 268 for (const CodeGenInstruction *Inst : getInstructionsByEnumValue()) { 269 // Make sure not to pick up "TargetOpcode" by accidentally getting 270 // the namespace off the PHI instruction or something. 271 if (Inst->Namespace != "TargetOpcode") 272 return Inst->Namespace; 273 } 274 275 return ""; 276 } 277 278 StringRef CodeGenTarget::getRegNamespace() const { 279 auto &RegClasses = RegBank->getRegClasses(); 280 return RegClasses.size() > 0 ? RegClasses.front().Namespace : ""; 281 } 282 283 Record *CodeGenTarget::getInstructionSet() const { 284 return TargetRec->getValueAsDef("InstructionSet"); 285 } 286 287 bool CodeGenTarget::getAllowRegisterRenaming() const { 288 return TargetRec->getValueAsInt("AllowRegisterRenaming"); 289 } 290 291 /// getAsmParser - Return the AssemblyParser definition for this target. 292 /// 293 Record *CodeGenTarget::getAsmParser() const { 294 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers"); 295 if (AsmParserNum >= LI.size()) 296 PrintFatalError("Target does not have an AsmParser #" + 297 Twine(AsmParserNum) + "!"); 298 return LI[AsmParserNum]; 299 } 300 301 /// getAsmParserVariant - Return the AssemblyParserVariant definition for 302 /// this target. 303 /// 304 Record *CodeGenTarget::getAsmParserVariant(unsigned i) const { 305 std::vector<Record*> LI = 306 TargetRec->getValueAsListOfDefs("AssemblyParserVariants"); 307 if (i >= LI.size()) 308 PrintFatalError("Target does not have an AsmParserVariant #" + Twine(i) + 309 "!"); 310 return LI[i]; 311 } 312 313 /// getAsmParserVariantCount - Return the AssemblyParserVariant definition 314 /// available for this target. 315 /// 316 unsigned CodeGenTarget::getAsmParserVariantCount() const { 317 std::vector<Record*> LI = 318 TargetRec->getValueAsListOfDefs("AssemblyParserVariants"); 319 return LI.size(); 320 } 321 322 /// getAsmWriter - Return the AssemblyWriter definition for this target. 323 /// 324 Record *CodeGenTarget::getAsmWriter() const { 325 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters"); 326 if (AsmWriterNum >= LI.size()) 327 PrintFatalError("Target does not have an AsmWriter #" + 328 Twine(AsmWriterNum) + "!"); 329 return LI[AsmWriterNum]; 330 } 331 332 CodeGenRegBank &CodeGenTarget::getRegBank() const { 333 if (!RegBank) 334 RegBank = std::make_unique<CodeGenRegBank>(Records, getHwModes()); 335 return *RegBank; 336 } 337 338 Optional<CodeGenRegisterClass *> 339 CodeGenTarget::getSuperRegForSubReg(const ValueTypeByHwMode &ValueTy, 340 CodeGenRegBank &RegBank, 341 const CodeGenSubRegIndex *SubIdx) const { 342 std::vector<CodeGenRegisterClass *> Candidates; 343 auto &RegClasses = RegBank.getRegClasses(); 344 345 // Try to find a register class which supports ValueTy, and also contains 346 // SubIdx. 347 for (CodeGenRegisterClass &RC : RegClasses) { 348 // Is there a subclass of this class which contains this subregister index? 349 CodeGenRegisterClass *SubClassWithSubReg = RC.getSubClassWithSubReg(SubIdx); 350 if (!SubClassWithSubReg) 351 continue; 352 353 // We have a class. Check if it supports this value type. 354 if (llvm::none_of(SubClassWithSubReg->VTs, 355 [&ValueTy](const ValueTypeByHwMode &ClassVT) { 356 return ClassVT == ValueTy; 357 })) 358 continue; 359 360 // We have a register class which supports both the value type and 361 // subregister index. Remember it. 362 Candidates.push_back(SubClassWithSubReg); 363 } 364 365 // If we didn't find anything, we're done. 366 if (Candidates.empty()) 367 return None; 368 369 // Find and return the largest of our candidate classes. 370 llvm::stable_sort(Candidates, [&](const CodeGenRegisterClass *A, 371 const CodeGenRegisterClass *B) { 372 if (A->getMembers().size() > B->getMembers().size()) 373 return true; 374 375 if (A->getMembers().size() < B->getMembers().size()) 376 return false; 377 378 // Order by name as a tie-breaker. 379 return StringRef(A->getName()) < B->getName(); 380 }); 381 382 return Candidates[0]; 383 } 384 385 void CodeGenTarget::ReadRegAltNameIndices() const { 386 RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex"); 387 llvm::sort(RegAltNameIndices, LessRecord()); 388 } 389 390 /// getRegisterByName - If there is a register with the specific AsmName, 391 /// return it. 392 const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const { 393 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName(); 394 StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name); 395 if (I == Regs.end()) 396 return nullptr; 397 return I->second; 398 } 399 400 std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R) 401 const { 402 const CodeGenRegister *Reg = getRegBank().getReg(R); 403 std::vector<ValueTypeByHwMode> Result; 404 for (const auto &RC : getRegBank().getRegClasses()) { 405 if (RC.contains(Reg)) { 406 ArrayRef<ValueTypeByHwMode> InVTs = RC.getValueTypes(); 407 Result.insert(Result.end(), InVTs.begin(), InVTs.end()); 408 } 409 } 410 411 // Remove duplicates. 412 llvm::sort(Result); 413 Result.erase(std::unique(Result.begin(), Result.end()), Result.end()); 414 return Result; 415 } 416 417 418 void CodeGenTarget::ReadLegalValueTypes() const { 419 for (const auto &RC : getRegBank().getRegClasses()) 420 LegalValueTypes.insert(LegalValueTypes.end(), RC.VTs.begin(), RC.VTs.end()); 421 422 // Remove duplicates. 423 llvm::sort(LegalValueTypes); 424 LegalValueTypes.erase(std::unique(LegalValueTypes.begin(), 425 LegalValueTypes.end()), 426 LegalValueTypes.end()); 427 } 428 429 CodeGenSchedModels &CodeGenTarget::getSchedModels() const { 430 if (!SchedModels) 431 SchedModels = std::make_unique<CodeGenSchedModels>(Records, *this); 432 return *SchedModels; 433 } 434 435 void CodeGenTarget::ReadInstructions() const { 436 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction"); 437 if (Insts.size() <= 2) 438 PrintFatalError("No 'Instruction' subclasses defined!"); 439 440 // Parse the instructions defined in the .td file. 441 for (unsigned i = 0, e = Insts.size(); i != e; ++i) 442 Instructions[Insts[i]] = std::make_unique<CodeGenInstruction>(Insts[i]); 443 } 444 445 static const CodeGenInstruction * 446 GetInstByName(const char *Name, 447 const DenseMap<const Record*, 448 std::unique_ptr<CodeGenInstruction>> &Insts, 449 RecordKeeper &Records) { 450 const Record *Rec = Records.getDef(Name); 451 452 const auto I = Insts.find(Rec); 453 if (!Rec || I == Insts.end()) 454 PrintFatalError(Twine("Could not find '") + Name + "' instruction!"); 455 return I->second.get(); 456 } 457 458 static const char *const FixedInstrs[] = { 459 #define HANDLE_TARGET_OPCODE(OPC) #OPC, 460 #include "llvm/Support/TargetOpcodes.def" 461 nullptr}; 462 463 unsigned CodeGenTarget::getNumFixedInstructions() { 464 return array_lengthof(FixedInstrs) - 1; 465 } 466 467 /// Return all of the instructions defined by the target, ordered by 468 /// their enum value. 469 void CodeGenTarget::ComputeInstrsByEnum() const { 470 const auto &Insts = getInstructions(); 471 for (const char *const *p = FixedInstrs; *p; ++p) { 472 const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records); 473 assert(Instr && "Missing target independent instruction"); 474 assert(Instr->Namespace == "TargetOpcode" && "Bad namespace"); 475 InstrsByEnum.push_back(Instr); 476 } 477 unsigned EndOfPredefines = InstrsByEnum.size(); 478 assert(EndOfPredefines == getNumFixedInstructions() && 479 "Missing generic opcode"); 480 481 for (const auto &I : Insts) { 482 const CodeGenInstruction *CGI = I.second.get(); 483 if (CGI->Namespace != "TargetOpcode") { 484 InstrsByEnum.push_back(CGI); 485 if (CGI->TheDef->getValueAsBit("isPseudo")) 486 ++NumPseudoInstructions; 487 } 488 } 489 490 assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr"); 491 492 // All of the instructions are now in random order based on the map iteration. 493 llvm::sort( 494 InstrsByEnum.begin() + EndOfPredefines, InstrsByEnum.end(), 495 [](const CodeGenInstruction *Rec1, const CodeGenInstruction *Rec2) { 496 const auto &D1 = *Rec1->TheDef; 497 const auto &D2 = *Rec2->TheDef; 498 return std::make_tuple(!D1.getValueAsBit("isPseudo"), D1.getName()) < 499 std::make_tuple(!D2.getValueAsBit("isPseudo"), D2.getName()); 500 }); 501 } 502 503 504 /// isLittleEndianEncoding - Return whether this target encodes its instruction 505 /// in little-endian format, i.e. bits laid out in the order [0..n] 506 /// 507 bool CodeGenTarget::isLittleEndianEncoding() const { 508 return getInstructionSet()->getValueAsBit("isLittleEndianEncoding"); 509 } 510 511 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit 512 /// encodings, reverse the bit order of all instructions. 513 void CodeGenTarget::reverseBitsForLittleEndianEncoding() { 514 if (!isLittleEndianEncoding()) 515 return; 516 517 std::vector<Record *> Insts = 518 Records.getAllDerivedDefinitions("InstructionEncoding"); 519 for (Record *R : Insts) { 520 if (R->getValueAsString("Namespace") == "TargetOpcode" || 521 R->getValueAsBit("isPseudo")) 522 continue; 523 524 BitsInit *BI = R->getValueAsBitsInit("Inst"); 525 526 unsigned numBits = BI->getNumBits(); 527 528 SmallVector<Init *, 16> NewBits(numBits); 529 530 for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) { 531 unsigned bitSwapIdx = numBits - bit - 1; 532 Init *OrigBit = BI->getBit(bit); 533 Init *BitSwap = BI->getBit(bitSwapIdx); 534 NewBits[bit] = BitSwap; 535 NewBits[bitSwapIdx] = OrigBit; 536 } 537 if (numBits % 2) { 538 unsigned middle = (numBits + 1) / 2; 539 NewBits[middle] = BI->getBit(middle); 540 } 541 542 BitsInit *NewBI = BitsInit::get(NewBits); 543 544 // Update the bits in reversed order so that emitInstrOpBits will get the 545 // correct endianness. 546 R->getValue("Inst")->setValue(NewBI); 547 } 548 } 549 550 /// guessInstructionProperties - Return true if it's OK to guess instruction 551 /// properties instead of raising an error. 552 /// 553 /// This is configurable as a temporary migration aid. It will eventually be 554 /// permanently false. 555 bool CodeGenTarget::guessInstructionProperties() const { 556 return getInstructionSet()->getValueAsBit("guessInstructionProperties"); 557 } 558 559 //===----------------------------------------------------------------------===// 560 // ComplexPattern implementation 561 // 562 ComplexPattern::ComplexPattern(Record *R) { 563 Ty = ::getValueType(R->getValueAsDef("Ty")); 564 NumOperands = R->getValueAsInt("NumOperands"); 565 SelectFunc = std::string(R->getValueAsString("SelectFunc")); 566 RootNodes = R->getValueAsListOfDefs("RootNodes"); 567 568 // FIXME: This is a hack to statically increase the priority of patterns which 569 // maps a sub-dag to a complex pattern. e.g. favors LEA over ADD. To get best 570 // possible pattern match we'll need to dynamically calculate the complexity 571 // of all patterns a dag can potentially map to. 572 int64_t RawComplexity = R->getValueAsInt("Complexity"); 573 if (RawComplexity == -1) 574 Complexity = NumOperands * 3; 575 else 576 Complexity = RawComplexity; 577 578 // FIXME: Why is this different from parseSDPatternOperatorProperties? 579 // Parse the properties. 580 Properties = 0; 581 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties"); 582 for (unsigned i = 0, e = PropList.size(); i != e; ++i) 583 if (PropList[i]->getName() == "SDNPHasChain") { 584 Properties |= 1 << SDNPHasChain; 585 } else if (PropList[i]->getName() == "SDNPOptInGlue") { 586 Properties |= 1 << SDNPOptInGlue; 587 } else if (PropList[i]->getName() == "SDNPMayStore") { 588 Properties |= 1 << SDNPMayStore; 589 } else if (PropList[i]->getName() == "SDNPMayLoad") { 590 Properties |= 1 << SDNPMayLoad; 591 } else if (PropList[i]->getName() == "SDNPSideEffect") { 592 Properties |= 1 << SDNPSideEffect; 593 } else if (PropList[i]->getName() == "SDNPMemOperand") { 594 Properties |= 1 << SDNPMemOperand; 595 } else if (PropList[i]->getName() == "SDNPVariadic") { 596 Properties |= 1 << SDNPVariadic; 597 } else if (PropList[i]->getName() == "SDNPWantRoot") { 598 Properties |= 1 << SDNPWantRoot; 599 } else if (PropList[i]->getName() == "SDNPWantParent") { 600 Properties |= 1 << SDNPWantParent; 601 } else { 602 PrintFatalError(R->getLoc(), "Unsupported SD Node property '" + 603 PropList[i]->getName() + 604 "' on ComplexPattern '" + R->getName() + 605 "'!"); 606 } 607 } 608 609 //===----------------------------------------------------------------------===// 610 // CodeGenIntrinsic Implementation 611 //===----------------------------------------------------------------------===// 612 613 CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC) { 614 std::vector<Record *> IntrProperties = 615 RC.getAllDerivedDefinitions("IntrinsicProperty"); 616 617 std::vector<Record *> DefaultProperties; 618 for (Record *Rec : IntrProperties) 619 if (Rec->getValueAsBit("IsDefault")) 620 DefaultProperties.push_back(Rec); 621 622 std::vector<Record *> Defs = RC.getAllDerivedDefinitions("Intrinsic"); 623 Intrinsics.reserve(Defs.size()); 624 625 for (unsigned I = 0, e = Defs.size(); I != e; ++I) 626 Intrinsics.push_back(CodeGenIntrinsic(Defs[I], DefaultProperties)); 627 628 llvm::sort(Intrinsics, 629 [](const CodeGenIntrinsic &LHS, const CodeGenIntrinsic &RHS) { 630 return std::tie(LHS.TargetPrefix, LHS.Name) < 631 std::tie(RHS.TargetPrefix, RHS.Name); 632 }); 633 Targets.push_back({"", 0, 0}); 634 for (size_t I = 0, E = Intrinsics.size(); I < E; ++I) 635 if (Intrinsics[I].TargetPrefix != Targets.back().Name) { 636 Targets.back().Count = I - Targets.back().Offset; 637 Targets.push_back({Intrinsics[I].TargetPrefix, I, 0}); 638 } 639 Targets.back().Count = Intrinsics.size() - Targets.back().Offset; 640 } 641 642 CodeGenIntrinsic::CodeGenIntrinsic(Record *R, 643 std::vector<Record *> DefaultProperties) { 644 TheDef = R; 645 std::string DefName = std::string(R->getName()); 646 ArrayRef<SMLoc> DefLoc = R->getLoc(); 647 ModRef = ReadWriteMem; 648 Properties = 0; 649 isOverloaded = false; 650 isCommutative = false; 651 canThrow = false; 652 isNoReturn = false; 653 isNoSync = false; 654 isNoFree = false; 655 isWillReturn = false; 656 isCold = false; 657 isNoDuplicate = false; 658 isConvergent = false; 659 isSpeculatable = false; 660 hasSideEffects = false; 661 662 if (DefName.size() <= 4 || 663 std::string(DefName.begin(), DefName.begin() + 4) != "int_") 664 PrintFatalError(DefLoc, 665 "Intrinsic '" + DefName + "' does not start with 'int_'!"); 666 667 EnumName = std::string(DefName.begin()+4, DefName.end()); 668 669 if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field. 670 GCCBuiltinName = std::string(R->getValueAsString("GCCBuiltinName")); 671 if (R->getValue("MSBuiltinName")) // Ignore a missing MSBuiltinName field. 672 MSBuiltinName = std::string(R->getValueAsString("MSBuiltinName")); 673 674 TargetPrefix = std::string(R->getValueAsString("TargetPrefix")); 675 Name = std::string(R->getValueAsString("LLVMName")); 676 677 if (Name == "") { 678 // If an explicit name isn't specified, derive one from the DefName. 679 Name = "llvm."; 680 681 for (unsigned i = 0, e = EnumName.size(); i != e; ++i) 682 Name += (EnumName[i] == '_') ? '.' : EnumName[i]; 683 } else { 684 // Verify it starts with "llvm.". 685 if (Name.size() <= 5 || 686 std::string(Name.begin(), Name.begin() + 5) != "llvm.") 687 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 688 "'s name does not start with 'llvm.'!"); 689 } 690 691 // If TargetPrefix is specified, make sure that Name starts with 692 // "llvm.<targetprefix>.". 693 if (!TargetPrefix.empty()) { 694 if (Name.size() < 6+TargetPrefix.size() || 695 std::string(Name.begin() + 5, Name.begin() + 6 + TargetPrefix.size()) 696 != (TargetPrefix + ".")) 697 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 698 "' does not start with 'llvm." + 699 TargetPrefix + ".'!"); 700 } 701 702 ListInit *RetTypes = R->getValueAsListInit("RetTypes"); 703 ListInit *ParamTypes = R->getValueAsListInit("ParamTypes"); 704 705 // First collate a list of overloaded types. 706 std::vector<MVT::SimpleValueType> OverloadedVTs; 707 for (ListInit *TypeList : {RetTypes, ParamTypes}) { 708 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 709 Record *TyEl = TypeList->getElementAsRecord(i); 710 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 711 712 if (TyEl->isSubClassOf("LLVMMatchType")) 713 continue; 714 715 MVT::SimpleValueType VT = getValueType(TyEl->getValueAsDef("VT")); 716 if (MVT(VT).isOverloaded()) { 717 OverloadedVTs.push_back(VT); 718 isOverloaded = true; 719 } 720 } 721 } 722 723 // Parse the list of return types. 724 ListInit *TypeList = RetTypes; 725 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 726 Record *TyEl = TypeList->getElementAsRecord(i); 727 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 728 MVT::SimpleValueType VT; 729 if (TyEl->isSubClassOf("LLVMMatchType")) { 730 unsigned MatchTy = TyEl->getValueAsInt("Number"); 731 assert(MatchTy < OverloadedVTs.size() && 732 "Invalid matching number!"); 733 VT = OverloadedVTs[MatchTy]; 734 // It only makes sense to use the extended and truncated vector element 735 // variants with iAny types; otherwise, if the intrinsic is not 736 // overloaded, all the types can be specified directly. 737 assert(((!TyEl->isSubClassOf("LLVMExtendedType") && 738 !TyEl->isSubClassOf("LLVMTruncatedType")) || 739 VT == MVT::iAny || VT == MVT::vAny) && 740 "Expected iAny or vAny type"); 741 } else { 742 VT = getValueType(TyEl->getValueAsDef("VT")); 743 } 744 745 // Reject invalid types. 746 if (VT == MVT::isVoid) 747 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 748 " has void in result type list!"); 749 750 IS.RetVTs.push_back(VT); 751 IS.RetTypeDefs.push_back(TyEl); 752 } 753 754 // Parse the list of parameter types. 755 TypeList = ParamTypes; 756 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 757 Record *TyEl = TypeList->getElementAsRecord(i); 758 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 759 MVT::SimpleValueType VT; 760 if (TyEl->isSubClassOf("LLVMMatchType")) { 761 unsigned MatchTy = TyEl->getValueAsInt("Number"); 762 if (MatchTy >= OverloadedVTs.size()) { 763 PrintError(R->getLoc(), 764 "Parameter #" + Twine(i) + " has out of bounds matching " 765 "number " + Twine(MatchTy)); 766 PrintFatalError(DefLoc, 767 Twine("ParamTypes is ") + TypeList->getAsString()); 768 } 769 VT = OverloadedVTs[MatchTy]; 770 // It only makes sense to use the extended and truncated vector element 771 // variants with iAny types; otherwise, if the intrinsic is not 772 // overloaded, all the types can be specified directly. 773 assert(((!TyEl->isSubClassOf("LLVMExtendedType") && 774 !TyEl->isSubClassOf("LLVMTruncatedType")) || 775 VT == MVT::iAny || VT == MVT::vAny) && 776 "Expected iAny or vAny type"); 777 } else 778 VT = getValueType(TyEl->getValueAsDef("VT")); 779 780 // Reject invalid types. 781 if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/) 782 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 783 " has void in result type list!"); 784 785 IS.ParamVTs.push_back(VT); 786 IS.ParamTypeDefs.push_back(TyEl); 787 } 788 789 // Parse the intrinsic properties. 790 ListInit *PropList = R->getValueAsListInit("IntrProperties"); 791 for (unsigned i = 0, e = PropList->size(); i != e; ++i) { 792 Record *Property = PropList->getElementAsRecord(i); 793 assert(Property->isSubClassOf("IntrinsicProperty") && 794 "Expected a property!"); 795 796 setProperty(Property); 797 } 798 799 // Set default properties to true. 800 setDefaultProperties(R, DefaultProperties); 801 802 // Also record the SDPatternOperator Properties. 803 Properties = parseSDPatternOperatorProperties(R); 804 805 // Sort the argument attributes for later benefit. 806 llvm::sort(ArgumentAttributes); 807 } 808 809 void CodeGenIntrinsic::setDefaultProperties( 810 Record *R, std::vector<Record *> DefaultProperties) { 811 // opt-out of using default attributes. 812 if (R->getValueAsBit("DisableDefaultAttributes")) 813 return; 814 815 for (Record *Rec : DefaultProperties) 816 setProperty(Rec); 817 } 818 819 void CodeGenIntrinsic::setProperty(Record *R) { 820 if (R->getName() == "IntrNoMem") 821 ModRef = NoMem; 822 else if (R->getName() == "IntrReadMem") 823 ModRef = ModRefBehavior(ModRef & ~MR_Mod); 824 else if (R->getName() == "IntrWriteMem") 825 ModRef = ModRefBehavior(ModRef & ~MR_Ref); 826 else if (R->getName() == "IntrArgMemOnly") 827 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem); 828 else if (R->getName() == "IntrInaccessibleMemOnly") 829 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_InaccessibleMem); 830 else if (R->getName() == "IntrInaccessibleMemOrArgMemOnly") 831 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem | 832 MR_InaccessibleMem); 833 else if (R->getName() == "Commutative") 834 isCommutative = true; 835 else if (R->getName() == "Throws") 836 canThrow = true; 837 else if (R->getName() == "IntrNoDuplicate") 838 isNoDuplicate = true; 839 else if (R->getName() == "IntrConvergent") 840 isConvergent = true; 841 else if (R->getName() == "IntrNoReturn") 842 isNoReturn = true; 843 else if (R->getName() == "IntrNoSync") 844 isNoSync = true; 845 else if (R->getName() == "IntrNoFree") 846 isNoFree = true; 847 else if (R->getName() == "IntrWillReturn") 848 isWillReturn = !isNoReturn; 849 else if (R->getName() == "IntrCold") 850 isCold = true; 851 else if (R->getName() == "IntrSpeculatable") 852 isSpeculatable = true; 853 else if (R->getName() == "IntrHasSideEffects") 854 hasSideEffects = true; 855 else if (R->isSubClassOf("NoCapture")) { 856 unsigned ArgNo = R->getValueAsInt("ArgNo"); 857 ArgumentAttributes.emplace_back(ArgNo, NoCapture, 0); 858 } else if (R->isSubClassOf("NoAlias")) { 859 unsigned ArgNo = R->getValueAsInt("ArgNo"); 860 ArgumentAttributes.emplace_back(ArgNo, NoAlias, 0); 861 } else if (R->isSubClassOf("NoUndef")) { 862 unsigned ArgNo = R->getValueAsInt("ArgNo"); 863 ArgumentAttributes.emplace_back(ArgNo, NoUndef, 0); 864 } else if (R->isSubClassOf("Returned")) { 865 unsigned ArgNo = R->getValueAsInt("ArgNo"); 866 ArgumentAttributes.emplace_back(ArgNo, Returned, 0); 867 } else if (R->isSubClassOf("ReadOnly")) { 868 unsigned ArgNo = R->getValueAsInt("ArgNo"); 869 ArgumentAttributes.emplace_back(ArgNo, ReadOnly, 0); 870 } else if (R->isSubClassOf("WriteOnly")) { 871 unsigned ArgNo = R->getValueAsInt("ArgNo"); 872 ArgumentAttributes.emplace_back(ArgNo, WriteOnly, 0); 873 } else if (R->isSubClassOf("ReadNone")) { 874 unsigned ArgNo = R->getValueAsInt("ArgNo"); 875 ArgumentAttributes.emplace_back(ArgNo, ReadNone, 0); 876 } else if (R->isSubClassOf("ImmArg")) { 877 unsigned ArgNo = R->getValueAsInt("ArgNo"); 878 ArgumentAttributes.emplace_back(ArgNo, ImmArg, 0); 879 } else if (R->isSubClassOf("Align")) { 880 unsigned ArgNo = R->getValueAsInt("ArgNo"); 881 uint64_t Align = R->getValueAsInt("Align"); 882 ArgumentAttributes.emplace_back(ArgNo, Alignment, Align); 883 } else 884 llvm_unreachable("Unknown property!"); 885 } 886 887 bool CodeGenIntrinsic::isParamAPointer(unsigned ParamIdx) const { 888 if (ParamIdx >= IS.ParamVTs.size()) 889 return false; 890 MVT ParamType = MVT(IS.ParamVTs[ParamIdx]); 891 return ParamType == MVT::iPTR || ParamType == MVT::iPTRAny; 892 } 893 894 bool CodeGenIntrinsic::isParamImmArg(unsigned ParamIdx) const { 895 // Convert argument index to attribute index starting from `FirstArgIndex`. 896 ArgAttribute Val{ParamIdx + 1, ImmArg, 0}; 897 return std::binary_search(ArgumentAttributes.begin(), 898 ArgumentAttributes.end(), Val); 899 } 900