1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This class wraps target description classes used by the various code 10 // generation TableGen backends. This makes it easier to access the data and 11 // provides a single place that needs to check it for validity. All of these 12 // classes abort on error conditions. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "CodeGenTarget.h" 17 #include "CodeGenDAGPatterns.h" 18 #include "CodeGenIntrinsics.h" 19 #include "CodeGenSchedule.h" 20 #include "llvm/ADT/STLExtras.h" 21 #include "llvm/ADT/StringExtras.h" 22 #include "llvm/Support/CommandLine.h" 23 #include "llvm/Support/Timer.h" 24 #include "llvm/TableGen/Error.h" 25 #include "llvm/TableGen/Record.h" 26 #include "llvm/TableGen/TableGenBackend.h" 27 #include <algorithm> 28 using namespace llvm; 29 30 cl::OptionCategory AsmParserCat("Options for -gen-asm-parser"); 31 cl::OptionCategory AsmWriterCat("Options for -gen-asm-writer"); 32 33 static cl::opt<unsigned> 34 AsmParserNum("asmparsernum", cl::init(0), 35 cl::desc("Make -gen-asm-parser emit assembly parser #N"), 36 cl::cat(AsmParserCat)); 37 38 static cl::opt<unsigned> 39 AsmWriterNum("asmwriternum", cl::init(0), 40 cl::desc("Make -gen-asm-writer emit assembly writer #N"), 41 cl::cat(AsmWriterCat)); 42 43 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen 44 /// record corresponds to. 45 MVT::SimpleValueType llvm::getValueType(Record *Rec) { 46 return (MVT::SimpleValueType)Rec->getValueAsInt("Value"); 47 } 48 49 StringRef llvm::getName(MVT::SimpleValueType T) { 50 switch (T) { 51 case MVT::Other: return "UNKNOWN"; 52 case MVT::iPTR: return "TLI.getPointerTy()"; 53 case MVT::iPTRAny: return "TLI.getPointerTy()"; 54 default: return getEnumName(T); 55 } 56 } 57 58 StringRef llvm::getEnumName(MVT::SimpleValueType T) { 59 switch (T) { 60 case MVT::Other: return "MVT::Other"; 61 case MVT::i1: return "MVT::i1"; 62 case MVT::i8: return "MVT::i8"; 63 case MVT::i16: return "MVT::i16"; 64 case MVT::i32: return "MVT::i32"; 65 case MVT::i64: return "MVT::i64"; 66 case MVT::i128: return "MVT::i128"; 67 case MVT::Any: return "MVT::Any"; 68 case MVT::iAny: return "MVT::iAny"; 69 case MVT::fAny: return "MVT::fAny"; 70 case MVT::vAny: return "MVT::vAny"; 71 case MVT::f16: return "MVT::f16"; 72 case MVT::bf16: return "MVT::bf16"; 73 case MVT::f32: return "MVT::f32"; 74 case MVT::f64: return "MVT::f64"; 75 case MVT::f80: return "MVT::f80"; 76 case MVT::f128: return "MVT::f128"; 77 case MVT::ppcf128: return "MVT::ppcf128"; 78 case MVT::x86mmx: return "MVT::x86mmx"; 79 case MVT::Glue: return "MVT::Glue"; 80 case MVT::isVoid: return "MVT::isVoid"; 81 case MVT::v1i1: return "MVT::v1i1"; 82 case MVT::v2i1: return "MVT::v2i1"; 83 case MVT::v4i1: return "MVT::v4i1"; 84 case MVT::v8i1: return "MVT::v8i1"; 85 case MVT::v16i1: return "MVT::v16i1"; 86 case MVT::v32i1: return "MVT::v32i1"; 87 case MVT::v64i1: return "MVT::v64i1"; 88 case MVT::v128i1: return "MVT::v128i1"; 89 case MVT::v512i1: return "MVT::v512i1"; 90 case MVT::v1024i1: return "MVT::v1024i1"; 91 case MVT::v1i8: return "MVT::v1i8"; 92 case MVT::v2i8: return "MVT::v2i8"; 93 case MVT::v4i8: return "MVT::v4i8"; 94 case MVT::v8i8: return "MVT::v8i8"; 95 case MVT::v16i8: return "MVT::v16i8"; 96 case MVT::v32i8: return "MVT::v32i8"; 97 case MVT::v64i8: return "MVT::v64i8"; 98 case MVT::v128i8: return "MVT::v128i8"; 99 case MVT::v256i8: return "MVT::v256i8"; 100 case MVT::v1i16: return "MVT::v1i16"; 101 case MVT::v2i16: return "MVT::v2i16"; 102 case MVT::v3i16: return "MVT::v3i16"; 103 case MVT::v4i16: return "MVT::v4i16"; 104 case MVT::v8i16: return "MVT::v8i16"; 105 case MVT::v16i16: return "MVT::v16i16"; 106 case MVT::v32i16: return "MVT::v32i16"; 107 case MVT::v64i16: return "MVT::v64i16"; 108 case MVT::v128i16: return "MVT::v128i16"; 109 case MVT::v1i32: return "MVT::v1i32"; 110 case MVT::v2i32: return "MVT::v2i32"; 111 case MVT::v3i32: return "MVT::v3i32"; 112 case MVT::v4i32: return "MVT::v4i32"; 113 case MVT::v5i32: return "MVT::v5i32"; 114 case MVT::v8i32: return "MVT::v8i32"; 115 case MVT::v16i32: return "MVT::v16i32"; 116 case MVT::v32i32: return "MVT::v32i32"; 117 case MVT::v64i32: return "MVT::v64i32"; 118 case MVT::v128i32: return "MVT::v128i32"; 119 case MVT::v256i32: return "MVT::v256i32"; 120 case MVT::v512i32: return "MVT::v512i32"; 121 case MVT::v1024i32: return "MVT::v1024i32"; 122 case MVT::v2048i32: return "MVT::v2048i32"; 123 case MVT::v1i64: return "MVT::v1i64"; 124 case MVT::v2i64: return "MVT::v2i64"; 125 case MVT::v4i64: return "MVT::v4i64"; 126 case MVT::v8i64: return "MVT::v8i64"; 127 case MVT::v16i64: return "MVT::v16i64"; 128 case MVT::v32i64: return "MVT::v32i64"; 129 case MVT::v1i128: return "MVT::v1i128"; 130 case MVT::v2f16: return "MVT::v2f16"; 131 case MVT::v3f16: return "MVT::v3f16"; 132 case MVT::v4f16: return "MVT::v4f16"; 133 case MVT::v8f16: return "MVT::v8f16"; 134 case MVT::v16f16: return "MVT::v16f16"; 135 case MVT::v32f16: return "MVT::v32f16"; 136 case MVT::v2bf16: return "MVT::v2bf16"; 137 case MVT::v3bf16: return "MVT::v3bf16"; 138 case MVT::v4bf16: return "MVT::v4bf16"; 139 case MVT::v8bf16: return "MVT::v8bf16"; 140 case MVT::v16bf16: return "MVT::v16bf16"; 141 case MVT::v32bf16: return "MVT::v32bf16"; 142 case MVT::v1f32: return "MVT::v1f32"; 143 case MVT::v2f32: return "MVT::v2f32"; 144 case MVT::v3f32: return "MVT::v3f32"; 145 case MVT::v4f32: return "MVT::v4f32"; 146 case MVT::v5f32: return "MVT::v5f32"; 147 case MVT::v8f32: return "MVT::v8f32"; 148 case MVT::v16f32: return "MVT::v16f32"; 149 case MVT::v32f32: return "MVT::v32f32"; 150 case MVT::v64f32: return "MVT::v64f32"; 151 case MVT::v128f32: return "MVT::v128f32"; 152 case MVT::v256f32: return "MVT::v256f32"; 153 case MVT::v512f32: return "MVT::v512f32"; 154 case MVT::v1024f32: return "MVT::v1024f32"; 155 case MVT::v2048f32: return "MVT::v2048f32"; 156 case MVT::v1f64: return "MVT::v1f64"; 157 case MVT::v2f64: return "MVT::v2f64"; 158 case MVT::v4f64: return "MVT::v4f64"; 159 case MVT::v8f64: return "MVT::v8f64"; 160 case MVT::v16f64: return "MVT::v16f64"; 161 case MVT::nxv1i1: return "MVT::nxv1i1"; 162 case MVT::nxv2i1: return "MVT::nxv2i1"; 163 case MVT::nxv4i1: return "MVT::nxv4i1"; 164 case MVT::nxv8i1: return "MVT::nxv8i1"; 165 case MVT::nxv16i1: return "MVT::nxv16i1"; 166 case MVT::nxv32i1: return "MVT::nxv32i1"; 167 case MVT::nxv1i8: return "MVT::nxv1i8"; 168 case MVT::nxv2i8: return "MVT::nxv2i8"; 169 case MVT::nxv4i8: return "MVT::nxv4i8"; 170 case MVT::nxv8i8: return "MVT::nxv8i8"; 171 case MVT::nxv16i8: return "MVT::nxv16i8"; 172 case MVT::nxv32i8: return "MVT::nxv32i8"; 173 case MVT::nxv1i16: return "MVT::nxv1i16"; 174 case MVT::nxv2i16: return "MVT::nxv2i16"; 175 case MVT::nxv4i16: return "MVT::nxv4i16"; 176 case MVT::nxv8i16: return "MVT::nxv8i16"; 177 case MVT::nxv16i16: return "MVT::nxv16i16"; 178 case MVT::nxv32i16: return "MVT::nxv32i16"; 179 case MVT::nxv1i32: return "MVT::nxv1i32"; 180 case MVT::nxv2i32: return "MVT::nxv2i32"; 181 case MVT::nxv4i32: return "MVT::nxv4i32"; 182 case MVT::nxv8i32: return "MVT::nxv8i32"; 183 case MVT::nxv16i32: return "MVT::nxv16i32"; 184 case MVT::nxv1i64: return "MVT::nxv1i64"; 185 case MVT::nxv2i64: return "MVT::nxv2i64"; 186 case MVT::nxv4i64: return "MVT::nxv4i64"; 187 case MVT::nxv8i64: return "MVT::nxv8i64"; 188 case MVT::nxv16i64: return "MVT::nxv16i64"; 189 case MVT::nxv2f16: return "MVT::nxv2f16"; 190 case MVT::nxv4f16: return "MVT::nxv4f16"; 191 case MVT::nxv8f16: return "MVT::nxv8f16"; 192 case MVT::nxv2bf16: return "MVT::nxv2bf16"; 193 case MVT::nxv4bf16: return "MVT::nxv4bf16"; 194 case MVT::nxv8bf16: return "MVT::nxv8bf16"; 195 case MVT::nxv1f32: return "MVT::nxv1f32"; 196 case MVT::nxv2f32: return "MVT::nxv2f32"; 197 case MVT::nxv4f32: return "MVT::nxv4f32"; 198 case MVT::nxv8f32: return "MVT::nxv8f32"; 199 case MVT::nxv16f32: return "MVT::nxv16f32"; 200 case MVT::nxv1f64: return "MVT::nxv1f64"; 201 case MVT::nxv2f64: return "MVT::nxv2f64"; 202 case MVT::nxv4f64: return "MVT::nxv4f64"; 203 case MVT::nxv8f64: return "MVT::nxv8f64"; 204 case MVT::token: return "MVT::token"; 205 case MVT::Metadata: return "MVT::Metadata"; 206 case MVT::iPTR: return "MVT::iPTR"; 207 case MVT::iPTRAny: return "MVT::iPTRAny"; 208 case MVT::Untyped: return "MVT::Untyped"; 209 case MVT::exnref: return "MVT::exnref"; 210 default: llvm_unreachable("ILLEGAL VALUE TYPE!"); 211 } 212 } 213 214 /// getQualifiedName - Return the name of the specified record, with a 215 /// namespace qualifier if the record contains one. 216 /// 217 std::string llvm::getQualifiedName(const Record *R) { 218 std::string Namespace; 219 if (R->getValue("Namespace")) 220 Namespace = std::string(R->getValueAsString("Namespace")); 221 if (Namespace.empty()) 222 return std::string(R->getName()); 223 return Namespace + "::" + R->getName().str(); 224 } 225 226 227 /// getTarget - Return the current instance of the Target class. 228 /// 229 CodeGenTarget::CodeGenTarget(RecordKeeper &records) 230 : Records(records), CGH(records) { 231 std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target"); 232 if (Targets.size() == 0) 233 PrintFatalError("ERROR: No 'Target' subclasses defined!"); 234 if (Targets.size() != 1) 235 PrintFatalError("ERROR: Multiple subclasses of Target defined!"); 236 TargetRec = Targets[0]; 237 } 238 239 CodeGenTarget::~CodeGenTarget() { 240 } 241 242 const StringRef CodeGenTarget::getName() const { 243 return TargetRec->getName(); 244 } 245 246 StringRef CodeGenTarget::getInstNamespace() const { 247 for (const CodeGenInstruction *Inst : getInstructionsByEnumValue()) { 248 // Make sure not to pick up "TargetOpcode" by accidentally getting 249 // the namespace off the PHI instruction or something. 250 if (Inst->Namespace != "TargetOpcode") 251 return Inst->Namespace; 252 } 253 254 return ""; 255 } 256 257 Record *CodeGenTarget::getInstructionSet() const { 258 return TargetRec->getValueAsDef("InstructionSet"); 259 } 260 261 bool CodeGenTarget::getAllowRegisterRenaming() const { 262 return TargetRec->getValueAsInt("AllowRegisterRenaming"); 263 } 264 265 /// getAsmParser - Return the AssemblyParser definition for this target. 266 /// 267 Record *CodeGenTarget::getAsmParser() const { 268 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers"); 269 if (AsmParserNum >= LI.size()) 270 PrintFatalError("Target does not have an AsmParser #" + 271 Twine(AsmParserNum) + "!"); 272 return LI[AsmParserNum]; 273 } 274 275 /// getAsmParserVariant - Return the AssemblyParserVariant definition for 276 /// this target. 277 /// 278 Record *CodeGenTarget::getAsmParserVariant(unsigned i) const { 279 std::vector<Record*> LI = 280 TargetRec->getValueAsListOfDefs("AssemblyParserVariants"); 281 if (i >= LI.size()) 282 PrintFatalError("Target does not have an AsmParserVariant #" + Twine(i) + 283 "!"); 284 return LI[i]; 285 } 286 287 /// getAsmParserVariantCount - Return the AssemblyParserVariant definition 288 /// available for this target. 289 /// 290 unsigned CodeGenTarget::getAsmParserVariantCount() const { 291 std::vector<Record*> LI = 292 TargetRec->getValueAsListOfDefs("AssemblyParserVariants"); 293 return LI.size(); 294 } 295 296 /// getAsmWriter - Return the AssemblyWriter definition for this target. 297 /// 298 Record *CodeGenTarget::getAsmWriter() const { 299 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters"); 300 if (AsmWriterNum >= LI.size()) 301 PrintFatalError("Target does not have an AsmWriter #" + 302 Twine(AsmWriterNum) + "!"); 303 return LI[AsmWriterNum]; 304 } 305 306 CodeGenRegBank &CodeGenTarget::getRegBank() const { 307 if (!RegBank) 308 RegBank = std::make_unique<CodeGenRegBank>(Records, getHwModes()); 309 return *RegBank; 310 } 311 312 Optional<CodeGenRegisterClass *> 313 CodeGenTarget::getSuperRegForSubReg(const ValueTypeByHwMode &ValueTy, 314 CodeGenRegBank &RegBank, 315 const CodeGenSubRegIndex *SubIdx) const { 316 std::vector<CodeGenRegisterClass *> Candidates; 317 auto &RegClasses = RegBank.getRegClasses(); 318 319 // Try to find a register class which supports ValueTy, and also contains 320 // SubIdx. 321 for (CodeGenRegisterClass &RC : RegClasses) { 322 // Is there a subclass of this class which contains this subregister index? 323 CodeGenRegisterClass *SubClassWithSubReg = RC.getSubClassWithSubReg(SubIdx); 324 if (!SubClassWithSubReg) 325 continue; 326 327 // We have a class. Check if it supports this value type. 328 if (llvm::none_of(SubClassWithSubReg->VTs, 329 [&ValueTy](const ValueTypeByHwMode &ClassVT) { 330 return ClassVT == ValueTy; 331 })) 332 continue; 333 334 // We have a register class which supports both the value type and 335 // subregister index. Remember it. 336 Candidates.push_back(SubClassWithSubReg); 337 } 338 339 // If we didn't find anything, we're done. 340 if (Candidates.empty()) 341 return None; 342 343 // Find and return the largest of our candidate classes. 344 llvm::stable_sort(Candidates, [&](const CodeGenRegisterClass *A, 345 const CodeGenRegisterClass *B) { 346 if (A->getMembers().size() > B->getMembers().size()) 347 return true; 348 349 if (A->getMembers().size() < B->getMembers().size()) 350 return false; 351 352 // Order by name as a tie-breaker. 353 return StringRef(A->getName()) < B->getName(); 354 }); 355 356 return Candidates[0]; 357 } 358 359 void CodeGenTarget::ReadRegAltNameIndices() const { 360 RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex"); 361 llvm::sort(RegAltNameIndices, LessRecord()); 362 } 363 364 /// getRegisterByName - If there is a register with the specific AsmName, 365 /// return it. 366 const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const { 367 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName(); 368 StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name); 369 if (I == Regs.end()) 370 return nullptr; 371 return I->second; 372 } 373 374 std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R) 375 const { 376 const CodeGenRegister *Reg = getRegBank().getReg(R); 377 std::vector<ValueTypeByHwMode> Result; 378 for (const auto &RC : getRegBank().getRegClasses()) { 379 if (RC.contains(Reg)) { 380 ArrayRef<ValueTypeByHwMode> InVTs = RC.getValueTypes(); 381 Result.insert(Result.end(), InVTs.begin(), InVTs.end()); 382 } 383 } 384 385 // Remove duplicates. 386 llvm::sort(Result); 387 Result.erase(std::unique(Result.begin(), Result.end()), Result.end()); 388 return Result; 389 } 390 391 392 void CodeGenTarget::ReadLegalValueTypes() const { 393 for (const auto &RC : getRegBank().getRegClasses()) 394 LegalValueTypes.insert(LegalValueTypes.end(), RC.VTs.begin(), RC.VTs.end()); 395 396 // Remove duplicates. 397 llvm::sort(LegalValueTypes); 398 LegalValueTypes.erase(std::unique(LegalValueTypes.begin(), 399 LegalValueTypes.end()), 400 LegalValueTypes.end()); 401 } 402 403 CodeGenSchedModels &CodeGenTarget::getSchedModels() const { 404 if (!SchedModels) 405 SchedModels = std::make_unique<CodeGenSchedModels>(Records, *this); 406 return *SchedModels; 407 } 408 409 void CodeGenTarget::ReadInstructions() const { 410 NamedRegionTimer T("Read Instructions", "Time spent reading instructions", 411 "CodeGenTarget", "CodeGenTarget", TimeRegions); 412 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction"); 413 if (Insts.size() <= 2) 414 PrintFatalError("No 'Instruction' subclasses defined!"); 415 416 // Parse the instructions defined in the .td file. 417 for (unsigned i = 0, e = Insts.size(); i != e; ++i) 418 Instructions[Insts[i]] = std::make_unique<CodeGenInstruction>(Insts[i]); 419 } 420 421 static const CodeGenInstruction * 422 GetInstByName(const char *Name, 423 const DenseMap<const Record*, 424 std::unique_ptr<CodeGenInstruction>> &Insts, 425 RecordKeeper &Records) { 426 const Record *Rec = Records.getDef(Name); 427 428 const auto I = Insts.find(Rec); 429 if (!Rec || I == Insts.end()) 430 PrintFatalError(Twine("Could not find '") + Name + "' instruction!"); 431 return I->second.get(); 432 } 433 434 static const char *const FixedInstrs[] = { 435 #define HANDLE_TARGET_OPCODE(OPC) #OPC, 436 #include "llvm/Support/TargetOpcodes.def" 437 nullptr}; 438 439 unsigned CodeGenTarget::getNumFixedInstructions() { 440 return array_lengthof(FixedInstrs) - 1; 441 } 442 443 /// Return all of the instructions defined by the target, ordered by 444 /// their enum value. 445 void CodeGenTarget::ComputeInstrsByEnum() const { 446 const auto &Insts = getInstructions(); 447 for (const char *const *p = FixedInstrs; *p; ++p) { 448 const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records); 449 assert(Instr && "Missing target independent instruction"); 450 assert(Instr->Namespace == "TargetOpcode" && "Bad namespace"); 451 InstrsByEnum.push_back(Instr); 452 } 453 unsigned EndOfPredefines = InstrsByEnum.size(); 454 assert(EndOfPredefines == getNumFixedInstructions() && 455 "Missing generic opcode"); 456 457 for (const auto &I : Insts) { 458 const CodeGenInstruction *CGI = I.second.get(); 459 if (CGI->Namespace != "TargetOpcode") { 460 InstrsByEnum.push_back(CGI); 461 if (CGI->TheDef->getValueAsBit("isPseudo")) 462 ++NumPseudoInstructions; 463 } 464 } 465 466 assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr"); 467 468 // All of the instructions are now in random order based on the map iteration. 469 llvm::sort( 470 InstrsByEnum.begin() + EndOfPredefines, InstrsByEnum.end(), 471 [](const CodeGenInstruction *Rec1, const CodeGenInstruction *Rec2) { 472 const auto &D1 = *Rec1->TheDef; 473 const auto &D2 = *Rec2->TheDef; 474 return std::make_tuple(!D1.getValueAsBit("isPseudo"), D1.getName()) < 475 std::make_tuple(!D2.getValueAsBit("isPseudo"), D2.getName()); 476 }); 477 } 478 479 480 /// isLittleEndianEncoding - Return whether this target encodes its instruction 481 /// in little-endian format, i.e. bits laid out in the order [0..n] 482 /// 483 bool CodeGenTarget::isLittleEndianEncoding() const { 484 return getInstructionSet()->getValueAsBit("isLittleEndianEncoding"); 485 } 486 487 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit 488 /// encodings, reverse the bit order of all instructions. 489 void CodeGenTarget::reverseBitsForLittleEndianEncoding() { 490 if (!isLittleEndianEncoding()) 491 return; 492 493 std::vector<Record *> Insts = 494 Records.getAllDerivedDefinitions("InstructionEncoding"); 495 for (Record *R : Insts) { 496 if (R->getValueAsString("Namespace") == "TargetOpcode" || 497 R->getValueAsBit("isPseudo")) 498 continue; 499 500 BitsInit *BI = R->getValueAsBitsInit("Inst"); 501 502 unsigned numBits = BI->getNumBits(); 503 504 SmallVector<Init *, 16> NewBits(numBits); 505 506 for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) { 507 unsigned bitSwapIdx = numBits - bit - 1; 508 Init *OrigBit = BI->getBit(bit); 509 Init *BitSwap = BI->getBit(bitSwapIdx); 510 NewBits[bit] = BitSwap; 511 NewBits[bitSwapIdx] = OrigBit; 512 } 513 if (numBits % 2) { 514 unsigned middle = (numBits + 1) / 2; 515 NewBits[middle] = BI->getBit(middle); 516 } 517 518 BitsInit *NewBI = BitsInit::get(NewBits); 519 520 // Update the bits in reversed order so that emitInstrOpBits will get the 521 // correct endianness. 522 R->getValue("Inst")->setValue(NewBI); 523 } 524 } 525 526 /// guessInstructionProperties - Return true if it's OK to guess instruction 527 /// properties instead of raising an error. 528 /// 529 /// This is configurable as a temporary migration aid. It will eventually be 530 /// permanently false. 531 bool CodeGenTarget::guessInstructionProperties() const { 532 return getInstructionSet()->getValueAsBit("guessInstructionProperties"); 533 } 534 535 //===----------------------------------------------------------------------===// 536 // ComplexPattern implementation 537 // 538 ComplexPattern::ComplexPattern(Record *R) { 539 Ty = ::getValueType(R->getValueAsDef("Ty")); 540 NumOperands = R->getValueAsInt("NumOperands"); 541 SelectFunc = std::string(R->getValueAsString("SelectFunc")); 542 RootNodes = R->getValueAsListOfDefs("RootNodes"); 543 544 // FIXME: This is a hack to statically increase the priority of patterns which 545 // maps a sub-dag to a complex pattern. e.g. favors LEA over ADD. To get best 546 // possible pattern match we'll need to dynamically calculate the complexity 547 // of all patterns a dag can potentially map to. 548 int64_t RawComplexity = R->getValueAsInt("Complexity"); 549 if (RawComplexity == -1) 550 Complexity = NumOperands * 3; 551 else 552 Complexity = RawComplexity; 553 554 // FIXME: Why is this different from parseSDPatternOperatorProperties? 555 // Parse the properties. 556 Properties = 0; 557 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties"); 558 for (unsigned i = 0, e = PropList.size(); i != e; ++i) 559 if (PropList[i]->getName() == "SDNPHasChain") { 560 Properties |= 1 << SDNPHasChain; 561 } else if (PropList[i]->getName() == "SDNPOptInGlue") { 562 Properties |= 1 << SDNPOptInGlue; 563 } else if (PropList[i]->getName() == "SDNPMayStore") { 564 Properties |= 1 << SDNPMayStore; 565 } else if (PropList[i]->getName() == "SDNPMayLoad") { 566 Properties |= 1 << SDNPMayLoad; 567 } else if (PropList[i]->getName() == "SDNPSideEffect") { 568 Properties |= 1 << SDNPSideEffect; 569 } else if (PropList[i]->getName() == "SDNPMemOperand") { 570 Properties |= 1 << SDNPMemOperand; 571 } else if (PropList[i]->getName() == "SDNPVariadic") { 572 Properties |= 1 << SDNPVariadic; 573 } else if (PropList[i]->getName() == "SDNPWantRoot") { 574 Properties |= 1 << SDNPWantRoot; 575 } else if (PropList[i]->getName() == "SDNPWantParent") { 576 Properties |= 1 << SDNPWantParent; 577 } else { 578 PrintFatalError(R->getLoc(), "Unsupported SD Node property '" + 579 PropList[i]->getName() + 580 "' on ComplexPattern '" + R->getName() + 581 "'!"); 582 } 583 } 584 585 //===----------------------------------------------------------------------===// 586 // CodeGenIntrinsic Implementation 587 //===----------------------------------------------------------------------===// 588 589 CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC) { 590 std::vector<Record*> Defs = RC.getAllDerivedDefinitions("Intrinsic"); 591 592 Intrinsics.reserve(Defs.size()); 593 594 for (unsigned I = 0, e = Defs.size(); I != e; ++I) 595 Intrinsics.push_back(CodeGenIntrinsic(Defs[I])); 596 597 llvm::sort(Intrinsics, 598 [](const CodeGenIntrinsic &LHS, const CodeGenIntrinsic &RHS) { 599 return std::tie(LHS.TargetPrefix, LHS.Name) < 600 std::tie(RHS.TargetPrefix, RHS.Name); 601 }); 602 Targets.push_back({"", 0, 0}); 603 for (size_t I = 0, E = Intrinsics.size(); I < E; ++I) 604 if (Intrinsics[I].TargetPrefix != Targets.back().Name) { 605 Targets.back().Count = I - Targets.back().Offset; 606 Targets.push_back({Intrinsics[I].TargetPrefix, I, 0}); 607 } 608 Targets.back().Count = Intrinsics.size() - Targets.back().Offset; 609 } 610 611 CodeGenIntrinsic::CodeGenIntrinsic(Record *R) { 612 TheDef = R; 613 std::string DefName = std::string(R->getName()); 614 ArrayRef<SMLoc> DefLoc = R->getLoc(); 615 ModRef = ReadWriteMem; 616 Properties = 0; 617 isOverloaded = false; 618 isCommutative = false; 619 canThrow = false; 620 isNoReturn = false; 621 isNoSync = false; 622 isWillReturn = false; 623 isCold = false; 624 isNoDuplicate = false; 625 isConvergent = false; 626 isSpeculatable = false; 627 hasSideEffects = false; 628 629 if (DefName.size() <= 4 || 630 std::string(DefName.begin(), DefName.begin() + 4) != "int_") 631 PrintFatalError(DefLoc, 632 "Intrinsic '" + DefName + "' does not start with 'int_'!"); 633 634 EnumName = std::string(DefName.begin()+4, DefName.end()); 635 636 if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field. 637 GCCBuiltinName = std::string(R->getValueAsString("GCCBuiltinName")); 638 if (R->getValue("MSBuiltinName")) // Ignore a missing MSBuiltinName field. 639 MSBuiltinName = std::string(R->getValueAsString("MSBuiltinName")); 640 641 TargetPrefix = std::string(R->getValueAsString("TargetPrefix")); 642 Name = std::string(R->getValueAsString("LLVMName")); 643 644 if (Name == "") { 645 // If an explicit name isn't specified, derive one from the DefName. 646 Name = "llvm."; 647 648 for (unsigned i = 0, e = EnumName.size(); i != e; ++i) 649 Name += (EnumName[i] == '_') ? '.' : EnumName[i]; 650 } else { 651 // Verify it starts with "llvm.". 652 if (Name.size() <= 5 || 653 std::string(Name.begin(), Name.begin() + 5) != "llvm.") 654 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 655 "'s name does not start with 'llvm.'!"); 656 } 657 658 // If TargetPrefix is specified, make sure that Name starts with 659 // "llvm.<targetprefix>.". 660 if (!TargetPrefix.empty()) { 661 if (Name.size() < 6+TargetPrefix.size() || 662 std::string(Name.begin() + 5, Name.begin() + 6 + TargetPrefix.size()) 663 != (TargetPrefix + ".")) 664 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 665 "' does not start with 'llvm." + 666 TargetPrefix + ".'!"); 667 } 668 669 ListInit *RetTypes = R->getValueAsListInit("RetTypes"); 670 ListInit *ParamTypes = R->getValueAsListInit("ParamTypes"); 671 672 // First collate a list of overloaded types. 673 std::vector<MVT::SimpleValueType> OverloadedVTs; 674 for (ListInit *TypeList : {RetTypes, ParamTypes}) { 675 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 676 Record *TyEl = TypeList->getElementAsRecord(i); 677 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 678 679 if (TyEl->isSubClassOf("LLVMMatchType")) 680 continue; 681 682 MVT::SimpleValueType VT = getValueType(TyEl->getValueAsDef("VT")); 683 if (MVT(VT).isOverloaded()) { 684 OverloadedVTs.push_back(VT); 685 isOverloaded = true; 686 } 687 } 688 } 689 690 // Parse the list of return types. 691 ListInit *TypeList = RetTypes; 692 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 693 Record *TyEl = TypeList->getElementAsRecord(i); 694 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 695 MVT::SimpleValueType VT; 696 if (TyEl->isSubClassOf("LLVMMatchType")) { 697 unsigned MatchTy = TyEl->getValueAsInt("Number"); 698 assert(MatchTy < OverloadedVTs.size() && 699 "Invalid matching number!"); 700 VT = OverloadedVTs[MatchTy]; 701 // It only makes sense to use the extended and truncated vector element 702 // variants with iAny types; otherwise, if the intrinsic is not 703 // overloaded, all the types can be specified directly. 704 assert(((!TyEl->isSubClassOf("LLVMExtendedType") && 705 !TyEl->isSubClassOf("LLVMTruncatedType")) || 706 VT == MVT::iAny || VT == MVT::vAny) && 707 "Expected iAny or vAny type"); 708 } else { 709 VT = getValueType(TyEl->getValueAsDef("VT")); 710 } 711 712 // Reject invalid types. 713 if (VT == MVT::isVoid) 714 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 715 " has void in result type list!"); 716 717 IS.RetVTs.push_back(VT); 718 IS.RetTypeDefs.push_back(TyEl); 719 } 720 721 // Parse the list of parameter types. 722 TypeList = ParamTypes; 723 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 724 Record *TyEl = TypeList->getElementAsRecord(i); 725 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 726 MVT::SimpleValueType VT; 727 if (TyEl->isSubClassOf("LLVMMatchType")) { 728 unsigned MatchTy = TyEl->getValueAsInt("Number"); 729 if (MatchTy >= OverloadedVTs.size()) { 730 PrintError(R->getLoc(), 731 "Parameter #" + Twine(i) + " has out of bounds matching " 732 "number " + Twine(MatchTy)); 733 PrintFatalError(DefLoc, 734 Twine("ParamTypes is ") + TypeList->getAsString()); 735 } 736 VT = OverloadedVTs[MatchTy]; 737 // It only makes sense to use the extended and truncated vector element 738 // variants with iAny types; otherwise, if the intrinsic is not 739 // overloaded, all the types can be specified directly. 740 assert(((!TyEl->isSubClassOf("LLVMExtendedType") && 741 !TyEl->isSubClassOf("LLVMTruncatedType")) || 742 VT == MVT::iAny || VT == MVT::vAny) && 743 "Expected iAny or vAny type"); 744 } else 745 VT = getValueType(TyEl->getValueAsDef("VT")); 746 747 // Reject invalid types. 748 if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/) 749 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 750 " has void in result type list!"); 751 752 IS.ParamVTs.push_back(VT); 753 IS.ParamTypeDefs.push_back(TyEl); 754 } 755 756 // Parse the intrinsic properties. 757 ListInit *PropList = R->getValueAsListInit("IntrProperties"); 758 for (unsigned i = 0, e = PropList->size(); i != e; ++i) { 759 Record *Property = PropList->getElementAsRecord(i); 760 assert(Property->isSubClassOf("IntrinsicProperty") && 761 "Expected a property!"); 762 763 if (Property->getName() == "IntrNoMem") 764 ModRef = NoMem; 765 else if (Property->getName() == "IntrReadMem") 766 ModRef = ModRefBehavior(ModRef & ~MR_Mod); 767 else if (Property->getName() == "IntrWriteMem") 768 ModRef = ModRefBehavior(ModRef & ~MR_Ref); 769 else if (Property->getName() == "IntrArgMemOnly") 770 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem); 771 else if (Property->getName() == "IntrInaccessibleMemOnly") 772 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_InaccessibleMem); 773 else if (Property->getName() == "IntrInaccessibleMemOrArgMemOnly") 774 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem | 775 MR_InaccessibleMem); 776 else if (Property->getName() == "Commutative") 777 isCommutative = true; 778 else if (Property->getName() == "Throws") 779 canThrow = true; 780 else if (Property->getName() == "IntrNoDuplicate") 781 isNoDuplicate = true; 782 else if (Property->getName() == "IntrConvergent") 783 isConvergent = true; 784 else if (Property->getName() == "IntrNoReturn") 785 isNoReturn = true; 786 else if (Property->getName() == "IntrNoSync") 787 isNoSync = true; 788 else if (Property->getName() == "IntrWillReturn") 789 isWillReturn = true; 790 else if (Property->getName() == "IntrCold") 791 isCold = true; 792 else if (Property->getName() == "IntrSpeculatable") 793 isSpeculatable = true; 794 else if (Property->getName() == "IntrHasSideEffects") 795 hasSideEffects = true; 796 else if (Property->isSubClassOf("NoCapture")) { 797 unsigned ArgNo = Property->getValueAsInt("ArgNo"); 798 ArgumentAttributes.emplace_back(ArgNo, NoCapture, 0); 799 } else if (Property->isSubClassOf("NoAlias")) { 800 unsigned ArgNo = Property->getValueAsInt("ArgNo"); 801 ArgumentAttributes.emplace_back(ArgNo, NoAlias, 0); 802 } else if (Property->isSubClassOf("Returned")) { 803 unsigned ArgNo = Property->getValueAsInt("ArgNo"); 804 ArgumentAttributes.emplace_back(ArgNo, Returned, 0); 805 } else if (Property->isSubClassOf("ReadOnly")) { 806 unsigned ArgNo = Property->getValueAsInt("ArgNo"); 807 ArgumentAttributes.emplace_back(ArgNo, ReadOnly, 0); 808 } else if (Property->isSubClassOf("WriteOnly")) { 809 unsigned ArgNo = Property->getValueAsInt("ArgNo"); 810 ArgumentAttributes.emplace_back(ArgNo, WriteOnly, 0); 811 } else if (Property->isSubClassOf("ReadNone")) { 812 unsigned ArgNo = Property->getValueAsInt("ArgNo"); 813 ArgumentAttributes.emplace_back(ArgNo, ReadNone, 0); 814 } else if (Property->isSubClassOf("ImmArg")) { 815 unsigned ArgNo = Property->getValueAsInt("ArgNo"); 816 ArgumentAttributes.emplace_back(ArgNo, ImmArg, 0); 817 } else if (Property->isSubClassOf("Align")) { 818 unsigned ArgNo = Property->getValueAsInt("ArgNo"); 819 uint64_t Align = Property->getValueAsInt("Align"); 820 ArgumentAttributes.emplace_back(ArgNo, Alignment, Align); 821 } else 822 llvm_unreachable("Unknown property!"); 823 } 824 825 // Also record the SDPatternOperator Properties. 826 Properties = parseSDPatternOperatorProperties(R); 827 828 // Sort the argument attributes for later benefit. 829 llvm::sort(ArgumentAttributes); 830 } 831 832 bool CodeGenIntrinsic::isParamAPointer(unsigned ParamIdx) const { 833 if (ParamIdx >= IS.ParamVTs.size()) 834 return false; 835 MVT ParamType = MVT(IS.ParamVTs[ParamIdx]); 836 return ParamType == MVT::iPTR || ParamType == MVT::iPTRAny; 837 } 838 839 bool CodeGenIntrinsic::isParamImmArg(unsigned ParamIdx) const { 840 // Convert argument index to attribute index starting from `FirstArgIndex`. 841 ArgAttribute Val{ParamIdx + 1, ImmArg, 0}; 842 return std::binary_search(ArgumentAttributes.begin(), 843 ArgumentAttributes.end(), Val); 844 } 845