1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This class wraps target description classes used by the various code 10 // generation TableGen backends. This makes it easier to access the data and 11 // provides a single place that needs to check it for validity. All of these 12 // classes abort on error conditions. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "CodeGenTarget.h" 17 #include "CodeGenDAGPatterns.h" 18 #include "CodeGenIntrinsics.h" 19 #include "CodeGenSchedule.h" 20 #include "llvm/ADT/STLExtras.h" 21 #include "llvm/ADT/StringExtras.h" 22 #include "llvm/Support/CommandLine.h" 23 #include "llvm/Support/Timer.h" 24 #include "llvm/TableGen/Error.h" 25 #include "llvm/TableGen/Record.h" 26 #include "llvm/TableGen/TableGenBackend.h" 27 #include <algorithm> 28 using namespace llvm; 29 30 cl::OptionCategory AsmParserCat("Options for -gen-asm-parser"); 31 cl::OptionCategory AsmWriterCat("Options for -gen-asm-writer"); 32 33 static cl::opt<unsigned> 34 AsmParserNum("asmparsernum", cl::init(0), 35 cl::desc("Make -gen-asm-parser emit assembly parser #N"), 36 cl::cat(AsmParserCat)); 37 38 static cl::opt<unsigned> 39 AsmWriterNum("asmwriternum", cl::init(0), 40 cl::desc("Make -gen-asm-writer emit assembly writer #N"), 41 cl::cat(AsmWriterCat)); 42 43 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen 44 /// record corresponds to. 45 MVT::SimpleValueType llvm::getValueType(Record *Rec) { 46 return (MVT::SimpleValueType)Rec->getValueAsInt("Value"); 47 } 48 49 StringRef llvm::getName(MVT::SimpleValueType T) { 50 switch (T) { 51 case MVT::Other: return "UNKNOWN"; 52 case MVT::iPTR: return "TLI.getPointerTy()"; 53 case MVT::iPTRAny: return "TLI.getPointerTy()"; 54 default: return getEnumName(T); 55 } 56 } 57 58 StringRef llvm::getEnumName(MVT::SimpleValueType T) { 59 switch (T) { 60 case MVT::Other: return "MVT::Other"; 61 case MVT::i1: return "MVT::i1"; 62 case MVT::i8: return "MVT::i8"; 63 case MVT::i16: return "MVT::i16"; 64 case MVT::i32: return "MVT::i32"; 65 case MVT::i64: return "MVT::i64"; 66 case MVT::i128: return "MVT::i128"; 67 case MVT::Any: return "MVT::Any"; 68 case MVT::iAny: return "MVT::iAny"; 69 case MVT::fAny: return "MVT::fAny"; 70 case MVT::vAny: return "MVT::vAny"; 71 case MVT::f16: return "MVT::f16"; 72 case MVT::bf16: return "MVT::bf16"; 73 case MVT::f32: return "MVT::f32"; 74 case MVT::f64: return "MVT::f64"; 75 case MVT::f80: return "MVT::f80"; 76 case MVT::f128: return "MVT::f128"; 77 case MVT::ppcf128: return "MVT::ppcf128"; 78 case MVT::x86mmx: return "MVT::x86mmx"; 79 case MVT::x86amx: return "MVT::x86amx"; 80 case MVT::Glue: return "MVT::Glue"; 81 case MVT::isVoid: return "MVT::isVoid"; 82 case MVT::v1i1: return "MVT::v1i1"; 83 case MVT::v2i1: return "MVT::v2i1"; 84 case MVT::v4i1: return "MVT::v4i1"; 85 case MVT::v8i1: return "MVT::v8i1"; 86 case MVT::v16i1: return "MVT::v16i1"; 87 case MVT::v32i1: return "MVT::v32i1"; 88 case MVT::v64i1: return "MVT::v64i1"; 89 case MVT::v128i1: return "MVT::v128i1"; 90 case MVT::v256i1: return "MVT::v256i1"; 91 case MVT::v512i1: return "MVT::v512i1"; 92 case MVT::v1024i1: return "MVT::v1024i1"; 93 case MVT::v1i8: return "MVT::v1i8"; 94 case MVT::v2i8: return "MVT::v2i8"; 95 case MVT::v4i8: return "MVT::v4i8"; 96 case MVT::v8i8: return "MVT::v8i8"; 97 case MVT::v16i8: return "MVT::v16i8"; 98 case MVT::v32i8: return "MVT::v32i8"; 99 case MVT::v64i8: return "MVT::v64i8"; 100 case MVT::v128i8: return "MVT::v128i8"; 101 case MVT::v256i8: return "MVT::v256i8"; 102 case MVT::v1i16: return "MVT::v1i16"; 103 case MVT::v2i16: return "MVT::v2i16"; 104 case MVT::v3i16: return "MVT::v3i16"; 105 case MVT::v4i16: return "MVT::v4i16"; 106 case MVT::v8i16: return "MVT::v8i16"; 107 case MVT::v16i16: return "MVT::v16i16"; 108 case MVT::v32i16: return "MVT::v32i16"; 109 case MVT::v64i16: return "MVT::v64i16"; 110 case MVT::v128i16: return "MVT::v128i16"; 111 case MVT::v1i32: return "MVT::v1i32"; 112 case MVT::v2i32: return "MVT::v2i32"; 113 case MVT::v3i32: return "MVT::v3i32"; 114 case MVT::v4i32: return "MVT::v4i32"; 115 case MVT::v5i32: return "MVT::v5i32"; 116 case MVT::v8i32: return "MVT::v8i32"; 117 case MVT::v16i32: return "MVT::v16i32"; 118 case MVT::v32i32: return "MVT::v32i32"; 119 case MVT::v64i32: return "MVT::v64i32"; 120 case MVT::v128i32: return "MVT::v128i32"; 121 case MVT::v256i32: return "MVT::v256i32"; 122 case MVT::v512i32: return "MVT::v512i32"; 123 case MVT::v1024i32: return "MVT::v1024i32"; 124 case MVT::v2048i32: return "MVT::v2048i32"; 125 case MVT::v1i64: return "MVT::v1i64"; 126 case MVT::v2i64: return "MVT::v2i64"; 127 case MVT::v4i64: return "MVT::v4i64"; 128 case MVT::v8i64: return "MVT::v8i64"; 129 case MVT::v16i64: return "MVT::v16i64"; 130 case MVT::v32i64: return "MVT::v32i64"; 131 case MVT::v64i64: return "MVT::v64i64"; 132 case MVT::v128i64: return "MVT::v128i64"; 133 case MVT::v256i64: return "MVT::v256i64"; 134 case MVT::v1i128: return "MVT::v1i128"; 135 case MVT::v2f16: return "MVT::v2f16"; 136 case MVT::v3f16: return "MVT::v3f16"; 137 case MVT::v4f16: return "MVT::v4f16"; 138 case MVT::v8f16: return "MVT::v8f16"; 139 case MVT::v16f16: return "MVT::v16f16"; 140 case MVT::v32f16: return "MVT::v32f16"; 141 case MVT::v64f16: return "MVT::v64f16"; 142 case MVT::v128f16: return "MVT::v128f16"; 143 case MVT::v2bf16: return "MVT::v2bf16"; 144 case MVT::v3bf16: return "MVT::v3bf16"; 145 case MVT::v4bf16: return "MVT::v4bf16"; 146 case MVT::v8bf16: return "MVT::v8bf16"; 147 case MVT::v16bf16: return "MVT::v16bf16"; 148 case MVT::v32bf16: return "MVT::v32bf16"; 149 case MVT::v64bf16: return "MVT::v64bf16"; 150 case MVT::v128bf16: return "MVT::v128bf16"; 151 case MVT::v1f32: return "MVT::v1f32"; 152 case MVT::v2f32: return "MVT::v2f32"; 153 case MVT::v3f32: return "MVT::v3f32"; 154 case MVT::v4f32: return "MVT::v4f32"; 155 case MVT::v5f32: return "MVT::v5f32"; 156 case MVT::v8f32: return "MVT::v8f32"; 157 case MVT::v16f32: return "MVT::v16f32"; 158 case MVT::v32f32: return "MVT::v32f32"; 159 case MVT::v64f32: return "MVT::v64f32"; 160 case MVT::v128f32: return "MVT::v128f32"; 161 case MVT::v256f32: return "MVT::v256f32"; 162 case MVT::v512f32: return "MVT::v512f32"; 163 case MVT::v1024f32: return "MVT::v1024f32"; 164 case MVT::v2048f32: return "MVT::v2048f32"; 165 case MVT::v1f64: return "MVT::v1f64"; 166 case MVT::v2f64: return "MVT::v2f64"; 167 case MVT::v4f64: return "MVT::v4f64"; 168 case MVT::v8f64: return "MVT::v8f64"; 169 case MVT::v16f64: return "MVT::v16f64"; 170 case MVT::v32f64: return "MVT::v32f64"; 171 case MVT::v64f64: return "MVT::v64f64"; 172 case MVT::v128f64: return "MVT::v128f64"; 173 case MVT::v256f64: return "MVT::v256f64"; 174 case MVT::nxv1i1: return "MVT::nxv1i1"; 175 case MVT::nxv2i1: return "MVT::nxv2i1"; 176 case MVT::nxv4i1: return "MVT::nxv4i1"; 177 case MVT::nxv8i1: return "MVT::nxv8i1"; 178 case MVT::nxv16i1: return "MVT::nxv16i1"; 179 case MVT::nxv32i1: return "MVT::nxv32i1"; 180 case MVT::nxv64i1: return "MVT::nxv64i1"; 181 case MVT::nxv1i8: return "MVT::nxv1i8"; 182 case MVT::nxv2i8: return "MVT::nxv2i8"; 183 case MVT::nxv4i8: return "MVT::nxv4i8"; 184 case MVT::nxv8i8: return "MVT::nxv8i8"; 185 case MVT::nxv16i8: return "MVT::nxv16i8"; 186 case MVT::nxv32i8: return "MVT::nxv32i8"; 187 case MVT::nxv64i8: return "MVT::nxv64i8"; 188 case MVT::nxv1i16: return "MVT::nxv1i16"; 189 case MVT::nxv2i16: return "MVT::nxv2i16"; 190 case MVT::nxv4i16: return "MVT::nxv4i16"; 191 case MVT::nxv8i16: return "MVT::nxv8i16"; 192 case MVT::nxv16i16: return "MVT::nxv16i16"; 193 case MVT::nxv32i16: return "MVT::nxv32i16"; 194 case MVT::nxv1i32: return "MVT::nxv1i32"; 195 case MVT::nxv2i32: return "MVT::nxv2i32"; 196 case MVT::nxv4i32: return "MVT::nxv4i32"; 197 case MVT::nxv8i32: return "MVT::nxv8i32"; 198 case MVT::nxv16i32: return "MVT::nxv16i32"; 199 case MVT::nxv32i32: return "MVT::nxv32i32"; 200 case MVT::nxv1i64: return "MVT::nxv1i64"; 201 case MVT::nxv2i64: return "MVT::nxv2i64"; 202 case MVT::nxv4i64: return "MVT::nxv4i64"; 203 case MVT::nxv8i64: return "MVT::nxv8i64"; 204 case MVT::nxv16i64: return "MVT::nxv16i64"; 205 case MVT::nxv32i64: return "MVT::nxv32i64"; 206 case MVT::nxv1f16: return "MVT::nxv1f16"; 207 case MVT::nxv2f16: return "MVT::nxv2f16"; 208 case MVT::nxv4f16: return "MVT::nxv4f16"; 209 case MVT::nxv8f16: return "MVT::nxv8f16"; 210 case MVT::nxv16f16: return "MVT::nxv16f16"; 211 case MVT::nxv32f16: return "MVT::nxv32f16"; 212 case MVT::nxv2bf16: return "MVT::nxv2bf16"; 213 case MVT::nxv4bf16: return "MVT::nxv4bf16"; 214 case MVT::nxv8bf16: return "MVT::nxv8bf16"; 215 case MVT::nxv1f32: return "MVT::nxv1f32"; 216 case MVT::nxv2f32: return "MVT::nxv2f32"; 217 case MVT::nxv4f32: return "MVT::nxv4f32"; 218 case MVT::nxv8f32: return "MVT::nxv8f32"; 219 case MVT::nxv16f32: return "MVT::nxv16f32"; 220 case MVT::nxv1f64: return "MVT::nxv1f64"; 221 case MVT::nxv2f64: return "MVT::nxv2f64"; 222 case MVT::nxv4f64: return "MVT::nxv4f64"; 223 case MVT::nxv8f64: return "MVT::nxv8f64"; 224 case MVT::token: return "MVT::token"; 225 case MVT::Metadata: return "MVT::Metadata"; 226 case MVT::iPTR: return "MVT::iPTR"; 227 case MVT::iPTRAny: return "MVT::iPTRAny"; 228 case MVT::Untyped: return "MVT::Untyped"; 229 case MVT::funcref: return "MVT::funcref"; 230 case MVT::externref: return "MVT::externref"; 231 default: llvm_unreachable("ILLEGAL VALUE TYPE!"); 232 } 233 } 234 235 /// getQualifiedName - Return the name of the specified record, with a 236 /// namespace qualifier if the record contains one. 237 /// 238 std::string llvm::getQualifiedName(const Record *R) { 239 std::string Namespace; 240 if (R->getValue("Namespace")) 241 Namespace = std::string(R->getValueAsString("Namespace")); 242 if (Namespace.empty()) 243 return std::string(R->getName()); 244 return Namespace + "::" + R->getName().str(); 245 } 246 247 248 /// getTarget - Return the current instance of the Target class. 249 /// 250 CodeGenTarget::CodeGenTarget(RecordKeeper &records) 251 : Records(records), CGH(records) { 252 std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target"); 253 if (Targets.size() == 0) 254 PrintFatalError("ERROR: No 'Target' subclasses defined!"); 255 if (Targets.size() != 1) 256 PrintFatalError("ERROR: Multiple subclasses of Target defined!"); 257 TargetRec = Targets[0]; 258 } 259 260 CodeGenTarget::~CodeGenTarget() { 261 } 262 263 const StringRef CodeGenTarget::getName() const { 264 return TargetRec->getName(); 265 } 266 267 /// getInstNamespace - Find and return the target machine's instruction 268 /// namespace. The namespace is cached because it is requested multiple times. 269 StringRef CodeGenTarget::getInstNamespace() const { 270 if (InstNamespace.empty()) { 271 for (const CodeGenInstruction *Inst : getInstructionsByEnumValue()) { 272 // We are not interested in the "TargetOpcode" namespace. 273 if (Inst->Namespace != "TargetOpcode") { 274 InstNamespace = Inst->Namespace; 275 break; 276 } 277 } 278 } 279 280 return InstNamespace; 281 } 282 283 StringRef CodeGenTarget::getRegNamespace() const { 284 auto &RegClasses = RegBank->getRegClasses(); 285 return RegClasses.size() > 0 ? RegClasses.front().Namespace : ""; 286 } 287 288 Record *CodeGenTarget::getInstructionSet() const { 289 return TargetRec->getValueAsDef("InstructionSet"); 290 } 291 292 bool CodeGenTarget::getAllowRegisterRenaming() const { 293 return TargetRec->getValueAsInt("AllowRegisterRenaming"); 294 } 295 296 /// getAsmParser - Return the AssemblyParser definition for this target. 297 /// 298 Record *CodeGenTarget::getAsmParser() const { 299 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers"); 300 if (AsmParserNum >= LI.size()) 301 PrintFatalError("Target does not have an AsmParser #" + 302 Twine(AsmParserNum) + "!"); 303 return LI[AsmParserNum]; 304 } 305 306 /// getAsmParserVariant - Return the AssemblyParserVariant definition for 307 /// this target. 308 /// 309 Record *CodeGenTarget::getAsmParserVariant(unsigned i) const { 310 std::vector<Record*> LI = 311 TargetRec->getValueAsListOfDefs("AssemblyParserVariants"); 312 if (i >= LI.size()) 313 PrintFatalError("Target does not have an AsmParserVariant #" + Twine(i) + 314 "!"); 315 return LI[i]; 316 } 317 318 /// getAsmParserVariantCount - Return the AssemblyParserVariant definition 319 /// available for this target. 320 /// 321 unsigned CodeGenTarget::getAsmParserVariantCount() const { 322 std::vector<Record*> LI = 323 TargetRec->getValueAsListOfDefs("AssemblyParserVariants"); 324 return LI.size(); 325 } 326 327 /// getAsmWriter - Return the AssemblyWriter definition for this target. 328 /// 329 Record *CodeGenTarget::getAsmWriter() const { 330 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters"); 331 if (AsmWriterNum >= LI.size()) 332 PrintFatalError("Target does not have an AsmWriter #" + 333 Twine(AsmWriterNum) + "!"); 334 return LI[AsmWriterNum]; 335 } 336 337 CodeGenRegBank &CodeGenTarget::getRegBank() const { 338 if (!RegBank) 339 RegBank = std::make_unique<CodeGenRegBank>(Records, getHwModes()); 340 return *RegBank; 341 } 342 343 Optional<CodeGenRegisterClass *> 344 CodeGenTarget::getSuperRegForSubReg(const ValueTypeByHwMode &ValueTy, 345 CodeGenRegBank &RegBank, 346 const CodeGenSubRegIndex *SubIdx, 347 bool MustBeAllocatable) const { 348 std::vector<CodeGenRegisterClass *> Candidates; 349 auto &RegClasses = RegBank.getRegClasses(); 350 351 // Try to find a register class which supports ValueTy, and also contains 352 // SubIdx. 353 for (CodeGenRegisterClass &RC : RegClasses) { 354 // Is there a subclass of this class which contains this subregister index? 355 CodeGenRegisterClass *SubClassWithSubReg = RC.getSubClassWithSubReg(SubIdx); 356 if (!SubClassWithSubReg) 357 continue; 358 359 // We have a class. Check if it supports this value type. 360 if (!llvm::is_contained(SubClassWithSubReg->VTs, ValueTy)) 361 continue; 362 363 // If necessary, check that it is allocatable. 364 if (MustBeAllocatable && !SubClassWithSubReg->Allocatable) 365 continue; 366 367 // We have a register class which supports both the value type and 368 // subregister index. Remember it. 369 Candidates.push_back(SubClassWithSubReg); 370 } 371 372 // If we didn't find anything, we're done. 373 if (Candidates.empty()) 374 return None; 375 376 // Find and return the largest of our candidate classes. 377 llvm::stable_sort(Candidates, [&](const CodeGenRegisterClass *A, 378 const CodeGenRegisterClass *B) { 379 if (A->getMembers().size() > B->getMembers().size()) 380 return true; 381 382 if (A->getMembers().size() < B->getMembers().size()) 383 return false; 384 385 // Order by name as a tie-breaker. 386 return StringRef(A->getName()) < B->getName(); 387 }); 388 389 return Candidates[0]; 390 } 391 392 void CodeGenTarget::ReadRegAltNameIndices() const { 393 RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex"); 394 llvm::sort(RegAltNameIndices, LessRecord()); 395 } 396 397 /// getRegisterByName - If there is a register with the specific AsmName, 398 /// return it. 399 const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const { 400 return getRegBank().getRegistersByName().lookup(Name); 401 } 402 403 std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R) 404 const { 405 const CodeGenRegister *Reg = getRegBank().getReg(R); 406 std::vector<ValueTypeByHwMode> Result; 407 for (const auto &RC : getRegBank().getRegClasses()) { 408 if (RC.contains(Reg)) { 409 ArrayRef<ValueTypeByHwMode> InVTs = RC.getValueTypes(); 410 llvm::append_range(Result, InVTs); 411 } 412 } 413 414 // Remove duplicates. 415 llvm::sort(Result); 416 Result.erase(std::unique(Result.begin(), Result.end()), Result.end()); 417 return Result; 418 } 419 420 421 void CodeGenTarget::ReadLegalValueTypes() const { 422 for (const auto &RC : getRegBank().getRegClasses()) 423 llvm::append_range(LegalValueTypes, RC.VTs); 424 425 // Remove duplicates. 426 llvm::sort(LegalValueTypes); 427 LegalValueTypes.erase(std::unique(LegalValueTypes.begin(), 428 LegalValueTypes.end()), 429 LegalValueTypes.end()); 430 } 431 432 CodeGenSchedModels &CodeGenTarget::getSchedModels() const { 433 if (!SchedModels) 434 SchedModels = std::make_unique<CodeGenSchedModels>(Records, *this); 435 return *SchedModels; 436 } 437 438 void CodeGenTarget::ReadInstructions() const { 439 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction"); 440 if (Insts.size() <= 2) 441 PrintFatalError("No 'Instruction' subclasses defined!"); 442 443 // Parse the instructions defined in the .td file. 444 for (unsigned i = 0, e = Insts.size(); i != e; ++i) 445 Instructions[Insts[i]] = std::make_unique<CodeGenInstruction>(Insts[i]); 446 } 447 448 static const CodeGenInstruction * 449 GetInstByName(const char *Name, 450 const DenseMap<const Record*, 451 std::unique_ptr<CodeGenInstruction>> &Insts, 452 RecordKeeper &Records) { 453 const Record *Rec = Records.getDef(Name); 454 455 const auto I = Insts.find(Rec); 456 if (!Rec || I == Insts.end()) 457 PrintFatalError(Twine("Could not find '") + Name + "' instruction!"); 458 return I->second.get(); 459 } 460 461 static const char *const FixedInstrs[] = { 462 #define HANDLE_TARGET_OPCODE(OPC) #OPC, 463 #include "llvm/Support/TargetOpcodes.def" 464 nullptr}; 465 466 unsigned CodeGenTarget::getNumFixedInstructions() { 467 return array_lengthof(FixedInstrs) - 1; 468 } 469 470 /// Return all of the instructions defined by the target, ordered by 471 /// their enum value. 472 void CodeGenTarget::ComputeInstrsByEnum() const { 473 const auto &Insts = getInstructions(); 474 for (const char *const *p = FixedInstrs; *p; ++p) { 475 const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records); 476 assert(Instr && "Missing target independent instruction"); 477 assert(Instr->Namespace == "TargetOpcode" && "Bad namespace"); 478 InstrsByEnum.push_back(Instr); 479 } 480 unsigned EndOfPredefines = InstrsByEnum.size(); 481 assert(EndOfPredefines == getNumFixedInstructions() && 482 "Missing generic opcode"); 483 484 for (const auto &I : Insts) { 485 const CodeGenInstruction *CGI = I.second.get(); 486 if (CGI->Namespace != "TargetOpcode") { 487 InstrsByEnum.push_back(CGI); 488 if (CGI->TheDef->getValueAsBit("isPseudo")) 489 ++NumPseudoInstructions; 490 } 491 } 492 493 assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr"); 494 495 // All of the instructions are now in random order based on the map iteration. 496 llvm::sort( 497 InstrsByEnum.begin() + EndOfPredefines, InstrsByEnum.end(), 498 [](const CodeGenInstruction *Rec1, const CodeGenInstruction *Rec2) { 499 const auto &D1 = *Rec1->TheDef; 500 const auto &D2 = *Rec2->TheDef; 501 return std::make_tuple(!D1.getValueAsBit("isPseudo"), D1.getName()) < 502 std::make_tuple(!D2.getValueAsBit("isPseudo"), D2.getName()); 503 }); 504 } 505 506 507 /// isLittleEndianEncoding - Return whether this target encodes its instruction 508 /// in little-endian format, i.e. bits laid out in the order [0..n] 509 /// 510 bool CodeGenTarget::isLittleEndianEncoding() const { 511 return getInstructionSet()->getValueAsBit("isLittleEndianEncoding"); 512 } 513 514 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit 515 /// encodings, reverse the bit order of all instructions. 516 void CodeGenTarget::reverseBitsForLittleEndianEncoding() { 517 if (!isLittleEndianEncoding()) 518 return; 519 520 std::vector<Record *> Insts = 521 Records.getAllDerivedDefinitions("InstructionEncoding"); 522 for (Record *R : Insts) { 523 if (R->getValueAsString("Namespace") == "TargetOpcode" || 524 R->getValueAsBit("isPseudo")) 525 continue; 526 527 BitsInit *BI = R->getValueAsBitsInit("Inst"); 528 529 unsigned numBits = BI->getNumBits(); 530 531 SmallVector<Init *, 16> NewBits(numBits); 532 533 for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) { 534 unsigned bitSwapIdx = numBits - bit - 1; 535 Init *OrigBit = BI->getBit(bit); 536 Init *BitSwap = BI->getBit(bitSwapIdx); 537 NewBits[bit] = BitSwap; 538 NewBits[bitSwapIdx] = OrigBit; 539 } 540 if (numBits % 2) { 541 unsigned middle = (numBits + 1) / 2; 542 NewBits[middle] = BI->getBit(middle); 543 } 544 545 BitsInit *NewBI = BitsInit::get(NewBits); 546 547 // Update the bits in reversed order so that emitInstrOpBits will get the 548 // correct endianness. 549 R->getValue("Inst")->setValue(NewBI); 550 } 551 } 552 553 /// guessInstructionProperties - Return true if it's OK to guess instruction 554 /// properties instead of raising an error. 555 /// 556 /// This is configurable as a temporary migration aid. It will eventually be 557 /// permanently false. 558 bool CodeGenTarget::guessInstructionProperties() const { 559 return getInstructionSet()->getValueAsBit("guessInstructionProperties"); 560 } 561 562 //===----------------------------------------------------------------------===// 563 // ComplexPattern implementation 564 // 565 ComplexPattern::ComplexPattern(Record *R) { 566 Ty = ::getValueType(R->getValueAsDef("Ty")); 567 NumOperands = R->getValueAsInt("NumOperands"); 568 SelectFunc = std::string(R->getValueAsString("SelectFunc")); 569 RootNodes = R->getValueAsListOfDefs("RootNodes"); 570 571 // FIXME: This is a hack to statically increase the priority of patterns which 572 // maps a sub-dag to a complex pattern. e.g. favors LEA over ADD. To get best 573 // possible pattern match we'll need to dynamically calculate the complexity 574 // of all patterns a dag can potentially map to. 575 int64_t RawComplexity = R->getValueAsInt("Complexity"); 576 if (RawComplexity == -1) 577 Complexity = NumOperands * 3; 578 else 579 Complexity = RawComplexity; 580 581 // FIXME: Why is this different from parseSDPatternOperatorProperties? 582 // Parse the properties. 583 Properties = 0; 584 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties"); 585 for (unsigned i = 0, e = PropList.size(); i != e; ++i) 586 if (PropList[i]->getName() == "SDNPHasChain") { 587 Properties |= 1 << SDNPHasChain; 588 } else if (PropList[i]->getName() == "SDNPOptInGlue") { 589 Properties |= 1 << SDNPOptInGlue; 590 } else if (PropList[i]->getName() == "SDNPMayStore") { 591 Properties |= 1 << SDNPMayStore; 592 } else if (PropList[i]->getName() == "SDNPMayLoad") { 593 Properties |= 1 << SDNPMayLoad; 594 } else if (PropList[i]->getName() == "SDNPSideEffect") { 595 Properties |= 1 << SDNPSideEffect; 596 } else if (PropList[i]->getName() == "SDNPMemOperand") { 597 Properties |= 1 << SDNPMemOperand; 598 } else if (PropList[i]->getName() == "SDNPVariadic") { 599 Properties |= 1 << SDNPVariadic; 600 } else if (PropList[i]->getName() == "SDNPWantRoot") { 601 Properties |= 1 << SDNPWantRoot; 602 } else if (PropList[i]->getName() == "SDNPWantParent") { 603 Properties |= 1 << SDNPWantParent; 604 } else { 605 PrintFatalError(R->getLoc(), "Unsupported SD Node property '" + 606 PropList[i]->getName() + 607 "' on ComplexPattern '" + R->getName() + 608 "'!"); 609 } 610 } 611 612 //===----------------------------------------------------------------------===// 613 // CodeGenIntrinsic Implementation 614 //===----------------------------------------------------------------------===// 615 616 CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC) { 617 std::vector<Record *> IntrProperties = 618 RC.getAllDerivedDefinitions("IntrinsicProperty"); 619 620 std::vector<Record *> DefaultProperties; 621 for (Record *Rec : IntrProperties) 622 if (Rec->getValueAsBit("IsDefault")) 623 DefaultProperties.push_back(Rec); 624 625 std::vector<Record *> Defs = RC.getAllDerivedDefinitions("Intrinsic"); 626 Intrinsics.reserve(Defs.size()); 627 628 for (unsigned I = 0, e = Defs.size(); I != e; ++I) 629 Intrinsics.push_back(CodeGenIntrinsic(Defs[I], DefaultProperties)); 630 631 llvm::sort(Intrinsics, 632 [](const CodeGenIntrinsic &LHS, const CodeGenIntrinsic &RHS) { 633 return std::tie(LHS.TargetPrefix, LHS.Name) < 634 std::tie(RHS.TargetPrefix, RHS.Name); 635 }); 636 Targets.push_back({"", 0, 0}); 637 for (size_t I = 0, E = Intrinsics.size(); I < E; ++I) 638 if (Intrinsics[I].TargetPrefix != Targets.back().Name) { 639 Targets.back().Count = I - Targets.back().Offset; 640 Targets.push_back({Intrinsics[I].TargetPrefix, I, 0}); 641 } 642 Targets.back().Count = Intrinsics.size() - Targets.back().Offset; 643 } 644 645 CodeGenIntrinsic::CodeGenIntrinsic(Record *R, 646 std::vector<Record *> DefaultProperties) { 647 TheDef = R; 648 std::string DefName = std::string(R->getName()); 649 ArrayRef<SMLoc> DefLoc = R->getLoc(); 650 ModRef = ReadWriteMem; 651 Properties = 0; 652 isOverloaded = false; 653 isCommutative = false; 654 canThrow = false; 655 isNoReturn = false; 656 isNoSync = false; 657 isNoFree = false; 658 isWillReturn = false; 659 isCold = false; 660 isNoDuplicate = false; 661 isConvergent = false; 662 isSpeculatable = false; 663 hasSideEffects = false; 664 665 if (DefName.size() <= 4 || 666 std::string(DefName.begin(), DefName.begin() + 4) != "int_") 667 PrintFatalError(DefLoc, 668 "Intrinsic '" + DefName + "' does not start with 'int_'!"); 669 670 EnumName = std::string(DefName.begin()+4, DefName.end()); 671 672 if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field. 673 GCCBuiltinName = std::string(R->getValueAsString("GCCBuiltinName")); 674 if (R->getValue("MSBuiltinName")) // Ignore a missing MSBuiltinName field. 675 MSBuiltinName = std::string(R->getValueAsString("MSBuiltinName")); 676 677 TargetPrefix = std::string(R->getValueAsString("TargetPrefix")); 678 Name = std::string(R->getValueAsString("LLVMName")); 679 680 if (Name == "") { 681 // If an explicit name isn't specified, derive one from the DefName. 682 Name = "llvm."; 683 684 for (unsigned i = 0, e = EnumName.size(); i != e; ++i) 685 Name += (EnumName[i] == '_') ? '.' : EnumName[i]; 686 } else { 687 // Verify it starts with "llvm.". 688 if (Name.size() <= 5 || 689 std::string(Name.begin(), Name.begin() + 5) != "llvm.") 690 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 691 "'s name does not start with 'llvm.'!"); 692 } 693 694 // If TargetPrefix is specified, make sure that Name starts with 695 // "llvm.<targetprefix>.". 696 if (!TargetPrefix.empty()) { 697 if (Name.size() < 6+TargetPrefix.size() || 698 std::string(Name.begin() + 5, Name.begin() + 6 + TargetPrefix.size()) 699 != (TargetPrefix + ".")) 700 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 701 "' does not start with 'llvm." + 702 TargetPrefix + ".'!"); 703 } 704 705 ListInit *RetTypes = R->getValueAsListInit("RetTypes"); 706 ListInit *ParamTypes = R->getValueAsListInit("ParamTypes"); 707 708 // First collate a list of overloaded types. 709 std::vector<MVT::SimpleValueType> OverloadedVTs; 710 for (ListInit *TypeList : {RetTypes, ParamTypes}) { 711 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 712 Record *TyEl = TypeList->getElementAsRecord(i); 713 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 714 715 if (TyEl->isSubClassOf("LLVMMatchType")) 716 continue; 717 718 MVT::SimpleValueType VT = getValueType(TyEl->getValueAsDef("VT")); 719 if (MVT(VT).isOverloaded()) { 720 OverloadedVTs.push_back(VT); 721 isOverloaded = true; 722 } 723 } 724 } 725 726 // Parse the list of return types. 727 ListInit *TypeList = RetTypes; 728 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 729 Record *TyEl = TypeList->getElementAsRecord(i); 730 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 731 MVT::SimpleValueType VT; 732 if (TyEl->isSubClassOf("LLVMMatchType")) { 733 unsigned MatchTy = TyEl->getValueAsInt("Number"); 734 assert(MatchTy < OverloadedVTs.size() && 735 "Invalid matching number!"); 736 VT = OverloadedVTs[MatchTy]; 737 // It only makes sense to use the extended and truncated vector element 738 // variants with iAny types; otherwise, if the intrinsic is not 739 // overloaded, all the types can be specified directly. 740 assert(((!TyEl->isSubClassOf("LLVMExtendedType") && 741 !TyEl->isSubClassOf("LLVMTruncatedType")) || 742 VT == MVT::iAny || VT == MVT::vAny) && 743 "Expected iAny or vAny type"); 744 } else { 745 VT = getValueType(TyEl->getValueAsDef("VT")); 746 } 747 748 // Reject invalid types. 749 if (VT == MVT::isVoid) 750 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 751 " has void in result type list!"); 752 753 IS.RetVTs.push_back(VT); 754 IS.RetTypeDefs.push_back(TyEl); 755 } 756 757 // Parse the list of parameter types. 758 TypeList = ParamTypes; 759 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 760 Record *TyEl = TypeList->getElementAsRecord(i); 761 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 762 MVT::SimpleValueType VT; 763 if (TyEl->isSubClassOf("LLVMMatchType")) { 764 unsigned MatchTy = TyEl->getValueAsInt("Number"); 765 if (MatchTy >= OverloadedVTs.size()) { 766 PrintError(R->getLoc(), 767 "Parameter #" + Twine(i) + " has out of bounds matching " 768 "number " + Twine(MatchTy)); 769 PrintFatalError(DefLoc, 770 Twine("ParamTypes is ") + TypeList->getAsString()); 771 } 772 VT = OverloadedVTs[MatchTy]; 773 // It only makes sense to use the extended and truncated vector element 774 // variants with iAny types; otherwise, if the intrinsic is not 775 // overloaded, all the types can be specified directly. 776 assert(((!TyEl->isSubClassOf("LLVMExtendedType") && 777 !TyEl->isSubClassOf("LLVMTruncatedType")) || 778 VT == MVT::iAny || VT == MVT::vAny) && 779 "Expected iAny or vAny type"); 780 } else 781 VT = getValueType(TyEl->getValueAsDef("VT")); 782 783 // Reject invalid types. 784 if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/) 785 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 786 " has void in result type list!"); 787 788 IS.ParamVTs.push_back(VT); 789 IS.ParamTypeDefs.push_back(TyEl); 790 } 791 792 // Parse the intrinsic properties. 793 ListInit *PropList = R->getValueAsListInit("IntrProperties"); 794 for (unsigned i = 0, e = PropList->size(); i != e; ++i) { 795 Record *Property = PropList->getElementAsRecord(i); 796 assert(Property->isSubClassOf("IntrinsicProperty") && 797 "Expected a property!"); 798 799 setProperty(Property); 800 } 801 802 // Set default properties to true. 803 setDefaultProperties(R, DefaultProperties); 804 805 // Also record the SDPatternOperator Properties. 806 Properties = parseSDPatternOperatorProperties(R); 807 808 // Sort the argument attributes for later benefit. 809 llvm::sort(ArgumentAttributes); 810 } 811 812 void CodeGenIntrinsic::setDefaultProperties( 813 Record *R, std::vector<Record *> DefaultProperties) { 814 // opt-out of using default attributes. 815 if (R->getValueAsBit("DisableDefaultAttributes")) 816 return; 817 818 for (Record *Rec : DefaultProperties) 819 setProperty(Rec); 820 } 821 822 void CodeGenIntrinsic::setProperty(Record *R) { 823 if (R->getName() == "IntrNoMem") 824 ModRef = NoMem; 825 else if (R->getName() == "IntrReadMem") { 826 if (!(ModRef & MR_Ref)) 827 PrintFatalError(TheDef->getLoc(), 828 Twine("IntrReadMem cannot be used after IntrNoMem or " 829 "IntrWriteMem. Default is ReadWrite")); 830 ModRef = ModRefBehavior(ModRef & ~MR_Mod); 831 } else if (R->getName() == "IntrWriteMem") { 832 if (!(ModRef & MR_Mod)) 833 PrintFatalError(TheDef->getLoc(), 834 Twine("IntrWriteMem cannot be used after IntrNoMem or " 835 "IntrReadMem. Default is ReadWrite")); 836 ModRef = ModRefBehavior(ModRef & ~MR_Ref); 837 } else if (R->getName() == "IntrArgMemOnly") 838 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem); 839 else if (R->getName() == "IntrInaccessibleMemOnly") 840 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_InaccessibleMem); 841 else if (R->getName() == "IntrInaccessibleMemOrArgMemOnly") 842 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem | 843 MR_InaccessibleMem); 844 else if (R->getName() == "Commutative") 845 isCommutative = true; 846 else if (R->getName() == "Throws") 847 canThrow = true; 848 else if (R->getName() == "IntrNoDuplicate") 849 isNoDuplicate = true; 850 else if (R->getName() == "IntrConvergent") 851 isConvergent = true; 852 else if (R->getName() == "IntrNoReturn") 853 isNoReturn = true; 854 else if (R->getName() == "IntrNoSync") 855 isNoSync = true; 856 else if (R->getName() == "IntrNoFree") 857 isNoFree = true; 858 else if (R->getName() == "IntrWillReturn") 859 isWillReturn = !isNoReturn; 860 else if (R->getName() == "IntrCold") 861 isCold = true; 862 else if (R->getName() == "IntrSpeculatable") 863 isSpeculatable = true; 864 else if (R->getName() == "IntrHasSideEffects") 865 hasSideEffects = true; 866 else if (R->isSubClassOf("NoCapture")) { 867 unsigned ArgNo = R->getValueAsInt("ArgNo"); 868 ArgumentAttributes.emplace_back(ArgNo, NoCapture, 0); 869 } else if (R->isSubClassOf("NoAlias")) { 870 unsigned ArgNo = R->getValueAsInt("ArgNo"); 871 ArgumentAttributes.emplace_back(ArgNo, NoAlias, 0); 872 } else if (R->isSubClassOf("NoUndef")) { 873 unsigned ArgNo = R->getValueAsInt("ArgNo"); 874 ArgumentAttributes.emplace_back(ArgNo, NoUndef, 0); 875 } else if (R->isSubClassOf("Returned")) { 876 unsigned ArgNo = R->getValueAsInt("ArgNo"); 877 ArgumentAttributes.emplace_back(ArgNo, Returned, 0); 878 } else if (R->isSubClassOf("ReadOnly")) { 879 unsigned ArgNo = R->getValueAsInt("ArgNo"); 880 ArgumentAttributes.emplace_back(ArgNo, ReadOnly, 0); 881 } else if (R->isSubClassOf("WriteOnly")) { 882 unsigned ArgNo = R->getValueAsInt("ArgNo"); 883 ArgumentAttributes.emplace_back(ArgNo, WriteOnly, 0); 884 } else if (R->isSubClassOf("ReadNone")) { 885 unsigned ArgNo = R->getValueAsInt("ArgNo"); 886 ArgumentAttributes.emplace_back(ArgNo, ReadNone, 0); 887 } else if (R->isSubClassOf("ImmArg")) { 888 unsigned ArgNo = R->getValueAsInt("ArgNo"); 889 ArgumentAttributes.emplace_back(ArgNo, ImmArg, 0); 890 } else if (R->isSubClassOf("Align")) { 891 unsigned ArgNo = R->getValueAsInt("ArgNo"); 892 uint64_t Align = R->getValueAsInt("Align"); 893 ArgumentAttributes.emplace_back(ArgNo, Alignment, Align); 894 } else 895 llvm_unreachable("Unknown property!"); 896 } 897 898 bool CodeGenIntrinsic::isParamAPointer(unsigned ParamIdx) const { 899 if (ParamIdx >= IS.ParamVTs.size()) 900 return false; 901 MVT ParamType = MVT(IS.ParamVTs[ParamIdx]); 902 return ParamType == MVT::iPTR || ParamType == MVT::iPTRAny; 903 } 904 905 bool CodeGenIntrinsic::isParamImmArg(unsigned ParamIdx) const { 906 // Convert argument index to attribute index starting from `FirstArgIndex`. 907 ArgAttribute Val{ParamIdx + 1, ImmArg, 0}; 908 return std::binary_search(ArgumentAttributes.begin(), 909 ArgumentAttributes.end(), Val); 910 } 911