1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class wraps target description classes used by the various code
10 // generation TableGen backends.  This makes it easier to access the data and
11 // provides a single place that needs to check it for validity.  All of these
12 // classes abort on error conditions.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "CodeGenTarget.h"
17 #include "CodeGenDAGPatterns.h"
18 #include "CodeGenIntrinsics.h"
19 #include "CodeGenSchedule.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/TableGen/Error.h"
24 #include "llvm/TableGen/Record.h"
25 #include <algorithm>
26 using namespace llvm;
27 
28 cl::OptionCategory AsmParserCat("Options for -gen-asm-parser");
29 cl::OptionCategory AsmWriterCat("Options for -gen-asm-writer");
30 
31 static cl::opt<unsigned>
32     AsmParserNum("asmparsernum", cl::init(0),
33                  cl::desc("Make -gen-asm-parser emit assembly parser #N"),
34                  cl::cat(AsmParserCat));
35 
36 static cl::opt<unsigned>
37     AsmWriterNum("asmwriternum", cl::init(0),
38                  cl::desc("Make -gen-asm-writer emit assembly writer #N"),
39                  cl::cat(AsmWriterCat));
40 
41 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
42 /// record corresponds to.
43 MVT::SimpleValueType llvm::getValueType(Record *Rec) {
44   return (MVT::SimpleValueType)Rec->getValueAsInt("Value");
45 }
46 
47 StringRef llvm::getName(MVT::SimpleValueType T) {
48   switch (T) {
49   case MVT::Other:   return "UNKNOWN";
50   case MVT::iPTR:    return "TLI.getPointerTy()";
51   case MVT::iPTRAny: return "TLI.getPointerTy()";
52   default: return getEnumName(T);
53   }
54 }
55 
56 StringRef llvm::getEnumName(MVT::SimpleValueType T) {
57   switch (T) {
58   case MVT::Other:    return "MVT::Other";
59   case MVT::i1:       return "MVT::i1";
60   case MVT::i8:       return "MVT::i8";
61   case MVT::i16:      return "MVT::i16";
62   case MVT::i32:      return "MVT::i32";
63   case MVT::i64:      return "MVT::i64";
64   case MVT::i128:     return "MVT::i128";
65   case MVT::Any:      return "MVT::Any";
66   case MVT::iAny:     return "MVT::iAny";
67   case MVT::fAny:     return "MVT::fAny";
68   case MVT::vAny:     return "MVT::vAny";
69   case MVT::f16:      return "MVT::f16";
70   case MVT::f32:      return "MVT::f32";
71   case MVT::f64:      return "MVT::f64";
72   case MVT::f80:      return "MVT::f80";
73   case MVT::f128:     return "MVT::f128";
74   case MVT::ppcf128:  return "MVT::ppcf128";
75   case MVT::x86mmx:   return "MVT::x86mmx";
76   case MVT::Glue:     return "MVT::Glue";
77   case MVT::isVoid:   return "MVT::isVoid";
78   case MVT::v1i1:     return "MVT::v1i1";
79   case MVT::v2i1:     return "MVT::v2i1";
80   case MVT::v4i1:     return "MVT::v4i1";
81   case MVT::v8i1:     return "MVT::v8i1";
82   case MVT::v16i1:    return "MVT::v16i1";
83   case MVT::v32i1:    return "MVT::v32i1";
84   case MVT::v64i1:    return "MVT::v64i1";
85   case MVT::v128i1:   return "MVT::v128i1";
86   case MVT::v512i1:   return "MVT::v512i1";
87   case MVT::v1024i1:  return "MVT::v1024i1";
88   case MVT::v1i8:     return "MVT::v1i8";
89   case MVT::v2i8:     return "MVT::v2i8";
90   case MVT::v4i8:     return "MVT::v4i8";
91   case MVT::v8i8:     return "MVT::v8i8";
92   case MVT::v16i8:    return "MVT::v16i8";
93   case MVT::v32i8:    return "MVT::v32i8";
94   case MVT::v64i8:    return "MVT::v64i8";
95   case MVT::v128i8:   return "MVT::v128i8";
96   case MVT::v256i8:   return "MVT::v256i8";
97   case MVT::v1i16:    return "MVT::v1i16";
98   case MVT::v2i16:    return "MVT::v2i16";
99   case MVT::v4i16:    return "MVT::v4i16";
100   case MVT::v8i16:    return "MVT::v8i16";
101   case MVT::v16i16:   return "MVT::v16i16";
102   case MVT::v32i16:   return "MVT::v32i16";
103   case MVT::v64i16:   return "MVT::v64i16";
104   case MVT::v128i16:  return "MVT::v128i16";
105   case MVT::v1i32:    return "MVT::v1i32";
106   case MVT::v2i32:    return "MVT::v2i32";
107   case MVT::v4i32:    return "MVT::v4i32";
108   case MVT::v8i32:    return "MVT::v8i32";
109   case MVT::v16i32:   return "MVT::v16i32";
110   case MVT::v32i32:   return "MVT::v32i32";
111   case MVT::v64i32:   return "MVT::v64i32";
112   case MVT::v1i64:    return "MVT::v1i64";
113   case MVT::v2i64:    return "MVT::v2i64";
114   case MVT::v4i64:    return "MVT::v4i64";
115   case MVT::v8i64:    return "MVT::v8i64";
116   case MVT::v16i64:   return "MVT::v16i64";
117   case MVT::v32i64:   return "MVT::v32i64";
118   case MVT::v1i128:   return "MVT::v1i128";
119   case MVT::v2f16:    return "MVT::v2f16";
120   case MVT::v4f16:    return "MVT::v4f16";
121   case MVT::v8f16:    return "MVT::v8f16";
122   case MVT::v1f32:    return "MVT::v1f32";
123   case MVT::v2f32:    return "MVT::v2f32";
124   case MVT::v4f32:    return "MVT::v4f32";
125   case MVT::v8f32:    return "MVT::v8f32";
126   case MVT::v16f32:   return "MVT::v16f32";
127   case MVT::v1f64:    return "MVT::v1f64";
128   case MVT::v2f64:    return "MVT::v2f64";
129   case MVT::v4f64:    return "MVT::v4f64";
130   case MVT::v8f64:    return "MVT::v8f64";
131   case MVT::nxv1i1:   return "MVT::nxv1i1";
132   case MVT::nxv2i1:   return "MVT::nxv2i1";
133   case MVT::nxv4i1:   return "MVT::nxv4i1";
134   case MVT::nxv8i1:   return "MVT::nxv8i1";
135   case MVT::nxv16i1:  return "MVT::nxv16i1";
136   case MVT::nxv32i1:  return "MVT::nxv32i1";
137   case MVT::nxv1i8:   return "MVT::nxv1i8";
138   case MVT::nxv2i8:   return "MVT::nxv2i8";
139   case MVT::nxv4i8:   return "MVT::nxv4i8";
140   case MVT::nxv8i8:   return "MVT::nxv8i8";
141   case MVT::nxv16i8:  return "MVT::nxv16i8";
142   case MVT::nxv32i8:  return "MVT::nxv32i8";
143   case MVT::nxv1i16:  return "MVT::nxv1i16";
144   case MVT::nxv2i16:  return "MVT::nxv2i16";
145   case MVT::nxv4i16:  return "MVT::nxv4i16";
146   case MVT::nxv8i16:  return "MVT::nxv8i16";
147   case MVT::nxv16i16: return "MVT::nxv16i16";
148   case MVT::nxv32i16: return "MVT::nxv32i16";
149   case MVT::nxv1i32:  return "MVT::nxv1i32";
150   case MVT::nxv2i32:  return "MVT::nxv2i32";
151   case MVT::nxv4i32:  return "MVT::nxv4i32";
152   case MVT::nxv8i32:  return "MVT::nxv8i32";
153   case MVT::nxv16i32: return "MVT::nxv16i32";
154   case MVT::nxv1i64:  return "MVT::nxv1i64";
155   case MVT::nxv2i64:  return "MVT::nxv2i64";
156   case MVT::nxv4i64:  return "MVT::nxv4i64";
157   case MVT::nxv8i64:  return "MVT::nxv8i64";
158   case MVT::nxv16i64: return "MVT::nxv16i64";
159   case MVT::nxv2f16:  return "MVT::nxv2f16";
160   case MVT::nxv4f16:  return "MVT::nxv4f16";
161   case MVT::nxv8f16:  return "MVT::nxv8f16";
162   case MVT::nxv1f32:  return "MVT::nxv1f32";
163   case MVT::nxv2f32:  return "MVT::nxv2f32";
164   case MVT::nxv4f32:  return "MVT::nxv4f32";
165   case MVT::nxv8f32:  return "MVT::nxv8f32";
166   case MVT::nxv16f32: return "MVT::nxv16f32";
167   case MVT::nxv1f64:  return "MVT::nxv1f64";
168   case MVT::nxv2f64:  return "MVT::nxv2f64";
169   case MVT::nxv4f64:  return "MVT::nxv4f64";
170   case MVT::nxv8f64:  return "MVT::nxv8f64";
171   case MVT::token:    return "MVT::token";
172   case MVT::Metadata: return "MVT::Metadata";
173   case MVT::iPTR:     return "MVT::iPTR";
174   case MVT::iPTRAny:  return "MVT::iPTRAny";
175   case MVT::Untyped:  return "MVT::Untyped";
176   case MVT::ExceptRef: return "MVT::ExceptRef";
177   default: llvm_unreachable("ILLEGAL VALUE TYPE!");
178   }
179 }
180 
181 /// getQualifiedName - Return the name of the specified record, with a
182 /// namespace qualifier if the record contains one.
183 ///
184 std::string llvm::getQualifiedName(const Record *R) {
185   std::string Namespace;
186   if (R->getValue("Namespace"))
187      Namespace = R->getValueAsString("Namespace");
188   if (Namespace.empty()) return R->getName();
189   return Namespace + "::" + R->getName().str();
190 }
191 
192 
193 /// getTarget - Return the current instance of the Target class.
194 ///
195 CodeGenTarget::CodeGenTarget(RecordKeeper &records)
196   : Records(records), CGH(records) {
197   std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
198   if (Targets.size() == 0)
199     PrintFatalError("ERROR: No 'Target' subclasses defined!");
200   if (Targets.size() != 1)
201     PrintFatalError("ERROR: Multiple subclasses of Target defined!");
202   TargetRec = Targets[0];
203 }
204 
205 CodeGenTarget::~CodeGenTarget() {
206 }
207 
208 const StringRef CodeGenTarget::getName() const {
209   return TargetRec->getName();
210 }
211 
212 StringRef CodeGenTarget::getInstNamespace() const {
213   for (const CodeGenInstruction *Inst : getInstructionsByEnumValue()) {
214     // Make sure not to pick up "TargetOpcode" by accidentally getting
215     // the namespace off the PHI instruction or something.
216     if (Inst->Namespace != "TargetOpcode")
217       return Inst->Namespace;
218   }
219 
220   return "";
221 }
222 
223 Record *CodeGenTarget::getInstructionSet() const {
224   return TargetRec->getValueAsDef("InstructionSet");
225 }
226 
227 bool CodeGenTarget::getAllowRegisterRenaming() const {
228   return TargetRec->getValueAsInt("AllowRegisterRenaming");
229 }
230 
231 /// getAsmParser - Return the AssemblyParser definition for this target.
232 ///
233 Record *CodeGenTarget::getAsmParser() const {
234   std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers");
235   if (AsmParserNum >= LI.size())
236     PrintFatalError("Target does not have an AsmParser #" +
237                     Twine(AsmParserNum) + "!");
238   return LI[AsmParserNum];
239 }
240 
241 /// getAsmParserVariant - Return the AssmblyParserVariant definition for
242 /// this target.
243 ///
244 Record *CodeGenTarget::getAsmParserVariant(unsigned i) const {
245   std::vector<Record*> LI =
246     TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
247   if (i >= LI.size())
248     PrintFatalError("Target does not have an AsmParserVariant #" + Twine(i) +
249                     "!");
250   return LI[i];
251 }
252 
253 /// getAsmParserVariantCount - Return the AssmblyParserVariant definition
254 /// available for this target.
255 ///
256 unsigned CodeGenTarget::getAsmParserVariantCount() const {
257   std::vector<Record*> LI =
258     TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
259   return LI.size();
260 }
261 
262 /// getAsmWriter - Return the AssemblyWriter definition for this target.
263 ///
264 Record *CodeGenTarget::getAsmWriter() const {
265   std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters");
266   if (AsmWriterNum >= LI.size())
267     PrintFatalError("Target does not have an AsmWriter #" +
268                     Twine(AsmWriterNum) + "!");
269   return LI[AsmWriterNum];
270 }
271 
272 CodeGenRegBank &CodeGenTarget::getRegBank() const {
273   if (!RegBank)
274     RegBank = llvm::make_unique<CodeGenRegBank>(Records, getHwModes());
275   return *RegBank;
276 }
277 
278 void CodeGenTarget::ReadRegAltNameIndices() const {
279   RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex");
280   llvm::sort(RegAltNameIndices, LessRecord());
281 }
282 
283 /// getRegisterByName - If there is a register with the specific AsmName,
284 /// return it.
285 const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const {
286   const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName();
287   StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name);
288   if (I == Regs.end())
289     return nullptr;
290   return I->second;
291 }
292 
293 std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R)
294       const {
295   const CodeGenRegister *Reg = getRegBank().getReg(R);
296   std::vector<ValueTypeByHwMode> Result;
297   for (const auto &RC : getRegBank().getRegClasses()) {
298     if (RC.contains(Reg)) {
299       ArrayRef<ValueTypeByHwMode> InVTs = RC.getValueTypes();
300       Result.insert(Result.end(), InVTs.begin(), InVTs.end());
301     }
302   }
303 
304   // Remove duplicates.
305   llvm::sort(Result);
306   Result.erase(std::unique(Result.begin(), Result.end()), Result.end());
307   return Result;
308 }
309 
310 
311 void CodeGenTarget::ReadLegalValueTypes() const {
312   for (const auto &RC : getRegBank().getRegClasses())
313     LegalValueTypes.insert(LegalValueTypes.end(), RC.VTs.begin(), RC.VTs.end());
314 
315   // Remove duplicates.
316   llvm::sort(LegalValueTypes);
317   LegalValueTypes.erase(std::unique(LegalValueTypes.begin(),
318                                     LegalValueTypes.end()),
319                         LegalValueTypes.end());
320 }
321 
322 CodeGenSchedModels &CodeGenTarget::getSchedModels() const {
323   if (!SchedModels)
324     SchedModels = llvm::make_unique<CodeGenSchedModels>(Records, *this);
325   return *SchedModels;
326 }
327 
328 void CodeGenTarget::ReadInstructions() const {
329   std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
330   if (Insts.size() <= 2)
331     PrintFatalError("No 'Instruction' subclasses defined!");
332 
333   // Parse the instructions defined in the .td file.
334   for (unsigned i = 0, e = Insts.size(); i != e; ++i)
335     Instructions[Insts[i]] = llvm::make_unique<CodeGenInstruction>(Insts[i]);
336 }
337 
338 static const CodeGenInstruction *
339 GetInstByName(const char *Name,
340               const DenseMap<const Record*,
341                              std::unique_ptr<CodeGenInstruction>> &Insts,
342               RecordKeeper &Records) {
343   const Record *Rec = Records.getDef(Name);
344 
345   const auto I = Insts.find(Rec);
346   if (!Rec || I == Insts.end())
347     PrintFatalError(Twine("Could not find '") + Name + "' instruction!");
348   return I->second.get();
349 }
350 
351 static const char *const FixedInstrs[] = {
352 #define HANDLE_TARGET_OPCODE(OPC) #OPC,
353 #include "llvm/Support/TargetOpcodes.def"
354     nullptr};
355 
356 unsigned CodeGenTarget::getNumFixedInstructions() {
357   return array_lengthof(FixedInstrs) - 1;
358 }
359 
360 /// Return all of the instructions defined by the target, ordered by
361 /// their enum value.
362 void CodeGenTarget::ComputeInstrsByEnum() const {
363   const auto &Insts = getInstructions();
364   for (const char *const *p = FixedInstrs; *p; ++p) {
365     const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records);
366     assert(Instr && "Missing target independent instruction");
367     assert(Instr->Namespace == "TargetOpcode" && "Bad namespace");
368     InstrsByEnum.push_back(Instr);
369   }
370   unsigned EndOfPredefines = InstrsByEnum.size();
371   assert(EndOfPredefines == getNumFixedInstructions() &&
372          "Missing generic opcode");
373 
374   for (const auto &I : Insts) {
375     const CodeGenInstruction *CGI = I.second.get();
376     if (CGI->Namespace != "TargetOpcode") {
377       InstrsByEnum.push_back(CGI);
378       if (CGI->TheDef->getValueAsBit("isPseudo"))
379         ++NumPseudoInstructions;
380     }
381   }
382 
383   assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr");
384 
385   // All of the instructions are now in random order based on the map iteration.
386   llvm::sort(
387       InstrsByEnum.begin() + EndOfPredefines, InstrsByEnum.end(),
388       [](const CodeGenInstruction *Rec1, const CodeGenInstruction *Rec2) {
389         const auto &D1 = *Rec1->TheDef;
390         const auto &D2 = *Rec2->TheDef;
391         return std::make_tuple(!D1.getValueAsBit("isPseudo"), D1.getName()) <
392                std::make_tuple(!D2.getValueAsBit("isPseudo"), D2.getName());
393       });
394 }
395 
396 
397 /// isLittleEndianEncoding - Return whether this target encodes its instruction
398 /// in little-endian format, i.e. bits laid out in the order [0..n]
399 ///
400 bool CodeGenTarget::isLittleEndianEncoding() const {
401   return getInstructionSet()->getValueAsBit("isLittleEndianEncoding");
402 }
403 
404 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit
405 /// encodings, reverse the bit order of all instructions.
406 void CodeGenTarget::reverseBitsForLittleEndianEncoding() {
407   if (!isLittleEndianEncoding())
408     return;
409 
410   std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
411   for (Record *R : Insts) {
412     if (R->getValueAsString("Namespace") == "TargetOpcode" ||
413         R->getValueAsBit("isPseudo"))
414       continue;
415 
416     BitsInit *BI = R->getValueAsBitsInit("Inst");
417 
418     unsigned numBits = BI->getNumBits();
419 
420     SmallVector<Init *, 16> NewBits(numBits);
421 
422     for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) {
423       unsigned bitSwapIdx = numBits - bit - 1;
424       Init *OrigBit = BI->getBit(bit);
425       Init *BitSwap = BI->getBit(bitSwapIdx);
426       NewBits[bit]        = BitSwap;
427       NewBits[bitSwapIdx] = OrigBit;
428     }
429     if (numBits % 2) {
430       unsigned middle = (numBits + 1) / 2;
431       NewBits[middle] = BI->getBit(middle);
432     }
433 
434     BitsInit *NewBI = BitsInit::get(NewBits);
435 
436     // Update the bits in reversed order so that emitInstrOpBits will get the
437     // correct endianness.
438     R->getValue("Inst")->setValue(NewBI);
439   }
440 }
441 
442 /// guessInstructionProperties - Return true if it's OK to guess instruction
443 /// properties instead of raising an error.
444 ///
445 /// This is configurable as a temporary migration aid. It will eventually be
446 /// permanently false.
447 bool CodeGenTarget::guessInstructionProperties() const {
448   return getInstructionSet()->getValueAsBit("guessInstructionProperties");
449 }
450 
451 //===----------------------------------------------------------------------===//
452 // ComplexPattern implementation
453 //
454 ComplexPattern::ComplexPattern(Record *R) {
455   Ty          = ::getValueType(R->getValueAsDef("Ty"));
456   NumOperands = R->getValueAsInt("NumOperands");
457   SelectFunc  = R->getValueAsString("SelectFunc");
458   RootNodes   = R->getValueAsListOfDefs("RootNodes");
459 
460   // FIXME: This is a hack to statically increase the priority of patterns which
461   // maps a sub-dag to a complex pattern. e.g. favors LEA over ADD. To get best
462   // possible pattern match we'll need to dynamically calculate the complexity
463   // of all patterns a dag can potentially map to.
464   int64_t RawComplexity = R->getValueAsInt("Complexity");
465   if (RawComplexity == -1)
466     Complexity = NumOperands * 3;
467   else
468     Complexity = RawComplexity;
469 
470   // FIXME: Why is this different from parseSDPatternOperatorProperties?
471   // Parse the properties.
472   Properties = 0;
473   std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties");
474   for (unsigned i = 0, e = PropList.size(); i != e; ++i)
475     if (PropList[i]->getName() == "SDNPHasChain") {
476       Properties |= 1 << SDNPHasChain;
477     } else if (PropList[i]->getName() == "SDNPOptInGlue") {
478       Properties |= 1 << SDNPOptInGlue;
479     } else if (PropList[i]->getName() == "SDNPMayStore") {
480       Properties |= 1 << SDNPMayStore;
481     } else if (PropList[i]->getName() == "SDNPMayLoad") {
482       Properties |= 1 << SDNPMayLoad;
483     } else if (PropList[i]->getName() == "SDNPSideEffect") {
484       Properties |= 1 << SDNPSideEffect;
485     } else if (PropList[i]->getName() == "SDNPMemOperand") {
486       Properties |= 1 << SDNPMemOperand;
487     } else if (PropList[i]->getName() == "SDNPVariadic") {
488       Properties |= 1 << SDNPVariadic;
489     } else if (PropList[i]->getName() == "SDNPWantRoot") {
490       Properties |= 1 << SDNPWantRoot;
491     } else if (PropList[i]->getName() == "SDNPWantParent") {
492       Properties |= 1 << SDNPWantParent;
493     } else {
494       PrintFatalError("Unsupported SD Node property '" +
495                       PropList[i]->getName() + "' on ComplexPattern '" +
496                       R->getName() + "'!");
497     }
498 }
499 
500 //===----------------------------------------------------------------------===//
501 // CodeGenIntrinsic Implementation
502 //===----------------------------------------------------------------------===//
503 
504 CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC,
505                                              bool TargetOnly) {
506   std::vector<Record*> Defs = RC.getAllDerivedDefinitions("Intrinsic");
507 
508   Intrinsics.reserve(Defs.size());
509 
510   for (unsigned I = 0, e = Defs.size(); I != e; ++I) {
511     bool isTarget = Defs[I]->getValueAsBit("isTarget");
512     if (isTarget == TargetOnly)
513       Intrinsics.push_back(CodeGenIntrinsic(Defs[I]));
514   }
515   llvm::sort(Intrinsics,
516              [](const CodeGenIntrinsic &LHS, const CodeGenIntrinsic &RHS) {
517                return std::tie(LHS.TargetPrefix, LHS.Name) <
518                       std::tie(RHS.TargetPrefix, RHS.Name);
519              });
520   Targets.push_back({"", 0, 0});
521   for (size_t I = 0, E = Intrinsics.size(); I < E; ++I)
522     if (Intrinsics[I].TargetPrefix != Targets.back().Name) {
523       Targets.back().Count = I - Targets.back().Offset;
524       Targets.push_back({Intrinsics[I].TargetPrefix, I, 0});
525     }
526   Targets.back().Count = Intrinsics.size() - Targets.back().Offset;
527 }
528 
529 CodeGenIntrinsic::CodeGenIntrinsic(Record *R) {
530   TheDef = R;
531   std::string DefName = R->getName();
532   ModRef = ReadWriteMem;
533   Properties = 0;
534   isOverloaded = false;
535   isCommutative = false;
536   canThrow = false;
537   isNoReturn = false;
538   isCold = false;
539   isNoDuplicate = false;
540   isConvergent = false;
541   isSpeculatable = false;
542   hasSideEffects = false;
543 
544   if (DefName.size() <= 4 ||
545       std::string(DefName.begin(), DefName.begin() + 4) != "int_")
546     PrintFatalError("Intrinsic '" + DefName + "' does not start with 'int_'!");
547 
548   EnumName = std::string(DefName.begin()+4, DefName.end());
549 
550   if (R->getValue("GCCBuiltinName"))  // Ignore a missing GCCBuiltinName field.
551     GCCBuiltinName = R->getValueAsString("GCCBuiltinName");
552   if (R->getValue("MSBuiltinName"))   // Ignore a missing MSBuiltinName field.
553     MSBuiltinName = R->getValueAsString("MSBuiltinName");
554 
555   TargetPrefix = R->getValueAsString("TargetPrefix");
556   Name = R->getValueAsString("LLVMName");
557 
558   if (Name == "") {
559     // If an explicit name isn't specified, derive one from the DefName.
560     Name = "llvm.";
561 
562     for (unsigned i = 0, e = EnumName.size(); i != e; ++i)
563       Name += (EnumName[i] == '_') ? '.' : EnumName[i];
564   } else {
565     // Verify it starts with "llvm.".
566     if (Name.size() <= 5 ||
567         std::string(Name.begin(), Name.begin() + 5) != "llvm.")
568       PrintFatalError("Intrinsic '" + DefName + "'s name does not start with 'llvm.'!");
569   }
570 
571   // If TargetPrefix is specified, make sure that Name starts with
572   // "llvm.<targetprefix>.".
573   if (!TargetPrefix.empty()) {
574     if (Name.size() < 6+TargetPrefix.size() ||
575         std::string(Name.begin() + 5, Name.begin() + 6 + TargetPrefix.size())
576         != (TargetPrefix + "."))
577       PrintFatalError("Intrinsic '" + DefName + "' does not start with 'llvm." +
578         TargetPrefix + ".'!");
579   }
580 
581   // Parse the list of return types.
582   std::vector<MVT::SimpleValueType> OverloadedVTs;
583   ListInit *TypeList = R->getValueAsListInit("RetTypes");
584   for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
585     Record *TyEl = TypeList->getElementAsRecord(i);
586     assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
587     MVT::SimpleValueType VT;
588     if (TyEl->isSubClassOf("LLVMMatchType")) {
589       unsigned MatchTy = TyEl->getValueAsInt("Number");
590       assert(MatchTy < OverloadedVTs.size() &&
591              "Invalid matching number!");
592       VT = OverloadedVTs[MatchTy];
593       // It only makes sense to use the extended and truncated vector element
594       // variants with iAny types; otherwise, if the intrinsic is not
595       // overloaded, all the types can be specified directly.
596       assert(((!TyEl->isSubClassOf("LLVMExtendedType") &&
597                !TyEl->isSubClassOf("LLVMTruncatedType")) ||
598               VT == MVT::iAny || VT == MVT::vAny) &&
599              "Expected iAny or vAny type");
600     } else {
601       VT = getValueType(TyEl->getValueAsDef("VT"));
602     }
603     if (MVT(VT).isOverloaded()) {
604       OverloadedVTs.push_back(VT);
605       isOverloaded = true;
606     }
607 
608     // Reject invalid types.
609     if (VT == MVT::isVoid)
610       PrintFatalError("Intrinsic '" + DefName + " has void in result type list!");
611 
612     IS.RetVTs.push_back(VT);
613     IS.RetTypeDefs.push_back(TyEl);
614   }
615 
616   // Parse the list of parameter types.
617   TypeList = R->getValueAsListInit("ParamTypes");
618   for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
619     Record *TyEl = TypeList->getElementAsRecord(i);
620     assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
621     MVT::SimpleValueType VT;
622     if (TyEl->isSubClassOf("LLVMMatchType")) {
623       unsigned MatchTy = TyEl->getValueAsInt("Number");
624       if (MatchTy >= OverloadedVTs.size()) {
625         PrintError(R->getLoc(),
626                    "Parameter #" + Twine(i) + " has out of bounds matching "
627                    "number " + Twine(MatchTy));
628         PrintFatalError(Twine("ParamTypes is ") + TypeList->getAsString());
629       }
630       VT = OverloadedVTs[MatchTy];
631       // It only makes sense to use the extended and truncated vector element
632       // variants with iAny types; otherwise, if the intrinsic is not
633       // overloaded, all the types can be specified directly.
634       assert(((!TyEl->isSubClassOf("LLVMExtendedType") &&
635                !TyEl->isSubClassOf("LLVMTruncatedType") &&
636                !TyEl->isSubClassOf("LLVMVectorSameWidth")) ||
637               VT == MVT::iAny || VT == MVT::vAny) &&
638              "Expected iAny or vAny type");
639     } else
640       VT = getValueType(TyEl->getValueAsDef("VT"));
641 
642     if (MVT(VT).isOverloaded()) {
643       OverloadedVTs.push_back(VT);
644       isOverloaded = true;
645     }
646 
647     // Reject invalid types.
648     if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/)
649       PrintFatalError("Intrinsic '" + DefName + " has void in result type list!");
650 
651     IS.ParamVTs.push_back(VT);
652     IS.ParamTypeDefs.push_back(TyEl);
653   }
654 
655   // Parse the intrinsic properties.
656   ListInit *PropList = R->getValueAsListInit("IntrProperties");
657   for (unsigned i = 0, e = PropList->size(); i != e; ++i) {
658     Record *Property = PropList->getElementAsRecord(i);
659     assert(Property->isSubClassOf("IntrinsicProperty") &&
660            "Expected a property!");
661 
662     if (Property->getName() == "IntrNoMem")
663       ModRef = NoMem;
664     else if (Property->getName() == "IntrReadMem")
665       ModRef = ModRefBehavior(ModRef & ~MR_Mod);
666     else if (Property->getName() == "IntrWriteMem")
667       ModRef = ModRefBehavior(ModRef & ~MR_Ref);
668     else if (Property->getName() == "IntrArgMemOnly")
669       ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem);
670     else if (Property->getName() == "IntrInaccessibleMemOnly")
671       ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_InaccessibleMem);
672     else if (Property->getName() == "IntrInaccessibleMemOrArgMemOnly")
673       ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem |
674                               MR_InaccessibleMem);
675     else if (Property->getName() == "Commutative")
676       isCommutative = true;
677     else if (Property->getName() == "Throws")
678       canThrow = true;
679     else if (Property->getName() == "IntrNoDuplicate")
680       isNoDuplicate = true;
681     else if (Property->getName() == "IntrConvergent")
682       isConvergent = true;
683     else if (Property->getName() == "IntrNoReturn")
684       isNoReturn = true;
685     else if (Property->getName() == "IntrCold")
686       isCold = true;
687     else if (Property->getName() == "IntrSpeculatable")
688       isSpeculatable = true;
689     else if (Property->getName() == "IntrHasSideEffects")
690       hasSideEffects = true;
691     else if (Property->isSubClassOf("NoCapture")) {
692       unsigned ArgNo = Property->getValueAsInt("ArgNo");
693       ArgumentAttributes.push_back(std::make_pair(ArgNo, NoCapture));
694     } else if (Property->isSubClassOf("Returned")) {
695       unsigned ArgNo = Property->getValueAsInt("ArgNo");
696       ArgumentAttributes.push_back(std::make_pair(ArgNo, Returned));
697     } else if (Property->isSubClassOf("ReadOnly")) {
698       unsigned ArgNo = Property->getValueAsInt("ArgNo");
699       ArgumentAttributes.push_back(std::make_pair(ArgNo, ReadOnly));
700     } else if (Property->isSubClassOf("WriteOnly")) {
701       unsigned ArgNo = Property->getValueAsInt("ArgNo");
702       ArgumentAttributes.push_back(std::make_pair(ArgNo, WriteOnly));
703     } else if (Property->isSubClassOf("ReadNone")) {
704       unsigned ArgNo = Property->getValueAsInt("ArgNo");
705       ArgumentAttributes.push_back(std::make_pair(ArgNo, ReadNone));
706     } else
707       llvm_unreachable("Unknown property!");
708   }
709 
710   // Also record the SDPatternOperator Properties.
711   Properties = parseSDPatternOperatorProperties(R);
712 
713   // Sort the argument attributes for later benefit.
714   llvm::sort(ArgumentAttributes);
715 }
716