1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This class wraps target description classes used by the various code 10 // generation TableGen backends. This makes it easier to access the data and 11 // provides a single place that needs to check it for validity. All of these 12 // classes abort on error conditions. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "CodeGenTarget.h" 17 #include "CodeGenDAGPatterns.h" 18 #include "CodeGenIntrinsics.h" 19 #include "CodeGenSchedule.h" 20 #include "llvm/ADT/STLExtras.h" 21 #include "llvm/ADT/StringExtras.h" 22 #include "llvm/Support/CommandLine.h" 23 #include "llvm/Support/Timer.h" 24 #include "llvm/TableGen/Error.h" 25 #include "llvm/TableGen/Record.h" 26 #include "llvm/TableGen/TableGenBackend.h" 27 #include <algorithm> 28 using namespace llvm; 29 30 cl::OptionCategory AsmParserCat("Options for -gen-asm-parser"); 31 cl::OptionCategory AsmWriterCat("Options for -gen-asm-writer"); 32 33 static cl::opt<unsigned> 34 AsmParserNum("asmparsernum", cl::init(0), 35 cl::desc("Make -gen-asm-parser emit assembly parser #N"), 36 cl::cat(AsmParserCat)); 37 38 static cl::opt<unsigned> 39 AsmWriterNum("asmwriternum", cl::init(0), 40 cl::desc("Make -gen-asm-writer emit assembly writer #N"), 41 cl::cat(AsmWriterCat)); 42 43 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen 44 /// record corresponds to. 45 MVT::SimpleValueType llvm::getValueType(Record *Rec) { 46 return (MVT::SimpleValueType)Rec->getValueAsInt("Value"); 47 } 48 49 StringRef llvm::getName(MVT::SimpleValueType T) { 50 switch (T) { 51 case MVT::Other: return "UNKNOWN"; 52 case MVT::iPTR: return "TLI.getPointerTy()"; 53 case MVT::iPTRAny: return "TLI.getPointerTy()"; 54 default: return getEnumName(T); 55 } 56 } 57 58 StringRef llvm::getEnumName(MVT::SimpleValueType T) { 59 switch (T) { 60 case MVT::Other: return "MVT::Other"; 61 case MVT::i1: return "MVT::i1"; 62 case MVT::i8: return "MVT::i8"; 63 case MVT::i16: return "MVT::i16"; 64 case MVT::i32: return "MVT::i32"; 65 case MVT::i64: return "MVT::i64"; 66 case MVT::i128: return "MVT::i128"; 67 case MVT::Any: return "MVT::Any"; 68 case MVT::iAny: return "MVT::iAny"; 69 case MVT::fAny: return "MVT::fAny"; 70 case MVT::vAny: return "MVT::vAny"; 71 case MVT::f16: return "MVT::f16"; 72 case MVT::bf16: return "MVT::bf16"; 73 case MVT::f32: return "MVT::f32"; 74 case MVT::f64: return "MVT::f64"; 75 case MVT::f80: return "MVT::f80"; 76 case MVT::f128: return "MVT::f128"; 77 case MVT::ppcf128: return "MVT::ppcf128"; 78 case MVT::x86mmx: return "MVT::x86mmx"; 79 case MVT::x86amx: return "MVT::x86amx"; 80 case MVT::Glue: return "MVT::Glue"; 81 case MVT::isVoid: return "MVT::isVoid"; 82 case MVT::v1i1: return "MVT::v1i1"; 83 case MVT::v2i1: return "MVT::v2i1"; 84 case MVT::v4i1: return "MVT::v4i1"; 85 case MVT::v8i1: return "MVT::v8i1"; 86 case MVT::v16i1: return "MVT::v16i1"; 87 case MVT::v32i1: return "MVT::v32i1"; 88 case MVT::v64i1: return "MVT::v64i1"; 89 case MVT::v128i1: return "MVT::v128i1"; 90 case MVT::v256i1: return "MVT::v256i1"; 91 case MVT::v512i1: return "MVT::v512i1"; 92 case MVT::v1024i1: return "MVT::v1024i1"; 93 case MVT::v1i8: return "MVT::v1i8"; 94 case MVT::v2i8: return "MVT::v2i8"; 95 case MVT::v4i8: return "MVT::v4i8"; 96 case MVT::v8i8: return "MVT::v8i8"; 97 case MVT::v16i8: return "MVT::v16i8"; 98 case MVT::v32i8: return "MVT::v32i8"; 99 case MVT::v64i8: return "MVT::v64i8"; 100 case MVT::v128i8: return "MVT::v128i8"; 101 case MVT::v256i8: return "MVT::v256i8"; 102 case MVT::v512i8: return "MVT::v512i8"; 103 case MVT::v1024i8: return "MVT::v1024i8"; 104 case MVT::v1i16: return "MVT::v1i16"; 105 case MVT::v2i16: return "MVT::v2i16"; 106 case MVT::v3i16: return "MVT::v3i16"; 107 case MVT::v4i16: return "MVT::v4i16"; 108 case MVT::v8i16: return "MVT::v8i16"; 109 case MVT::v16i16: return "MVT::v16i16"; 110 case MVT::v32i16: return "MVT::v32i16"; 111 case MVT::v64i16: return "MVT::v64i16"; 112 case MVT::v128i16: return "MVT::v128i16"; 113 case MVT::v256i16: return "MVT::v256i16"; 114 case MVT::v512i16: return "MVT::v512i16"; 115 case MVT::v1i32: return "MVT::v1i32"; 116 case MVT::v2i32: return "MVT::v2i32"; 117 case MVT::v3i32: return "MVT::v3i32"; 118 case MVT::v4i32: return "MVT::v4i32"; 119 case MVT::v5i32: return "MVT::v5i32"; 120 case MVT::v6i32: return "MVT::v6i32"; 121 case MVT::v7i32: return "MVT::v7i32"; 122 case MVT::v8i32: return "MVT::v8i32"; 123 case MVT::v16i32: return "MVT::v16i32"; 124 case MVT::v32i32: return "MVT::v32i32"; 125 case MVT::v64i32: return "MVT::v64i32"; 126 case MVT::v128i32: return "MVT::v128i32"; 127 case MVT::v256i32: return "MVT::v256i32"; 128 case MVT::v512i32: return "MVT::v512i32"; 129 case MVT::v1024i32: return "MVT::v1024i32"; 130 case MVT::v2048i32: return "MVT::v2048i32"; 131 case MVT::v1i64: return "MVT::v1i64"; 132 case MVT::v2i64: return "MVT::v2i64"; 133 case MVT::v3i64: return "MVT::v3i64"; 134 case MVT::v4i64: return "MVT::v4i64"; 135 case MVT::v8i64: return "MVT::v8i64"; 136 case MVT::v16i64: return "MVT::v16i64"; 137 case MVT::v32i64: return "MVT::v32i64"; 138 case MVT::v64i64: return "MVT::v64i64"; 139 case MVT::v128i64: return "MVT::v128i64"; 140 case MVT::v256i64: return "MVT::v256i64"; 141 case MVT::v1i128: return "MVT::v1i128"; 142 case MVT::v1f16: return "MVT::v1f16"; 143 case MVT::v2f16: return "MVT::v2f16"; 144 case MVT::v3f16: return "MVT::v3f16"; 145 case MVT::v4f16: return "MVT::v4f16"; 146 case MVT::v8f16: return "MVT::v8f16"; 147 case MVT::v16f16: return "MVT::v16f16"; 148 case MVT::v32f16: return "MVT::v32f16"; 149 case MVT::v64f16: return "MVT::v64f16"; 150 case MVT::v128f16: return "MVT::v128f16"; 151 case MVT::v256f16: return "MVT::v256f16"; 152 case MVT::v512f16: return "MVT::v512f16"; 153 case MVT::v2bf16: return "MVT::v2bf16"; 154 case MVT::v3bf16: return "MVT::v3bf16"; 155 case MVT::v4bf16: return "MVT::v4bf16"; 156 case MVT::v8bf16: return "MVT::v8bf16"; 157 case MVT::v16bf16: return "MVT::v16bf16"; 158 case MVT::v32bf16: return "MVT::v32bf16"; 159 case MVT::v64bf16: return "MVT::v64bf16"; 160 case MVT::v128bf16: return "MVT::v128bf16"; 161 case MVT::v1f32: return "MVT::v1f32"; 162 case MVT::v2f32: return "MVT::v2f32"; 163 case MVT::v3f32: return "MVT::v3f32"; 164 case MVT::v4f32: return "MVT::v4f32"; 165 case MVT::v5f32: return "MVT::v5f32"; 166 case MVT::v6f32: return "MVT::v6f32"; 167 case MVT::v7f32: return "MVT::v7f32"; 168 case MVT::v8f32: return "MVT::v8f32"; 169 case MVT::v16f32: return "MVT::v16f32"; 170 case MVT::v32f32: return "MVT::v32f32"; 171 case MVT::v64f32: return "MVT::v64f32"; 172 case MVT::v128f32: return "MVT::v128f32"; 173 case MVT::v256f32: return "MVT::v256f32"; 174 case MVT::v512f32: return "MVT::v512f32"; 175 case MVT::v1024f32: return "MVT::v1024f32"; 176 case MVT::v2048f32: return "MVT::v2048f32"; 177 case MVT::v1f64: return "MVT::v1f64"; 178 case MVT::v2f64: return "MVT::v2f64"; 179 case MVT::v3f64: return "MVT::v3f64"; 180 case MVT::v4f64: return "MVT::v4f64"; 181 case MVT::v8f64: return "MVT::v8f64"; 182 case MVT::v16f64: return "MVT::v16f64"; 183 case MVT::v32f64: return "MVT::v32f64"; 184 case MVT::v64f64: return "MVT::v64f64"; 185 case MVT::v128f64: return "MVT::v128f64"; 186 case MVT::v256f64: return "MVT::v256f64"; 187 case MVT::nxv1i1: return "MVT::nxv1i1"; 188 case MVT::nxv2i1: return "MVT::nxv2i1"; 189 case MVT::nxv4i1: return "MVT::nxv4i1"; 190 case MVT::nxv8i1: return "MVT::nxv8i1"; 191 case MVT::nxv16i1: return "MVT::nxv16i1"; 192 case MVT::nxv32i1: return "MVT::nxv32i1"; 193 case MVT::nxv64i1: return "MVT::nxv64i1"; 194 case MVT::nxv1i8: return "MVT::nxv1i8"; 195 case MVT::nxv2i8: return "MVT::nxv2i8"; 196 case MVT::nxv4i8: return "MVT::nxv4i8"; 197 case MVT::nxv8i8: return "MVT::nxv8i8"; 198 case MVT::nxv16i8: return "MVT::nxv16i8"; 199 case MVT::nxv32i8: return "MVT::nxv32i8"; 200 case MVT::nxv64i8: return "MVT::nxv64i8"; 201 case MVT::nxv1i16: return "MVT::nxv1i16"; 202 case MVT::nxv2i16: return "MVT::nxv2i16"; 203 case MVT::nxv4i16: return "MVT::nxv4i16"; 204 case MVT::nxv8i16: return "MVT::nxv8i16"; 205 case MVT::nxv16i16: return "MVT::nxv16i16"; 206 case MVT::nxv32i16: return "MVT::nxv32i16"; 207 case MVT::nxv1i32: return "MVT::nxv1i32"; 208 case MVT::nxv2i32: return "MVT::nxv2i32"; 209 case MVT::nxv4i32: return "MVT::nxv4i32"; 210 case MVT::nxv8i32: return "MVT::nxv8i32"; 211 case MVT::nxv16i32: return "MVT::nxv16i32"; 212 case MVT::nxv32i32: return "MVT::nxv32i32"; 213 case MVT::nxv1i64: return "MVT::nxv1i64"; 214 case MVT::nxv2i64: return "MVT::nxv2i64"; 215 case MVT::nxv4i64: return "MVT::nxv4i64"; 216 case MVT::nxv8i64: return "MVT::nxv8i64"; 217 case MVT::nxv16i64: return "MVT::nxv16i64"; 218 case MVT::nxv32i64: return "MVT::nxv32i64"; 219 case MVT::nxv1f16: return "MVT::nxv1f16"; 220 case MVT::nxv2f16: return "MVT::nxv2f16"; 221 case MVT::nxv4f16: return "MVT::nxv4f16"; 222 case MVT::nxv8f16: return "MVT::nxv8f16"; 223 case MVT::nxv16f16: return "MVT::nxv16f16"; 224 case MVT::nxv32f16: return "MVT::nxv32f16"; 225 case MVT::nxv1bf16: return "MVT::nxv1bf16"; 226 case MVT::nxv2bf16: return "MVT::nxv2bf16"; 227 case MVT::nxv4bf16: return "MVT::nxv4bf16"; 228 case MVT::nxv8bf16: return "MVT::nxv8bf16"; 229 case MVT::nxv1f32: return "MVT::nxv1f32"; 230 case MVT::nxv2f32: return "MVT::nxv2f32"; 231 case MVT::nxv4f32: return "MVT::nxv4f32"; 232 case MVT::nxv8f32: return "MVT::nxv8f32"; 233 case MVT::nxv16f32: return "MVT::nxv16f32"; 234 case MVT::nxv1f64: return "MVT::nxv1f64"; 235 case MVT::nxv2f64: return "MVT::nxv2f64"; 236 case MVT::nxv4f64: return "MVT::nxv4f64"; 237 case MVT::nxv8f64: return "MVT::nxv8f64"; 238 case MVT::token: return "MVT::token"; 239 case MVT::Metadata: return "MVT::Metadata"; 240 case MVT::iPTR: return "MVT::iPTR"; 241 case MVT::iPTRAny: return "MVT::iPTRAny"; 242 case MVT::Untyped: return "MVT::Untyped"; 243 case MVT::funcref: return "MVT::funcref"; 244 case MVT::externref: return "MVT::externref"; 245 default: llvm_unreachable("ILLEGAL VALUE TYPE!"); 246 } 247 } 248 249 /// getQualifiedName - Return the name of the specified record, with a 250 /// namespace qualifier if the record contains one. 251 /// 252 std::string llvm::getQualifiedName(const Record *R) { 253 std::string Namespace; 254 if (R->getValue("Namespace")) 255 Namespace = std::string(R->getValueAsString("Namespace")); 256 if (Namespace.empty()) 257 return std::string(R->getName()); 258 return Namespace + "::" + R->getName().str(); 259 } 260 261 262 /// getTarget - Return the current instance of the Target class. 263 /// 264 CodeGenTarget::CodeGenTarget(RecordKeeper &records) 265 : Records(records), CGH(records) { 266 std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target"); 267 if (Targets.size() == 0) 268 PrintFatalError("No 'Target' subclasses defined!"); 269 if (Targets.size() != 1) 270 PrintFatalError("Multiple subclasses of Target defined!"); 271 TargetRec = Targets[0]; 272 } 273 274 CodeGenTarget::~CodeGenTarget() { 275 } 276 277 StringRef CodeGenTarget::getName() const { return TargetRec->getName(); } 278 279 /// getInstNamespace - Find and return the target machine's instruction 280 /// namespace. The namespace is cached because it is requested multiple times. 281 StringRef CodeGenTarget::getInstNamespace() const { 282 if (InstNamespace.empty()) { 283 for (const CodeGenInstruction *Inst : getInstructionsByEnumValue()) { 284 // We are not interested in the "TargetOpcode" namespace. 285 if (Inst->Namespace != "TargetOpcode") { 286 InstNamespace = Inst->Namespace; 287 break; 288 } 289 } 290 } 291 292 return InstNamespace; 293 } 294 295 StringRef CodeGenTarget::getRegNamespace() const { 296 auto &RegClasses = RegBank->getRegClasses(); 297 return RegClasses.size() > 0 ? RegClasses.front().Namespace : ""; 298 } 299 300 Record *CodeGenTarget::getInstructionSet() const { 301 return TargetRec->getValueAsDef("InstructionSet"); 302 } 303 304 bool CodeGenTarget::getAllowRegisterRenaming() const { 305 return TargetRec->getValueAsInt("AllowRegisterRenaming"); 306 } 307 308 /// getAsmParser - Return the AssemblyParser definition for this target. 309 /// 310 Record *CodeGenTarget::getAsmParser() const { 311 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers"); 312 if (AsmParserNum >= LI.size()) 313 PrintFatalError("Target does not have an AsmParser #" + 314 Twine(AsmParserNum) + "!"); 315 return LI[AsmParserNum]; 316 } 317 318 /// getAsmParserVariant - Return the AssemblyParserVariant definition for 319 /// this target. 320 /// 321 Record *CodeGenTarget::getAsmParserVariant(unsigned i) const { 322 std::vector<Record*> LI = 323 TargetRec->getValueAsListOfDefs("AssemblyParserVariants"); 324 if (i >= LI.size()) 325 PrintFatalError("Target does not have an AsmParserVariant #" + Twine(i) + 326 "!"); 327 return LI[i]; 328 } 329 330 /// getAsmParserVariantCount - Return the AssemblyParserVariant definition 331 /// available for this target. 332 /// 333 unsigned CodeGenTarget::getAsmParserVariantCount() const { 334 std::vector<Record*> LI = 335 TargetRec->getValueAsListOfDefs("AssemblyParserVariants"); 336 return LI.size(); 337 } 338 339 /// getAsmWriter - Return the AssemblyWriter definition for this target. 340 /// 341 Record *CodeGenTarget::getAsmWriter() const { 342 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters"); 343 if (AsmWriterNum >= LI.size()) 344 PrintFatalError("Target does not have an AsmWriter #" + 345 Twine(AsmWriterNum) + "!"); 346 return LI[AsmWriterNum]; 347 } 348 349 CodeGenRegBank &CodeGenTarget::getRegBank() const { 350 if (!RegBank) 351 RegBank = std::make_unique<CodeGenRegBank>(Records, getHwModes()); 352 return *RegBank; 353 } 354 355 Optional<CodeGenRegisterClass *> 356 CodeGenTarget::getSuperRegForSubReg(const ValueTypeByHwMode &ValueTy, 357 CodeGenRegBank &RegBank, 358 const CodeGenSubRegIndex *SubIdx, 359 bool MustBeAllocatable) const { 360 std::vector<CodeGenRegisterClass *> Candidates; 361 auto &RegClasses = RegBank.getRegClasses(); 362 363 // Try to find a register class which supports ValueTy, and also contains 364 // SubIdx. 365 for (CodeGenRegisterClass &RC : RegClasses) { 366 // Is there a subclass of this class which contains this subregister index? 367 CodeGenRegisterClass *SubClassWithSubReg = RC.getSubClassWithSubReg(SubIdx); 368 if (!SubClassWithSubReg) 369 continue; 370 371 // We have a class. Check if it supports this value type. 372 if (!llvm::is_contained(SubClassWithSubReg->VTs, ValueTy)) 373 continue; 374 375 // If necessary, check that it is allocatable. 376 if (MustBeAllocatable && !SubClassWithSubReg->Allocatable) 377 continue; 378 379 // We have a register class which supports both the value type and 380 // subregister index. Remember it. 381 Candidates.push_back(SubClassWithSubReg); 382 } 383 384 // If we didn't find anything, we're done. 385 if (Candidates.empty()) 386 return None; 387 388 // Find and return the largest of our candidate classes. 389 llvm::stable_sort(Candidates, [&](const CodeGenRegisterClass *A, 390 const CodeGenRegisterClass *B) { 391 if (A->getMembers().size() > B->getMembers().size()) 392 return true; 393 394 if (A->getMembers().size() < B->getMembers().size()) 395 return false; 396 397 // Order by name as a tie-breaker. 398 return StringRef(A->getName()) < B->getName(); 399 }); 400 401 return Candidates[0]; 402 } 403 404 void CodeGenTarget::ReadRegAltNameIndices() const { 405 RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex"); 406 llvm::sort(RegAltNameIndices, LessRecord()); 407 } 408 409 /// getRegisterByName - If there is a register with the specific AsmName, 410 /// return it. 411 const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const { 412 return getRegBank().getRegistersByName().lookup(Name); 413 } 414 415 std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R) 416 const { 417 const CodeGenRegister *Reg = getRegBank().getReg(R); 418 std::vector<ValueTypeByHwMode> Result; 419 for (const auto &RC : getRegBank().getRegClasses()) { 420 if (RC.contains(Reg)) { 421 ArrayRef<ValueTypeByHwMode> InVTs = RC.getValueTypes(); 422 llvm::append_range(Result, InVTs); 423 } 424 } 425 426 // Remove duplicates. 427 llvm::sort(Result); 428 Result.erase(std::unique(Result.begin(), Result.end()), Result.end()); 429 return Result; 430 } 431 432 433 void CodeGenTarget::ReadLegalValueTypes() const { 434 for (const auto &RC : getRegBank().getRegClasses()) 435 llvm::append_range(LegalValueTypes, RC.VTs); 436 437 // Remove duplicates. 438 llvm::sort(LegalValueTypes); 439 LegalValueTypes.erase(std::unique(LegalValueTypes.begin(), 440 LegalValueTypes.end()), 441 LegalValueTypes.end()); 442 } 443 444 CodeGenSchedModels &CodeGenTarget::getSchedModels() const { 445 if (!SchedModels) 446 SchedModels = std::make_unique<CodeGenSchedModels>(Records, *this); 447 return *SchedModels; 448 } 449 450 void CodeGenTarget::ReadInstructions() const { 451 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction"); 452 if (Insts.size() <= 2) 453 PrintFatalError("No 'Instruction' subclasses defined!"); 454 455 // Parse the instructions defined in the .td file. 456 for (unsigned i = 0, e = Insts.size(); i != e; ++i) 457 Instructions[Insts[i]] = std::make_unique<CodeGenInstruction>(Insts[i]); 458 } 459 460 static const CodeGenInstruction * 461 GetInstByName(const char *Name, 462 const DenseMap<const Record*, 463 std::unique_ptr<CodeGenInstruction>> &Insts, 464 RecordKeeper &Records) { 465 const Record *Rec = Records.getDef(Name); 466 467 const auto I = Insts.find(Rec); 468 if (!Rec || I == Insts.end()) 469 PrintFatalError(Twine("Could not find '") + Name + "' instruction!"); 470 return I->second.get(); 471 } 472 473 static const char *const FixedInstrs[] = { 474 #define HANDLE_TARGET_OPCODE(OPC) #OPC, 475 #include "llvm/Support/TargetOpcodes.def" 476 nullptr}; 477 478 unsigned CodeGenTarget::getNumFixedInstructions() { 479 return array_lengthof(FixedInstrs) - 1; 480 } 481 482 /// Return all of the instructions defined by the target, ordered by 483 /// their enum value. 484 void CodeGenTarget::ComputeInstrsByEnum() const { 485 const auto &Insts = getInstructions(); 486 for (const char *const *p = FixedInstrs; *p; ++p) { 487 const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records); 488 assert(Instr && "Missing target independent instruction"); 489 assert(Instr->Namespace == "TargetOpcode" && "Bad namespace"); 490 InstrsByEnum.push_back(Instr); 491 } 492 unsigned EndOfPredefines = InstrsByEnum.size(); 493 assert(EndOfPredefines == getNumFixedInstructions() && 494 "Missing generic opcode"); 495 496 for (const auto &I : Insts) { 497 const CodeGenInstruction *CGI = I.second.get(); 498 if (CGI->Namespace != "TargetOpcode") { 499 InstrsByEnum.push_back(CGI); 500 if (CGI->TheDef->getValueAsBit("isPseudo")) 501 ++NumPseudoInstructions; 502 } 503 } 504 505 assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr"); 506 507 // All of the instructions are now in random order based on the map iteration. 508 llvm::sort( 509 InstrsByEnum.begin() + EndOfPredefines, InstrsByEnum.end(), 510 [](const CodeGenInstruction *Rec1, const CodeGenInstruction *Rec2) { 511 const auto &D1 = *Rec1->TheDef; 512 const auto &D2 = *Rec2->TheDef; 513 return std::make_tuple(!D1.getValueAsBit("isPseudo"), D1.getName()) < 514 std::make_tuple(!D2.getValueAsBit("isPseudo"), D2.getName()); 515 }); 516 } 517 518 519 /// isLittleEndianEncoding - Return whether this target encodes its instruction 520 /// in little-endian format, i.e. bits laid out in the order [0..n] 521 /// 522 bool CodeGenTarget::isLittleEndianEncoding() const { 523 return getInstructionSet()->getValueAsBit("isLittleEndianEncoding"); 524 } 525 526 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit 527 /// encodings, reverse the bit order of all instructions. 528 void CodeGenTarget::reverseBitsForLittleEndianEncoding() { 529 if (!isLittleEndianEncoding()) 530 return; 531 532 std::vector<Record *> Insts = 533 Records.getAllDerivedDefinitions("InstructionEncoding"); 534 for (Record *R : Insts) { 535 if (R->getValueAsString("Namespace") == "TargetOpcode" || 536 R->getValueAsBit("isPseudo")) 537 continue; 538 539 BitsInit *BI = R->getValueAsBitsInit("Inst"); 540 541 unsigned numBits = BI->getNumBits(); 542 543 SmallVector<Init *, 16> NewBits(numBits); 544 545 for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) { 546 unsigned bitSwapIdx = numBits - bit - 1; 547 Init *OrigBit = BI->getBit(bit); 548 Init *BitSwap = BI->getBit(bitSwapIdx); 549 NewBits[bit] = BitSwap; 550 NewBits[bitSwapIdx] = OrigBit; 551 } 552 if (numBits % 2) { 553 unsigned middle = (numBits + 1) / 2; 554 NewBits[middle] = BI->getBit(middle); 555 } 556 557 BitsInit *NewBI = BitsInit::get(NewBits); 558 559 // Update the bits in reversed order so that emitInstrOpBits will get the 560 // correct endianness. 561 R->getValue("Inst")->setValue(NewBI); 562 } 563 } 564 565 /// guessInstructionProperties - Return true if it's OK to guess instruction 566 /// properties instead of raising an error. 567 /// 568 /// This is configurable as a temporary migration aid. It will eventually be 569 /// permanently false. 570 bool CodeGenTarget::guessInstructionProperties() const { 571 return getInstructionSet()->getValueAsBit("guessInstructionProperties"); 572 } 573 574 //===----------------------------------------------------------------------===// 575 // ComplexPattern implementation 576 // 577 ComplexPattern::ComplexPattern(Record *R) { 578 Ty = ::getValueType(R->getValueAsDef("Ty")); 579 NumOperands = R->getValueAsInt("NumOperands"); 580 SelectFunc = std::string(R->getValueAsString("SelectFunc")); 581 RootNodes = R->getValueAsListOfDefs("RootNodes"); 582 583 // FIXME: This is a hack to statically increase the priority of patterns which 584 // maps a sub-dag to a complex pattern. e.g. favors LEA over ADD. To get best 585 // possible pattern match we'll need to dynamically calculate the complexity 586 // of all patterns a dag can potentially map to. 587 int64_t RawComplexity = R->getValueAsInt("Complexity"); 588 if (RawComplexity == -1) 589 Complexity = NumOperands * 3; 590 else 591 Complexity = RawComplexity; 592 593 // FIXME: Why is this different from parseSDPatternOperatorProperties? 594 // Parse the properties. 595 Properties = 0; 596 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties"); 597 for (unsigned i = 0, e = PropList.size(); i != e; ++i) 598 if (PropList[i]->getName() == "SDNPHasChain") { 599 Properties |= 1 << SDNPHasChain; 600 } else if (PropList[i]->getName() == "SDNPOptInGlue") { 601 Properties |= 1 << SDNPOptInGlue; 602 } else if (PropList[i]->getName() == "SDNPMayStore") { 603 Properties |= 1 << SDNPMayStore; 604 } else if (PropList[i]->getName() == "SDNPMayLoad") { 605 Properties |= 1 << SDNPMayLoad; 606 } else if (PropList[i]->getName() == "SDNPSideEffect") { 607 Properties |= 1 << SDNPSideEffect; 608 } else if (PropList[i]->getName() == "SDNPMemOperand") { 609 Properties |= 1 << SDNPMemOperand; 610 } else if (PropList[i]->getName() == "SDNPVariadic") { 611 Properties |= 1 << SDNPVariadic; 612 } else if (PropList[i]->getName() == "SDNPWantRoot") { 613 Properties |= 1 << SDNPWantRoot; 614 } else if (PropList[i]->getName() == "SDNPWantParent") { 615 Properties |= 1 << SDNPWantParent; 616 } else { 617 PrintFatalError(R->getLoc(), "Unsupported SD Node property '" + 618 PropList[i]->getName() + 619 "' on ComplexPattern '" + R->getName() + 620 "'!"); 621 } 622 } 623 624 //===----------------------------------------------------------------------===// 625 // CodeGenIntrinsic Implementation 626 //===----------------------------------------------------------------------===// 627 628 CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC) { 629 std::vector<Record *> IntrProperties = 630 RC.getAllDerivedDefinitions("IntrinsicProperty"); 631 632 std::vector<Record *> DefaultProperties; 633 for (Record *Rec : IntrProperties) 634 if (Rec->getValueAsBit("IsDefault")) 635 DefaultProperties.push_back(Rec); 636 637 std::vector<Record *> Defs = RC.getAllDerivedDefinitions("Intrinsic"); 638 Intrinsics.reserve(Defs.size()); 639 640 for (unsigned I = 0, e = Defs.size(); I != e; ++I) 641 Intrinsics.push_back(CodeGenIntrinsic(Defs[I], DefaultProperties)); 642 643 llvm::sort(Intrinsics, 644 [](const CodeGenIntrinsic &LHS, const CodeGenIntrinsic &RHS) { 645 return std::tie(LHS.TargetPrefix, LHS.Name) < 646 std::tie(RHS.TargetPrefix, RHS.Name); 647 }); 648 Targets.push_back({"", 0, 0}); 649 for (size_t I = 0, E = Intrinsics.size(); I < E; ++I) 650 if (Intrinsics[I].TargetPrefix != Targets.back().Name) { 651 Targets.back().Count = I - Targets.back().Offset; 652 Targets.push_back({Intrinsics[I].TargetPrefix, I, 0}); 653 } 654 Targets.back().Count = Intrinsics.size() - Targets.back().Offset; 655 } 656 657 CodeGenIntrinsic::CodeGenIntrinsic(Record *R, 658 std::vector<Record *> DefaultProperties) { 659 TheDef = R; 660 std::string DefName = std::string(R->getName()); 661 ArrayRef<SMLoc> DefLoc = R->getLoc(); 662 ModRef = ReadWriteMem; 663 Properties = 0; 664 isOverloaded = false; 665 isCommutative = false; 666 canThrow = false; 667 isNoReturn = false; 668 isNoSync = false; 669 isNoFree = false; 670 isWillReturn = false; 671 isCold = false; 672 isNoDuplicate = false; 673 isNoMerge = false; 674 isConvergent = false; 675 isSpeculatable = false; 676 hasSideEffects = false; 677 678 if (DefName.size() <= 4 || 679 std::string(DefName.begin(), DefName.begin() + 4) != "int_") 680 PrintFatalError(DefLoc, 681 "Intrinsic '" + DefName + "' does not start with 'int_'!"); 682 683 EnumName = std::string(DefName.begin()+4, DefName.end()); 684 685 if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field. 686 GCCBuiltinName = std::string(R->getValueAsString("GCCBuiltinName")); 687 if (R->getValue("MSBuiltinName")) // Ignore a missing MSBuiltinName field. 688 MSBuiltinName = std::string(R->getValueAsString("MSBuiltinName")); 689 690 TargetPrefix = std::string(R->getValueAsString("TargetPrefix")); 691 Name = std::string(R->getValueAsString("LLVMName")); 692 693 if (Name == "") { 694 // If an explicit name isn't specified, derive one from the DefName. 695 Name = "llvm."; 696 697 for (unsigned i = 0, e = EnumName.size(); i != e; ++i) 698 Name += (EnumName[i] == '_') ? '.' : EnumName[i]; 699 } else { 700 // Verify it starts with "llvm.". 701 if (Name.size() <= 5 || 702 std::string(Name.begin(), Name.begin() + 5) != "llvm.") 703 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 704 "'s name does not start with 'llvm.'!"); 705 } 706 707 // If TargetPrefix is specified, make sure that Name starts with 708 // "llvm.<targetprefix>.". 709 if (!TargetPrefix.empty()) { 710 if (Name.size() < 6+TargetPrefix.size() || 711 std::string(Name.begin() + 5, Name.begin() + 6 + TargetPrefix.size()) 712 != (TargetPrefix + ".")) 713 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 714 "' does not start with 'llvm." + 715 TargetPrefix + ".'!"); 716 } 717 718 ListInit *RetTypes = R->getValueAsListInit("RetTypes"); 719 ListInit *ParamTypes = R->getValueAsListInit("ParamTypes"); 720 721 // First collate a list of overloaded types. 722 std::vector<MVT::SimpleValueType> OverloadedVTs; 723 for (ListInit *TypeList : {RetTypes, ParamTypes}) { 724 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 725 Record *TyEl = TypeList->getElementAsRecord(i); 726 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 727 728 if (TyEl->isSubClassOf("LLVMMatchType")) 729 continue; 730 731 MVT::SimpleValueType VT = getValueType(TyEl->getValueAsDef("VT")); 732 if (MVT(VT).isOverloaded()) { 733 OverloadedVTs.push_back(VT); 734 isOverloaded = true; 735 } 736 } 737 } 738 739 // Parse the list of return types. 740 ListInit *TypeList = RetTypes; 741 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 742 Record *TyEl = TypeList->getElementAsRecord(i); 743 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 744 MVT::SimpleValueType VT; 745 if (TyEl->isSubClassOf("LLVMMatchType")) { 746 unsigned MatchTy = TyEl->getValueAsInt("Number"); 747 assert(MatchTy < OverloadedVTs.size() && 748 "Invalid matching number!"); 749 VT = OverloadedVTs[MatchTy]; 750 // It only makes sense to use the extended and truncated vector element 751 // variants with iAny types; otherwise, if the intrinsic is not 752 // overloaded, all the types can be specified directly. 753 assert(((!TyEl->isSubClassOf("LLVMExtendedType") && 754 !TyEl->isSubClassOf("LLVMTruncatedType")) || 755 VT == MVT::iAny || VT == MVT::vAny) && 756 "Expected iAny or vAny type"); 757 } else { 758 VT = getValueType(TyEl->getValueAsDef("VT")); 759 } 760 761 // Reject invalid types. 762 if (VT == MVT::isVoid) 763 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 764 " has void in result type list!"); 765 766 IS.RetVTs.push_back(VT); 767 IS.RetTypeDefs.push_back(TyEl); 768 } 769 770 // Parse the list of parameter types. 771 TypeList = ParamTypes; 772 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 773 Record *TyEl = TypeList->getElementAsRecord(i); 774 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 775 MVT::SimpleValueType VT; 776 if (TyEl->isSubClassOf("LLVMMatchType")) { 777 unsigned MatchTy = TyEl->getValueAsInt("Number"); 778 if (MatchTy >= OverloadedVTs.size()) { 779 PrintError(R->getLoc(), 780 "Parameter #" + Twine(i) + " has out of bounds matching " 781 "number " + Twine(MatchTy)); 782 PrintFatalError(DefLoc, 783 Twine("ParamTypes is ") + TypeList->getAsString()); 784 } 785 VT = OverloadedVTs[MatchTy]; 786 // It only makes sense to use the extended and truncated vector element 787 // variants with iAny types; otherwise, if the intrinsic is not 788 // overloaded, all the types can be specified directly. 789 assert(((!TyEl->isSubClassOf("LLVMExtendedType") && 790 !TyEl->isSubClassOf("LLVMTruncatedType")) || 791 VT == MVT::iAny || VT == MVT::vAny) && 792 "Expected iAny or vAny type"); 793 } else 794 VT = getValueType(TyEl->getValueAsDef("VT")); 795 796 // Reject invalid types. 797 if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/) 798 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 799 " has void in result type list!"); 800 801 IS.ParamVTs.push_back(VT); 802 IS.ParamTypeDefs.push_back(TyEl); 803 } 804 805 // Parse the intrinsic properties. 806 ListInit *PropList = R->getValueAsListInit("IntrProperties"); 807 for (unsigned i = 0, e = PropList->size(); i != e; ++i) { 808 Record *Property = PropList->getElementAsRecord(i); 809 assert(Property->isSubClassOf("IntrinsicProperty") && 810 "Expected a property!"); 811 812 setProperty(Property); 813 } 814 815 // Set default properties to true. 816 setDefaultProperties(R, DefaultProperties); 817 818 // Also record the SDPatternOperator Properties. 819 Properties = parseSDPatternOperatorProperties(R); 820 821 // Sort the argument attributes for later benefit. 822 llvm::sort(ArgumentAttributes); 823 } 824 825 void CodeGenIntrinsic::setDefaultProperties( 826 Record *R, std::vector<Record *> DefaultProperties) { 827 // opt-out of using default attributes. 828 if (R->getValueAsBit("DisableDefaultAttributes")) 829 return; 830 831 for (Record *Rec : DefaultProperties) 832 setProperty(Rec); 833 } 834 835 void CodeGenIntrinsic::setProperty(Record *R) { 836 if (R->getName() == "IntrNoMem") 837 ModRef = NoMem; 838 else if (R->getName() == "IntrReadMem") { 839 if (!(ModRef & MR_Ref)) 840 PrintFatalError(TheDef->getLoc(), 841 Twine("IntrReadMem cannot be used after IntrNoMem or " 842 "IntrWriteMem. Default is ReadWrite")); 843 ModRef = ModRefBehavior(ModRef & ~MR_Mod); 844 } else if (R->getName() == "IntrWriteMem") { 845 if (!(ModRef & MR_Mod)) 846 PrintFatalError(TheDef->getLoc(), 847 Twine("IntrWriteMem cannot be used after IntrNoMem or " 848 "IntrReadMem. Default is ReadWrite")); 849 ModRef = ModRefBehavior(ModRef & ~MR_Ref); 850 } else if (R->getName() == "IntrArgMemOnly") 851 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem); 852 else if (R->getName() == "IntrInaccessibleMemOnly") 853 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_InaccessibleMem); 854 else if (R->getName() == "IntrInaccessibleMemOrArgMemOnly") 855 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem | 856 MR_InaccessibleMem); 857 else if (R->getName() == "Commutative") 858 isCommutative = true; 859 else if (R->getName() == "Throws") 860 canThrow = true; 861 else if (R->getName() == "IntrNoDuplicate") 862 isNoDuplicate = true; 863 else if (R->getName() == "IntrNoMerge") 864 isNoMerge = true; 865 else if (R->getName() == "IntrConvergent") 866 isConvergent = true; 867 else if (R->getName() == "IntrNoReturn") 868 isNoReturn = true; 869 else if (R->getName() == "IntrNoSync") 870 isNoSync = true; 871 else if (R->getName() == "IntrNoFree") 872 isNoFree = true; 873 else if (R->getName() == "IntrWillReturn") 874 isWillReturn = !isNoReturn; 875 else if (R->getName() == "IntrCold") 876 isCold = true; 877 else if (R->getName() == "IntrSpeculatable") 878 isSpeculatable = true; 879 else if (R->getName() == "IntrHasSideEffects") 880 hasSideEffects = true; 881 else if (R->isSubClassOf("NoCapture")) { 882 unsigned ArgNo = R->getValueAsInt("ArgNo"); 883 ArgumentAttributes.emplace_back(ArgNo, NoCapture, 0); 884 } else if (R->isSubClassOf("NoAlias")) { 885 unsigned ArgNo = R->getValueAsInt("ArgNo"); 886 ArgumentAttributes.emplace_back(ArgNo, NoAlias, 0); 887 } else if (R->isSubClassOf("NoUndef")) { 888 unsigned ArgNo = R->getValueAsInt("ArgNo"); 889 ArgumentAttributes.emplace_back(ArgNo, NoUndef, 0); 890 } else if (R->isSubClassOf("Returned")) { 891 unsigned ArgNo = R->getValueAsInt("ArgNo"); 892 ArgumentAttributes.emplace_back(ArgNo, Returned, 0); 893 } else if (R->isSubClassOf("ReadOnly")) { 894 unsigned ArgNo = R->getValueAsInt("ArgNo"); 895 ArgumentAttributes.emplace_back(ArgNo, ReadOnly, 0); 896 } else if (R->isSubClassOf("WriteOnly")) { 897 unsigned ArgNo = R->getValueAsInt("ArgNo"); 898 ArgumentAttributes.emplace_back(ArgNo, WriteOnly, 0); 899 } else if (R->isSubClassOf("ReadNone")) { 900 unsigned ArgNo = R->getValueAsInt("ArgNo"); 901 ArgumentAttributes.emplace_back(ArgNo, ReadNone, 0); 902 } else if (R->isSubClassOf("ImmArg")) { 903 unsigned ArgNo = R->getValueAsInt("ArgNo"); 904 ArgumentAttributes.emplace_back(ArgNo, ImmArg, 0); 905 } else if (R->isSubClassOf("Align")) { 906 unsigned ArgNo = R->getValueAsInt("ArgNo"); 907 uint64_t Align = R->getValueAsInt("Align"); 908 ArgumentAttributes.emplace_back(ArgNo, Alignment, Align); 909 } else 910 llvm_unreachable("Unknown property!"); 911 } 912 913 bool CodeGenIntrinsic::isParamAPointer(unsigned ParamIdx) const { 914 if (ParamIdx >= IS.ParamVTs.size()) 915 return false; 916 MVT ParamType = MVT(IS.ParamVTs[ParamIdx]); 917 return ParamType == MVT::iPTR || ParamType == MVT::iPTRAny; 918 } 919 920 bool CodeGenIntrinsic::isParamImmArg(unsigned ParamIdx) const { 921 // Convert argument index to attribute index starting from `FirstArgIndex`. 922 ArgAttribute Val{ParamIdx + 1, ImmArg, 0}; 923 return std::binary_search(ArgumentAttributes.begin(), 924 ArgumentAttributes.end(), Val); 925 } 926