1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper ---------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This class wrap target description classes used by the various code
11 // generation TableGen backends.  This makes it easier to access the data and
12 // provides a single place that needs to check it for validity.  All of these
13 // classes throw exceptions on error conditions.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "CodeGenTarget.h"
18 #include "Record.h"
19 #include "llvm/ADT/StringExtras.h"
20 #include "llvm/Support/CommandLine.h"
21 #include <set>
22 #include <algorithm>
23 using namespace llvm;
24 
25 static cl::opt<unsigned>
26 AsmWriterNum("asmwriternum", cl::init(0),
27              cl::desc("Make -gen-asm-writer emit assembly writer #N"));
28 
29 /// getValueType - Return the MCV::ValueType that the specified TableGen record
30 /// corresponds to.
31 MVT::ValueType llvm::getValueType(Record *Rec) {
32   return (MVT::ValueType)Rec->getValueAsInt("Value");
33 }
34 
35 std::string llvm::getName(MVT::ValueType T) {
36   switch (T) {
37   case MVT::Other: return "UNKNOWN";
38   case MVT::i1:    return "i1";
39   case MVT::i8:    return "i8";
40   case MVT::i16:   return "i16";
41   case MVT::i32:   return "i32";
42   case MVT::i64:   return "i64";
43   case MVT::i128:  return "i128";
44   case MVT::f32:   return "f32";
45   case MVT::f64:   return "f64";
46   case MVT::f80:   return "f80";
47   case MVT::f128:  return "f128";
48   case MVT::Flag:  return "Flag";
49   case MVT::isVoid:return "void";
50   case MVT::v8i8:  return "v8i8";
51   case MVT::v4i16: return "v4i16";
52   case MVT::v2i32: return "v2i32";
53   case MVT::v16i8: return "v16i8";
54   case MVT::v8i16: return "v8i16";
55   case MVT::v4i32: return "v4i32";
56   case MVT::v2i64: return "v2i64";
57   case MVT::v4f32: return "v4f32";
58   case MVT::v2f64: return "v2f64";
59   default: assert(0 && "ILLEGAL VALUE TYPE!"); return "";
60   }
61 }
62 
63 std::string llvm::getEnumName(MVT::ValueType T) {
64   switch (T) {
65   case MVT::Other: return "Other";
66   case MVT::i1:    return "i1";
67   case MVT::i8:    return "i8";
68   case MVT::i16:   return "i16";
69   case MVT::i32:   return "i32";
70   case MVT::i64:   return "i64";
71   case MVT::i128:  return "i128";
72   case MVT::f32:   return "f32";
73   case MVT::f64:   return "f64";
74   case MVT::f80:   return "f80";
75   case MVT::f128:  return "f128";
76   case MVT::Flag:  return "Flag";
77   case MVT::isVoid:return "isVoid";
78   case MVT::v16i8: return "v16i8";
79   case MVT::v8i16: return "v8i16";
80   case MVT::v4i32: return "v4i32";
81   case MVT::v2i64: return "v2i64";
82   case MVT::v4f32: return "v4f32";
83   case MVT::v2f64: return "v2f64";
84   default: assert(0 && "ILLEGAL VALUE TYPE!"); return "";
85   }
86 }
87 
88 
89 std::ostream &llvm::operator<<(std::ostream &OS, MVT::ValueType T) {
90   return OS << getName(T);
91 }
92 
93 
94 /// getTarget - Return the current instance of the Target class.
95 ///
96 CodeGenTarget::CodeGenTarget() : PointerType(MVT::Other) {
97   std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
98   if (Targets.size() == 0)
99     throw std::string("ERROR: No 'Target' subclasses defined!");
100   if (Targets.size() != 1)
101     throw std::string("ERROR: Multiple subclasses of Target defined!");
102   TargetRec = Targets[0];
103 
104   // Read in all of the CalleeSavedRegisters.
105   CalleeSavedRegisters =TargetRec->getValueAsListOfDefs("CalleeSavedRegisters");
106   PointerType = getValueType(TargetRec->getValueAsDef("PointerType"));
107 }
108 
109 
110 const std::string &CodeGenTarget::getName() const {
111   return TargetRec->getName();
112 }
113 
114 Record *CodeGenTarget::getInstructionSet() const {
115   return TargetRec->getValueAsDef("InstructionSet");
116 }
117 
118 /// getAsmWriter - Return the AssemblyWriter definition for this target.
119 ///
120 Record *CodeGenTarget::getAsmWriter() const {
121   std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters");
122   if (AsmWriterNum >= LI.size())
123     throw "Target does not have an AsmWriter #" + utostr(AsmWriterNum) + "!";
124   return LI[AsmWriterNum];
125 }
126 
127 void CodeGenTarget::ReadRegisters() const {
128   std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
129   if (Regs.empty())
130     throw std::string("No 'Register' subclasses defined!");
131 
132   Registers.reserve(Regs.size());
133   Registers.assign(Regs.begin(), Regs.end());
134 }
135 
136 CodeGenRegister::CodeGenRegister(Record *R) : TheDef(R) {
137   DeclaredSpillSize = R->getValueAsInt("SpillSize");
138   DeclaredSpillAlignment = R->getValueAsInt("SpillAlignment");
139 }
140 
141 const std::string &CodeGenRegister::getName() const {
142   return TheDef->getName();
143 }
144 
145 void CodeGenTarget::ReadRegisterClasses() const {
146   std::vector<Record*> RegClasses =
147     Records.getAllDerivedDefinitions("RegisterClass");
148   if (RegClasses.empty())
149     throw std::string("No 'RegisterClass' subclasses defined!");
150 
151   RegisterClasses.reserve(RegClasses.size());
152   RegisterClasses.assign(RegClasses.begin(), RegClasses.end());
153 }
154 
155 CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) {
156   // Rename anonymous register classes.
157   if (R->getName().size() > 9 && R->getName()[9] == '.') {
158     static unsigned AnonCounter = 0;
159     R->setName("AnonRegClass_"+utostr(AnonCounter++));
160   }
161 
162   std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
163   for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
164     Record *Type = TypeList[i];
165     if (!Type->isSubClassOf("ValueType"))
166       throw "RegTypes list member '" + Type->getName() +
167         "' does not derive from the ValueType class!";
168     VTs.push_back(getValueType(Type));
169   }
170   assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
171 
172   std::vector<Record*> RegList = R->getValueAsListOfDefs("MemberList");
173   for (unsigned i = 0, e = RegList.size(); i != e; ++i) {
174     Record *Reg = RegList[i];
175     if (!Reg->isSubClassOf("Register"))
176       throw "Register Class member '" + Reg->getName() +
177             "' does not derive from the Register class!";
178     Elements.push_back(Reg);
179   }
180 
181   // Allow targets to override the size in bits of the RegisterClass.
182   unsigned Size = R->getValueAsInt("Size");
183 
184   Namespace = R->getValueAsString("Namespace");
185   SpillSize = Size ? Size : MVT::getSizeInBits(VTs[0]);
186   SpillAlignment = R->getValueAsInt("Alignment");
187   MethodBodies = R->getValueAsCode("MethodBodies");
188   MethodProtos = R->getValueAsCode("MethodProtos");
189 }
190 
191 const std::string &CodeGenRegisterClass::getName() const {
192   return TheDef->getName();
193 }
194 
195 void CodeGenTarget::ReadLegalValueTypes() const {
196   const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
197   for (unsigned i = 0, e = RCs.size(); i != e; ++i)
198     for (unsigned ri = 0, re = RCs[i].VTs.size(); ri != re; ++ri)
199       LegalValueTypes.push_back(RCs[i].VTs[ri]);
200 
201   // Remove duplicates.
202   std::sort(LegalValueTypes.begin(), LegalValueTypes.end());
203   LegalValueTypes.erase(std::unique(LegalValueTypes.begin(),
204                                     LegalValueTypes.end()),
205                         LegalValueTypes.end());
206 }
207 
208 
209 void CodeGenTarget::ReadInstructions() const {
210   std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
211   if (Insts.size() <= 2)
212     throw std::string("No 'Instruction' subclasses defined!");
213 
214   // Parse the instructions defined in the .td file.
215   std::string InstFormatName =
216     getAsmWriter()->getValueAsString("InstFormatName");
217 
218   for (unsigned i = 0, e = Insts.size(); i != e; ++i) {
219     std::string AsmStr = Insts[i]->getValueAsString(InstFormatName);
220     Instructions.insert(std::make_pair(Insts[i]->getName(),
221                                        CodeGenInstruction(Insts[i], AsmStr)));
222   }
223 }
224 
225 /// getInstructionsByEnumValue - Return all of the instructions defined by the
226 /// target, ordered by their enum value.
227 void CodeGenTarget::
228 getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
229                                                  &NumberedInstructions) {
230   std::map<std::string, CodeGenInstruction>::const_iterator I;
231   I = getInstructions().find("PHI");
232   if (I == Instructions.end()) throw "Could not find 'PHI' instruction!";
233   const CodeGenInstruction *PHI = &I->second;
234 
235   I = getInstructions().find("INLINEASM");
236   if (I == Instructions.end()) throw "Could not find 'INLINEASM' instruction!";
237   const CodeGenInstruction *INLINEASM = &I->second;
238 
239   // Print out the rest of the instructions now.
240   NumberedInstructions.push_back(PHI);
241   NumberedInstructions.push_back(INLINEASM);
242   for (inst_iterator II = inst_begin(), E = inst_end(); II != E; ++II)
243     if (&II->second != PHI &&&II->second != INLINEASM)
244       NumberedInstructions.push_back(&II->second);
245 }
246 
247 
248 /// isLittleEndianEncoding - Return whether this target encodes its instruction
249 /// in little-endian format, i.e. bits laid out in the order [0..n]
250 ///
251 bool CodeGenTarget::isLittleEndianEncoding() const {
252   return getInstructionSet()->getValueAsBit("isLittleEndianEncoding");
253 }
254 
255 CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
256   : TheDef(R), AsmString(AsmStr) {
257   Name      = R->getValueAsString("Name");
258   Namespace = R->getValueAsString("Namespace");
259 
260   isReturn     = R->getValueAsBit("isReturn");
261   isBranch     = R->getValueAsBit("isBranch");
262   isBarrier    = R->getValueAsBit("isBarrier");
263   isCall       = R->getValueAsBit("isCall");
264   isLoad       = R->getValueAsBit("isLoad");
265   isStore      = R->getValueAsBit("isStore");
266   isTwoAddress = R->getValueAsBit("isTwoAddress");
267   isConvertibleToThreeAddress = R->getValueAsBit("isConvertibleToThreeAddress");
268   isCommutable = R->getValueAsBit("isCommutable");
269   isTerminator = R->getValueAsBit("isTerminator");
270   hasDelaySlot = R->getValueAsBit("hasDelaySlot");
271   usesCustomDAGSchedInserter = R->getValueAsBit("usesCustomDAGSchedInserter");
272   hasCtrlDep   = R->getValueAsBit("hasCtrlDep");
273   noResults    = R->getValueAsBit("noResults");
274   hasVariableNumberOfOperands = false;
275 
276   DagInit *DI;
277   try {
278     DI = R->getValueAsDag("OperandList");
279   } catch (...) {
280     // Error getting operand list, just ignore it (sparcv9).
281     AsmString.clear();
282     OperandList.clear();
283     return;
284   }
285 
286   unsigned MIOperandNo = 0;
287   std::set<std::string> OperandNames;
288   for (unsigned i = 0, e = DI->getNumArgs(); i != e; ++i) {
289     DefInit *Arg = dynamic_cast<DefInit*>(DI->getArg(i));
290     if (!Arg)
291       throw "Illegal operand for the '" + R->getName() + "' instruction!";
292 
293     Record *Rec = Arg->getDef();
294     std::string PrintMethod = "printOperand";
295     unsigned NumOps = 1;
296     DagInit *MIOpInfo = 0;
297     if (Rec->isSubClassOf("Operand")) {
298       PrintMethod = Rec->getValueAsString("PrintMethod");
299       NumOps = Rec->getValueAsInt("NumMIOperands");
300       MIOpInfo = Rec->getValueAsDag("MIOperandInfo");
301     } else if (Rec->getName() == "variable_ops") {
302       hasVariableNumberOfOperands = true;
303       continue;
304     } else if (!Rec->isSubClassOf("RegisterClass"))
305       throw "Unknown operand class '" + Rec->getName() +
306             "' in instruction '" + R->getName() + "' instruction!";
307 
308     // Check that the operand has a name and that it's unique.
309     if (DI->getArgName(i).empty())
310       throw "In instruction '" + R->getName() + "', operand #" + utostr(i) +
311         " has no name!";
312     if (!OperandNames.insert(DI->getArgName(i)).second)
313       throw "In instruction '" + R->getName() + "', operand #" + utostr(i) +
314         " has the same name as a previous operand!";
315 
316     OperandList.push_back(OperandInfo(Rec, DI->getArgName(i), PrintMethod,
317                                       MIOperandNo, NumOps, MIOpInfo));
318     MIOperandNo += NumOps;
319   }
320 }
321 
322 
323 
324 /// getOperandNamed - Return the index of the operand with the specified
325 /// non-empty name.  If the instruction does not have an operand with the
326 /// specified name, throw an exception.
327 ///
328 unsigned CodeGenInstruction::getOperandNamed(const std::string &Name) const {
329   assert(!Name.empty() && "Cannot search for operand with no name!");
330   for (unsigned i = 0, e = OperandList.size(); i != e; ++i)
331     if (OperandList[i].Name == Name) return i;
332   throw "Instruction '" + TheDef->getName() +
333         "' does not have an operand named '$" + Name + "'!";
334 }
335 
336 //===----------------------------------------------------------------------===//
337 // ComplexPattern implementation
338 //
339 ComplexPattern::ComplexPattern(Record *R) {
340   Ty          = ::getValueType(R->getValueAsDef("Ty"));
341   NumOperands = R->getValueAsInt("NumOperands");
342   SelectFunc  = R->getValueAsString("SelectFunc");
343   RootNodes   = R->getValueAsListOfDefs("RootNodes");
344 }
345 
346