1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class wraps target description classes used by the various code
10 // generation TableGen backends.  This makes it easier to access the data and
11 // provides a single place that needs to check it for validity.  All of these
12 // classes abort on error conditions.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "CodeGenTarget.h"
17 #include "CodeGenDAGPatterns.h"
18 #include "CodeGenIntrinsics.h"
19 #include "CodeGenSchedule.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/Timer.h"
24 #include "llvm/TableGen/Error.h"
25 #include "llvm/TableGen/Record.h"
26 #include "llvm/TableGen/TableGenBackend.h"
27 #include <algorithm>
28 using namespace llvm;
29 
30 cl::OptionCategory AsmParserCat("Options for -gen-asm-parser");
31 cl::OptionCategory AsmWriterCat("Options for -gen-asm-writer");
32 
33 static cl::opt<unsigned>
34     AsmParserNum("asmparsernum", cl::init(0),
35                  cl::desc("Make -gen-asm-parser emit assembly parser #N"),
36                  cl::cat(AsmParserCat));
37 
38 static cl::opt<unsigned>
39     AsmWriterNum("asmwriternum", cl::init(0),
40                  cl::desc("Make -gen-asm-writer emit assembly writer #N"),
41                  cl::cat(AsmWriterCat));
42 
43 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
44 /// record corresponds to.
45 MVT::SimpleValueType llvm::getValueType(Record *Rec) {
46   return (MVT::SimpleValueType)Rec->getValueAsInt("Value");
47 }
48 
49 StringRef llvm::getName(MVT::SimpleValueType T) {
50   switch (T) {
51   case MVT::Other:   return "UNKNOWN";
52   case MVT::iPTR:    return "TLI.getPointerTy()";
53   case MVT::iPTRAny: return "TLI.getPointerTy()";
54   default: return getEnumName(T);
55   }
56 }
57 
58 StringRef llvm::getEnumName(MVT::SimpleValueType T) {
59   switch (T) {
60   case MVT::Other:    return "MVT::Other";
61   case MVT::i1:       return "MVT::i1";
62   case MVT::i8:       return "MVT::i8";
63   case MVT::i16:      return "MVT::i16";
64   case MVT::i32:      return "MVT::i32";
65   case MVT::i64:      return "MVT::i64";
66   case MVT::i128:     return "MVT::i128";
67   case MVT::Any:      return "MVT::Any";
68   case MVT::iAny:     return "MVT::iAny";
69   case MVT::fAny:     return "MVT::fAny";
70   case MVT::vAny:     return "MVT::vAny";
71   case MVT::f16:      return "MVT::f16";
72   case MVT::f32:      return "MVT::f32";
73   case MVT::f64:      return "MVT::f64";
74   case MVT::f80:      return "MVT::f80";
75   case MVT::f128:     return "MVT::f128";
76   case MVT::ppcf128:  return "MVT::ppcf128";
77   case MVT::x86mmx:   return "MVT::x86mmx";
78   case MVT::Glue:     return "MVT::Glue";
79   case MVT::isVoid:   return "MVT::isVoid";
80   case MVT::v1i1:     return "MVT::v1i1";
81   case MVT::v2i1:     return "MVT::v2i1";
82   case MVT::v4i1:     return "MVT::v4i1";
83   case MVT::v8i1:     return "MVT::v8i1";
84   case MVT::v16i1:    return "MVT::v16i1";
85   case MVT::v32i1:    return "MVT::v32i1";
86   case MVT::v64i1:    return "MVT::v64i1";
87   case MVT::v128i1:   return "MVT::v128i1";
88   case MVT::v512i1:   return "MVT::v512i1";
89   case MVT::v1024i1:  return "MVT::v1024i1";
90   case MVT::v1i8:     return "MVT::v1i8";
91   case MVT::v2i8:     return "MVT::v2i8";
92   case MVT::v4i8:     return "MVT::v4i8";
93   case MVT::v8i8:     return "MVT::v8i8";
94   case MVT::v16i8:    return "MVT::v16i8";
95   case MVT::v32i8:    return "MVT::v32i8";
96   case MVT::v64i8:    return "MVT::v64i8";
97   case MVT::v128i8:   return "MVT::v128i8";
98   case MVT::v256i8:   return "MVT::v256i8";
99   case MVT::v1i16:    return "MVT::v1i16";
100   case MVT::v2i16:    return "MVT::v2i16";
101   case MVT::v3i16:    return "MVT::v3i16";
102   case MVT::v4i16:    return "MVT::v4i16";
103   case MVT::v8i16:    return "MVT::v8i16";
104   case MVT::v16i16:   return "MVT::v16i16";
105   case MVT::v32i16:   return "MVT::v32i16";
106   case MVT::v64i16:   return "MVT::v64i16";
107   case MVT::v128i16:  return "MVT::v128i16";
108   case MVT::v1i32:    return "MVT::v1i32";
109   case MVT::v2i32:    return "MVT::v2i32";
110   case MVT::v3i32:    return "MVT::v3i32";
111   case MVT::v4i32:    return "MVT::v4i32";
112   case MVT::v5i32:    return "MVT::v5i32";
113   case MVT::v8i32:    return "MVT::v8i32";
114   case MVT::v16i32:   return "MVT::v16i32";
115   case MVT::v32i32:   return "MVT::v32i32";
116   case MVT::v64i32:   return "MVT::v64i32";
117   case MVT::v128i32:  return "MVT::v128i32";
118   case MVT::v256i32:  return "MVT::v256i32";
119   case MVT::v512i32:  return "MVT::v512i32";
120   case MVT::v1024i32: return "MVT::v1024i32";
121   case MVT::v2048i32: return "MVT::v2048i32";
122   case MVT::v1i64:    return "MVT::v1i64";
123   case MVT::v2i64:    return "MVT::v2i64";
124   case MVT::v4i64:    return "MVT::v4i64";
125   case MVT::v8i64:    return "MVT::v8i64";
126   case MVT::v16i64:   return "MVT::v16i64";
127   case MVT::v32i64:   return "MVT::v32i64";
128   case MVT::v1i128:   return "MVT::v1i128";
129   case MVT::v2f16:    return "MVT::v2f16";
130   case MVT::v3f16:    return "MVT::v3f16";
131   case MVT::v4f16:    return "MVT::v4f16";
132   case MVT::v8f16:    return "MVT::v8f16";
133   case MVT::v16f16:   return "MVT::v16f16";
134   case MVT::v32f16:   return "MVT::v32f16";
135   case MVT::v1f32:    return "MVT::v1f32";
136   case MVT::v2f32:    return "MVT::v2f32";
137   case MVT::v3f32:    return "MVT::v3f32";
138   case MVT::v4f32:    return "MVT::v4f32";
139   case MVT::v5f32:    return "MVT::v5f32";
140   case MVT::v8f32:    return "MVT::v8f32";
141   case MVT::v16f32:   return "MVT::v16f32";
142   case MVT::v32f32:   return "MVT::v32f32";
143   case MVT::v64f32:   return "MVT::v64f32";
144   case MVT::v128f32:  return "MVT::v128f32";
145   case MVT::v256f32:  return "MVT::v256f32";
146   case MVT::v512f32:  return "MVT::v512f32";
147   case MVT::v1024f32: return "MVT::v1024f32";
148   case MVT::v2048f32: return "MVT::v2048f32";
149   case MVT::v1f64:    return "MVT::v1f64";
150   case MVT::v2f64:    return "MVT::v2f64";
151   case MVT::v4f64:    return "MVT::v4f64";
152   case MVT::v8f64:    return "MVT::v8f64";
153   case MVT::nxv1i1:   return "MVT::nxv1i1";
154   case MVT::nxv2i1:   return "MVT::nxv2i1";
155   case MVT::nxv4i1:   return "MVT::nxv4i1";
156   case MVT::nxv8i1:   return "MVT::nxv8i1";
157   case MVT::nxv16i1:  return "MVT::nxv16i1";
158   case MVT::nxv32i1:  return "MVT::nxv32i1";
159   case MVT::nxv1i8:   return "MVT::nxv1i8";
160   case MVT::nxv2i8:   return "MVT::nxv2i8";
161   case MVT::nxv4i8:   return "MVT::nxv4i8";
162   case MVT::nxv8i8:   return "MVT::nxv8i8";
163   case MVT::nxv16i8:  return "MVT::nxv16i8";
164   case MVT::nxv32i8:  return "MVT::nxv32i8";
165   case MVT::nxv1i16:  return "MVT::nxv1i16";
166   case MVT::nxv2i16:  return "MVT::nxv2i16";
167   case MVT::nxv4i16:  return "MVT::nxv4i16";
168   case MVT::nxv8i16:  return "MVT::nxv8i16";
169   case MVT::nxv16i16: return "MVT::nxv16i16";
170   case MVT::nxv32i16: return "MVT::nxv32i16";
171   case MVT::nxv1i32:  return "MVT::nxv1i32";
172   case MVT::nxv2i32:  return "MVT::nxv2i32";
173   case MVT::nxv4i32:  return "MVT::nxv4i32";
174   case MVT::nxv8i32:  return "MVT::nxv8i32";
175   case MVT::nxv16i32: return "MVT::nxv16i32";
176   case MVT::nxv1i64:  return "MVT::nxv1i64";
177   case MVT::nxv2i64:  return "MVT::nxv2i64";
178   case MVT::nxv4i64:  return "MVT::nxv4i64";
179   case MVT::nxv8i64:  return "MVT::nxv8i64";
180   case MVT::nxv16i64: return "MVT::nxv16i64";
181   case MVT::nxv2f16:  return "MVT::nxv2f16";
182   case MVT::nxv4f16:  return "MVT::nxv4f16";
183   case MVT::nxv8f16:  return "MVT::nxv8f16";
184   case MVT::nxv1f32:  return "MVT::nxv1f32";
185   case MVT::nxv2f32:  return "MVT::nxv2f32";
186   case MVT::nxv4f32:  return "MVT::nxv4f32";
187   case MVT::nxv8f32:  return "MVT::nxv8f32";
188   case MVT::nxv16f32: return "MVT::nxv16f32";
189   case MVT::nxv1f64:  return "MVT::nxv1f64";
190   case MVT::nxv2f64:  return "MVT::nxv2f64";
191   case MVT::nxv4f64:  return "MVT::nxv4f64";
192   case MVT::nxv8f64:  return "MVT::nxv8f64";
193   case MVT::token:    return "MVT::token";
194   case MVT::Metadata: return "MVT::Metadata";
195   case MVT::iPTR:     return "MVT::iPTR";
196   case MVT::iPTRAny:  return "MVT::iPTRAny";
197   case MVT::Untyped:  return "MVT::Untyped";
198   case MVT::exnref:   return "MVT::exnref";
199   default: llvm_unreachable("ILLEGAL VALUE TYPE!");
200   }
201 }
202 
203 /// getQualifiedName - Return the name of the specified record, with a
204 /// namespace qualifier if the record contains one.
205 ///
206 std::string llvm::getQualifiedName(const Record *R) {
207   std::string Namespace;
208   if (R->getValue("Namespace"))
209      Namespace = R->getValueAsString("Namespace");
210   if (Namespace.empty()) return R->getName();
211   return Namespace + "::" + R->getName().str();
212 }
213 
214 
215 /// getTarget - Return the current instance of the Target class.
216 ///
217 CodeGenTarget::CodeGenTarget(RecordKeeper &records)
218   : Records(records), CGH(records) {
219   std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
220   if (Targets.size() == 0)
221     PrintFatalError("ERROR: No 'Target' subclasses defined!");
222   if (Targets.size() != 1)
223     PrintFatalError("ERROR: Multiple subclasses of Target defined!");
224   TargetRec = Targets[0];
225 }
226 
227 CodeGenTarget::~CodeGenTarget() {
228 }
229 
230 const StringRef CodeGenTarget::getName() const {
231   return TargetRec->getName();
232 }
233 
234 StringRef CodeGenTarget::getInstNamespace() const {
235   for (const CodeGenInstruction *Inst : getInstructionsByEnumValue()) {
236     // Make sure not to pick up "TargetOpcode" by accidentally getting
237     // the namespace off the PHI instruction or something.
238     if (Inst->Namespace != "TargetOpcode")
239       return Inst->Namespace;
240   }
241 
242   return "";
243 }
244 
245 Record *CodeGenTarget::getInstructionSet() const {
246   return TargetRec->getValueAsDef("InstructionSet");
247 }
248 
249 bool CodeGenTarget::getAllowRegisterRenaming() const {
250   return TargetRec->getValueAsInt("AllowRegisterRenaming");
251 }
252 
253 /// getAsmParser - Return the AssemblyParser definition for this target.
254 ///
255 Record *CodeGenTarget::getAsmParser() const {
256   std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers");
257   if (AsmParserNum >= LI.size())
258     PrintFatalError("Target does not have an AsmParser #" +
259                     Twine(AsmParserNum) + "!");
260   return LI[AsmParserNum];
261 }
262 
263 /// getAsmParserVariant - Return the AssmblyParserVariant definition for
264 /// this target.
265 ///
266 Record *CodeGenTarget::getAsmParserVariant(unsigned i) const {
267   std::vector<Record*> LI =
268     TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
269   if (i >= LI.size())
270     PrintFatalError("Target does not have an AsmParserVariant #" + Twine(i) +
271                     "!");
272   return LI[i];
273 }
274 
275 /// getAsmParserVariantCount - Return the AssmblyParserVariant definition
276 /// available for this target.
277 ///
278 unsigned CodeGenTarget::getAsmParserVariantCount() const {
279   std::vector<Record*> LI =
280     TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
281   return LI.size();
282 }
283 
284 /// getAsmWriter - Return the AssemblyWriter definition for this target.
285 ///
286 Record *CodeGenTarget::getAsmWriter() const {
287   std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters");
288   if (AsmWriterNum >= LI.size())
289     PrintFatalError("Target does not have an AsmWriter #" +
290                     Twine(AsmWriterNum) + "!");
291   return LI[AsmWriterNum];
292 }
293 
294 CodeGenRegBank &CodeGenTarget::getRegBank() const {
295   if (!RegBank)
296     RegBank = std::make_unique<CodeGenRegBank>(Records, getHwModes());
297   return *RegBank;
298 }
299 
300 Optional<CodeGenRegisterClass *>
301 CodeGenTarget::getSuperRegForSubReg(const ValueTypeByHwMode &ValueTy,
302                                     CodeGenRegBank &RegBank,
303                                     const CodeGenSubRegIndex *SubIdx) const {
304   std::vector<CodeGenRegisterClass *> Candidates;
305   auto &RegClasses = RegBank.getRegClasses();
306 
307   // Try to find a register class which supports ValueTy, and also contains
308   // SubIdx.
309   for (CodeGenRegisterClass &RC : RegClasses) {
310     // Is there a subclass of this class which contains this subregister index?
311     CodeGenRegisterClass *SubClassWithSubReg = RC.getSubClassWithSubReg(SubIdx);
312     if (!SubClassWithSubReg)
313       continue;
314 
315     // We have a class. Check if it supports this value type.
316     if (llvm::none_of(SubClassWithSubReg->VTs,
317                       [&ValueTy](const ValueTypeByHwMode &ClassVT) {
318                         return ClassVT == ValueTy;
319                       }))
320       continue;
321 
322     // We have a register class which supports both the value type and
323     // subregister index. Remember it.
324     Candidates.push_back(SubClassWithSubReg);
325   }
326 
327   // If we didn't find anything, we're done.
328   if (Candidates.empty())
329     return None;
330 
331   // Find and return the largest of our candidate classes.
332   llvm::stable_sort(Candidates, [&](const CodeGenRegisterClass *A,
333                                     const CodeGenRegisterClass *B) {
334     if (A->getMembers().size() > B->getMembers().size())
335       return true;
336 
337     if (A->getMembers().size() < B->getMembers().size())
338       return false;
339 
340     // Order by name as a tie-breaker.
341     return StringRef(A->getName()) < B->getName();
342   });
343 
344   return Candidates[0];
345 }
346 
347 void CodeGenTarget::ReadRegAltNameIndices() const {
348   RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex");
349   llvm::sort(RegAltNameIndices, LessRecord());
350 }
351 
352 /// getRegisterByName - If there is a register with the specific AsmName,
353 /// return it.
354 const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const {
355   const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName();
356   StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name);
357   if (I == Regs.end())
358     return nullptr;
359   return I->second;
360 }
361 
362 std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R)
363       const {
364   const CodeGenRegister *Reg = getRegBank().getReg(R);
365   std::vector<ValueTypeByHwMode> Result;
366   for (const auto &RC : getRegBank().getRegClasses()) {
367     if (RC.contains(Reg)) {
368       ArrayRef<ValueTypeByHwMode> InVTs = RC.getValueTypes();
369       Result.insert(Result.end(), InVTs.begin(), InVTs.end());
370     }
371   }
372 
373   // Remove duplicates.
374   llvm::sort(Result);
375   Result.erase(std::unique(Result.begin(), Result.end()), Result.end());
376   return Result;
377 }
378 
379 
380 void CodeGenTarget::ReadLegalValueTypes() const {
381   for (const auto &RC : getRegBank().getRegClasses())
382     LegalValueTypes.insert(LegalValueTypes.end(), RC.VTs.begin(), RC.VTs.end());
383 
384   // Remove duplicates.
385   llvm::sort(LegalValueTypes);
386   LegalValueTypes.erase(std::unique(LegalValueTypes.begin(),
387                                     LegalValueTypes.end()),
388                         LegalValueTypes.end());
389 }
390 
391 CodeGenSchedModels &CodeGenTarget::getSchedModels() const {
392   if (!SchedModels)
393     SchedModels = std::make_unique<CodeGenSchedModels>(Records, *this);
394   return *SchedModels;
395 }
396 
397 void CodeGenTarget::ReadInstructions() const {
398   NamedRegionTimer T("Read Instructions", "Time spent reading instructions",
399                      "CodeGenTarget", "CodeGenTarget", TimeRegions);
400   std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
401   if (Insts.size() <= 2)
402     PrintFatalError("No 'Instruction' subclasses defined!");
403 
404   // Parse the instructions defined in the .td file.
405   for (unsigned i = 0, e = Insts.size(); i != e; ++i)
406     Instructions[Insts[i]] = std::make_unique<CodeGenInstruction>(Insts[i]);
407 }
408 
409 static const CodeGenInstruction *
410 GetInstByName(const char *Name,
411               const DenseMap<const Record*,
412                              std::unique_ptr<CodeGenInstruction>> &Insts,
413               RecordKeeper &Records) {
414   const Record *Rec = Records.getDef(Name);
415 
416   const auto I = Insts.find(Rec);
417   if (!Rec || I == Insts.end())
418     PrintFatalError(Twine("Could not find '") + Name + "' instruction!");
419   return I->second.get();
420 }
421 
422 static const char *const FixedInstrs[] = {
423 #define HANDLE_TARGET_OPCODE(OPC) #OPC,
424 #include "llvm/Support/TargetOpcodes.def"
425     nullptr};
426 
427 unsigned CodeGenTarget::getNumFixedInstructions() {
428   return array_lengthof(FixedInstrs) - 1;
429 }
430 
431 /// Return all of the instructions defined by the target, ordered by
432 /// their enum value.
433 void CodeGenTarget::ComputeInstrsByEnum() const {
434   const auto &Insts = getInstructions();
435   for (const char *const *p = FixedInstrs; *p; ++p) {
436     const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records);
437     assert(Instr && "Missing target independent instruction");
438     assert(Instr->Namespace == "TargetOpcode" && "Bad namespace");
439     InstrsByEnum.push_back(Instr);
440   }
441   unsigned EndOfPredefines = InstrsByEnum.size();
442   assert(EndOfPredefines == getNumFixedInstructions() &&
443          "Missing generic opcode");
444 
445   for (const auto &I : Insts) {
446     const CodeGenInstruction *CGI = I.second.get();
447     if (CGI->Namespace != "TargetOpcode") {
448       InstrsByEnum.push_back(CGI);
449       if (CGI->TheDef->getValueAsBit("isPseudo"))
450         ++NumPseudoInstructions;
451     }
452   }
453 
454   assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr");
455 
456   // All of the instructions are now in random order based on the map iteration.
457   llvm::sort(
458       InstrsByEnum.begin() + EndOfPredefines, InstrsByEnum.end(),
459       [](const CodeGenInstruction *Rec1, const CodeGenInstruction *Rec2) {
460         const auto &D1 = *Rec1->TheDef;
461         const auto &D2 = *Rec2->TheDef;
462         return std::make_tuple(!D1.getValueAsBit("isPseudo"), D1.getName()) <
463                std::make_tuple(!D2.getValueAsBit("isPseudo"), D2.getName());
464       });
465 }
466 
467 
468 /// isLittleEndianEncoding - Return whether this target encodes its instruction
469 /// in little-endian format, i.e. bits laid out in the order [0..n]
470 ///
471 bool CodeGenTarget::isLittleEndianEncoding() const {
472   return getInstructionSet()->getValueAsBit("isLittleEndianEncoding");
473 }
474 
475 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit
476 /// encodings, reverse the bit order of all instructions.
477 void CodeGenTarget::reverseBitsForLittleEndianEncoding() {
478   if (!isLittleEndianEncoding())
479     return;
480 
481   std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
482   for (Record *R : Insts) {
483     if (R->getValueAsString("Namespace") == "TargetOpcode" ||
484         R->getValueAsBit("isPseudo"))
485       continue;
486 
487     BitsInit *BI = R->getValueAsBitsInit("Inst");
488 
489     unsigned numBits = BI->getNumBits();
490 
491     SmallVector<Init *, 16> NewBits(numBits);
492 
493     for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) {
494       unsigned bitSwapIdx = numBits - bit - 1;
495       Init *OrigBit = BI->getBit(bit);
496       Init *BitSwap = BI->getBit(bitSwapIdx);
497       NewBits[bit]        = BitSwap;
498       NewBits[bitSwapIdx] = OrigBit;
499     }
500     if (numBits % 2) {
501       unsigned middle = (numBits + 1) / 2;
502       NewBits[middle] = BI->getBit(middle);
503     }
504 
505     BitsInit *NewBI = BitsInit::get(NewBits);
506 
507     // Update the bits in reversed order so that emitInstrOpBits will get the
508     // correct endianness.
509     R->getValue("Inst")->setValue(NewBI);
510   }
511 }
512 
513 /// guessInstructionProperties - Return true if it's OK to guess instruction
514 /// properties instead of raising an error.
515 ///
516 /// This is configurable as a temporary migration aid. It will eventually be
517 /// permanently false.
518 bool CodeGenTarget::guessInstructionProperties() const {
519   return getInstructionSet()->getValueAsBit("guessInstructionProperties");
520 }
521 
522 //===----------------------------------------------------------------------===//
523 // ComplexPattern implementation
524 //
525 ComplexPattern::ComplexPattern(Record *R) {
526   Ty          = ::getValueType(R->getValueAsDef("Ty"));
527   NumOperands = R->getValueAsInt("NumOperands");
528   SelectFunc  = R->getValueAsString("SelectFunc");
529   RootNodes   = R->getValueAsListOfDefs("RootNodes");
530 
531   // FIXME: This is a hack to statically increase the priority of patterns which
532   // maps a sub-dag to a complex pattern. e.g. favors LEA over ADD. To get best
533   // possible pattern match we'll need to dynamically calculate the complexity
534   // of all patterns a dag can potentially map to.
535   int64_t RawComplexity = R->getValueAsInt("Complexity");
536   if (RawComplexity == -1)
537     Complexity = NumOperands * 3;
538   else
539     Complexity = RawComplexity;
540 
541   // FIXME: Why is this different from parseSDPatternOperatorProperties?
542   // Parse the properties.
543   Properties = 0;
544   std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties");
545   for (unsigned i = 0, e = PropList.size(); i != e; ++i)
546     if (PropList[i]->getName() == "SDNPHasChain") {
547       Properties |= 1 << SDNPHasChain;
548     } else if (PropList[i]->getName() == "SDNPOptInGlue") {
549       Properties |= 1 << SDNPOptInGlue;
550     } else if (PropList[i]->getName() == "SDNPMayStore") {
551       Properties |= 1 << SDNPMayStore;
552     } else if (PropList[i]->getName() == "SDNPMayLoad") {
553       Properties |= 1 << SDNPMayLoad;
554     } else if (PropList[i]->getName() == "SDNPSideEffect") {
555       Properties |= 1 << SDNPSideEffect;
556     } else if (PropList[i]->getName() == "SDNPMemOperand") {
557       Properties |= 1 << SDNPMemOperand;
558     } else if (PropList[i]->getName() == "SDNPVariadic") {
559       Properties |= 1 << SDNPVariadic;
560     } else if (PropList[i]->getName() == "SDNPWantRoot") {
561       Properties |= 1 << SDNPWantRoot;
562     } else if (PropList[i]->getName() == "SDNPWantParent") {
563       Properties |= 1 << SDNPWantParent;
564     } else {
565       PrintFatalError(R->getLoc(), "Unsupported SD Node property '" +
566                                        PropList[i]->getName() +
567                                        "' on ComplexPattern '" + R->getName() +
568                                        "'!");
569     }
570 }
571 
572 //===----------------------------------------------------------------------===//
573 // CodeGenIntrinsic Implementation
574 //===----------------------------------------------------------------------===//
575 
576 CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC,
577                                              bool TargetOnly) {
578   std::vector<Record*> Defs = RC.getAllDerivedDefinitions("Intrinsic");
579 
580   Intrinsics.reserve(Defs.size());
581 
582   for (unsigned I = 0, e = Defs.size(); I != e; ++I) {
583     bool isTarget = Defs[I]->getValueAsBit("isTarget");
584     if (isTarget == TargetOnly)
585       Intrinsics.push_back(CodeGenIntrinsic(Defs[I]));
586   }
587   llvm::sort(Intrinsics,
588              [](const CodeGenIntrinsic &LHS, const CodeGenIntrinsic &RHS) {
589                return std::tie(LHS.TargetPrefix, LHS.Name) <
590                       std::tie(RHS.TargetPrefix, RHS.Name);
591              });
592   Targets.push_back({"", 0, 0});
593   for (size_t I = 0, E = Intrinsics.size(); I < E; ++I)
594     if (Intrinsics[I].TargetPrefix != Targets.back().Name) {
595       Targets.back().Count = I - Targets.back().Offset;
596       Targets.push_back({Intrinsics[I].TargetPrefix, I, 0});
597     }
598   Targets.back().Count = Intrinsics.size() - Targets.back().Offset;
599 }
600 
601 CodeGenIntrinsic::CodeGenIntrinsic(Record *R) {
602   TheDef = R;
603   std::string DefName = R->getName();
604   ArrayRef<SMLoc> DefLoc = R->getLoc();
605   ModRef = ReadWriteMem;
606   Properties = 0;
607   isOverloaded = false;
608   isCommutative = false;
609   canThrow = false;
610   isNoReturn = false;
611   isWillReturn = false;
612   isCold = false;
613   isNoDuplicate = false;
614   isConvergent = false;
615   isSpeculatable = false;
616   hasSideEffects = false;
617 
618   if (DefName.size() <= 4 ||
619       std::string(DefName.begin(), DefName.begin() + 4) != "int_")
620     PrintFatalError(DefLoc,
621                     "Intrinsic '" + DefName + "' does not start with 'int_'!");
622 
623   EnumName = std::string(DefName.begin()+4, DefName.end());
624 
625   if (R->getValue("GCCBuiltinName"))  // Ignore a missing GCCBuiltinName field.
626     GCCBuiltinName = R->getValueAsString("GCCBuiltinName");
627   if (R->getValue("MSBuiltinName"))   // Ignore a missing MSBuiltinName field.
628     MSBuiltinName = R->getValueAsString("MSBuiltinName");
629 
630   TargetPrefix = R->getValueAsString("TargetPrefix");
631   Name = R->getValueAsString("LLVMName");
632 
633   if (Name == "") {
634     // If an explicit name isn't specified, derive one from the DefName.
635     Name = "llvm.";
636 
637     for (unsigned i = 0, e = EnumName.size(); i != e; ++i)
638       Name += (EnumName[i] == '_') ? '.' : EnumName[i];
639   } else {
640     // Verify it starts with "llvm.".
641     if (Name.size() <= 5 ||
642         std::string(Name.begin(), Name.begin() + 5) != "llvm.")
643       PrintFatalError(DefLoc, "Intrinsic '" + DefName +
644                                   "'s name does not start with 'llvm.'!");
645   }
646 
647   // If TargetPrefix is specified, make sure that Name starts with
648   // "llvm.<targetprefix>.".
649   if (!TargetPrefix.empty()) {
650     if (Name.size() < 6+TargetPrefix.size() ||
651         std::string(Name.begin() + 5, Name.begin() + 6 + TargetPrefix.size())
652         != (TargetPrefix + "."))
653       PrintFatalError(DefLoc, "Intrinsic '" + DefName +
654                                   "' does not start with 'llvm." +
655                                   TargetPrefix + ".'!");
656   }
657 
658   ListInit *RetTypes = R->getValueAsListInit("RetTypes");
659   ListInit *ParamTypes = R->getValueAsListInit("ParamTypes");
660 
661   // First collate a list of overloaded types.
662   std::vector<MVT::SimpleValueType> OverloadedVTs;
663   for (ListInit *TypeList : {RetTypes, ParamTypes}) {
664     for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
665       Record *TyEl = TypeList->getElementAsRecord(i);
666       assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
667 
668       if (TyEl->isSubClassOf("LLVMMatchType"))
669         continue;
670 
671       MVT::SimpleValueType VT = getValueType(TyEl->getValueAsDef("VT"));
672       if (MVT(VT).isOverloaded()) {
673         OverloadedVTs.push_back(VT);
674         isOverloaded = true;
675       }
676     }
677   }
678 
679   // Parse the list of return types.
680   ListInit *TypeList = RetTypes;
681   for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
682     Record *TyEl = TypeList->getElementAsRecord(i);
683     assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
684     MVT::SimpleValueType VT;
685     if (TyEl->isSubClassOf("LLVMMatchType")) {
686       unsigned MatchTy = TyEl->getValueAsInt("Number");
687       assert(MatchTy < OverloadedVTs.size() &&
688              "Invalid matching number!");
689       VT = OverloadedVTs[MatchTy];
690       // It only makes sense to use the extended and truncated vector element
691       // variants with iAny types; otherwise, if the intrinsic is not
692       // overloaded, all the types can be specified directly.
693       assert(((!TyEl->isSubClassOf("LLVMExtendedType") &&
694                !TyEl->isSubClassOf("LLVMTruncatedType")) ||
695               VT == MVT::iAny || VT == MVT::vAny) &&
696              "Expected iAny or vAny type");
697     } else {
698       VT = getValueType(TyEl->getValueAsDef("VT"));
699     }
700 
701     // Reject invalid types.
702     if (VT == MVT::isVoid)
703       PrintFatalError(DefLoc, "Intrinsic '" + DefName +
704                                   " has void in result type list!");
705 
706     IS.RetVTs.push_back(VT);
707     IS.RetTypeDefs.push_back(TyEl);
708   }
709 
710   // Parse the list of parameter types.
711   TypeList = ParamTypes;
712   for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
713     Record *TyEl = TypeList->getElementAsRecord(i);
714     assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
715     MVT::SimpleValueType VT;
716     if (TyEl->isSubClassOf("LLVMMatchType")) {
717       unsigned MatchTy = TyEl->getValueAsInt("Number");
718       if (MatchTy >= OverloadedVTs.size()) {
719         PrintError(R->getLoc(),
720                    "Parameter #" + Twine(i) + " has out of bounds matching "
721                    "number " + Twine(MatchTy));
722         PrintFatalError(DefLoc,
723                         Twine("ParamTypes is ") + TypeList->getAsString());
724       }
725       VT = OverloadedVTs[MatchTy];
726       // It only makes sense to use the extended and truncated vector element
727       // variants with iAny types; otherwise, if the intrinsic is not
728       // overloaded, all the types can be specified directly.
729       assert(((!TyEl->isSubClassOf("LLVMExtendedType") &&
730                !TyEl->isSubClassOf("LLVMTruncatedType") &&
731                !TyEl->isSubClassOf("LLVMScalarOrSameVectorWidth")) ||
732               VT == MVT::iAny || VT == MVT::vAny) &&
733              "Expected iAny or vAny type");
734     } else
735       VT = getValueType(TyEl->getValueAsDef("VT"));
736 
737     // Reject invalid types.
738     if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/)
739       PrintFatalError(DefLoc, "Intrinsic '" + DefName +
740                                   " has void in result type list!");
741 
742     IS.ParamVTs.push_back(VT);
743     IS.ParamTypeDefs.push_back(TyEl);
744   }
745 
746   // Parse the intrinsic properties.
747   ListInit *PropList = R->getValueAsListInit("IntrProperties");
748   for (unsigned i = 0, e = PropList->size(); i != e; ++i) {
749     Record *Property = PropList->getElementAsRecord(i);
750     assert(Property->isSubClassOf("IntrinsicProperty") &&
751            "Expected a property!");
752 
753     if (Property->getName() == "IntrNoMem")
754       ModRef = NoMem;
755     else if (Property->getName() == "IntrReadMem")
756       ModRef = ModRefBehavior(ModRef & ~MR_Mod);
757     else if (Property->getName() == "IntrWriteMem")
758       ModRef = ModRefBehavior(ModRef & ~MR_Ref);
759     else if (Property->getName() == "IntrArgMemOnly")
760       ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem);
761     else if (Property->getName() == "IntrInaccessibleMemOnly")
762       ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_InaccessibleMem);
763     else if (Property->getName() == "IntrInaccessibleMemOrArgMemOnly")
764       ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem |
765                               MR_InaccessibleMem);
766     else if (Property->getName() == "Commutative")
767       isCommutative = true;
768     else if (Property->getName() == "Throws")
769       canThrow = true;
770     else if (Property->getName() == "IntrNoDuplicate")
771       isNoDuplicate = true;
772     else if (Property->getName() == "IntrConvergent")
773       isConvergent = true;
774     else if (Property->getName() == "IntrNoReturn")
775       isNoReturn = true;
776     else if (Property->getName() == "IntrWillReturn")
777       isWillReturn = true;
778     else if (Property->getName() == "IntrCold")
779       isCold = true;
780     else if (Property->getName() == "IntrSpeculatable")
781       isSpeculatable = true;
782     else if (Property->getName() == "IntrHasSideEffects")
783       hasSideEffects = true;
784     else if (Property->isSubClassOf("NoCapture")) {
785       unsigned ArgNo = Property->getValueAsInt("ArgNo");
786       ArgumentAttributes.push_back(std::make_pair(ArgNo, NoCapture));
787     } else if (Property->isSubClassOf("NoAlias")) {
788       unsigned ArgNo = Property->getValueAsInt("ArgNo");
789       ArgumentAttributes.push_back(std::make_pair(ArgNo, NoAlias));
790     } else if (Property->isSubClassOf("Returned")) {
791       unsigned ArgNo = Property->getValueAsInt("ArgNo");
792       ArgumentAttributes.push_back(std::make_pair(ArgNo, Returned));
793     } else if (Property->isSubClassOf("ReadOnly")) {
794       unsigned ArgNo = Property->getValueAsInt("ArgNo");
795       ArgumentAttributes.push_back(std::make_pair(ArgNo, ReadOnly));
796     } else if (Property->isSubClassOf("WriteOnly")) {
797       unsigned ArgNo = Property->getValueAsInt("ArgNo");
798       ArgumentAttributes.push_back(std::make_pair(ArgNo, WriteOnly));
799     } else if (Property->isSubClassOf("ReadNone")) {
800       unsigned ArgNo = Property->getValueAsInt("ArgNo");
801       ArgumentAttributes.push_back(std::make_pair(ArgNo, ReadNone));
802     } else if (Property->isSubClassOf("ImmArg")) {
803       unsigned ArgNo = Property->getValueAsInt("ArgNo");
804       ArgumentAttributes.push_back(std::make_pair(ArgNo, ImmArg));
805     } else
806       llvm_unreachable("Unknown property!");
807   }
808 
809   // Also record the SDPatternOperator Properties.
810   Properties = parseSDPatternOperatorProperties(R);
811 
812   // Sort the argument attributes for later benefit.
813   llvm::sort(ArgumentAttributes);
814 }
815 
816 bool CodeGenIntrinsic::isParamAPointer(unsigned ParamIdx) const {
817   if (ParamIdx >= IS.ParamVTs.size())
818     return false;
819   MVT ParamType = MVT(IS.ParamVTs[ParamIdx]);
820   return ParamType == MVT::iPTR || ParamType == MVT::iPTRAny;
821 }
822