1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This class wraps target description classes used by the various code 10 // generation TableGen backends. This makes it easier to access the data and 11 // provides a single place that needs to check it for validity. All of these 12 // classes abort on error conditions. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "CodeGenTarget.h" 17 #include "CodeGenDAGPatterns.h" 18 #include "CodeGenIntrinsics.h" 19 #include "CodeGenSchedule.h" 20 #include "llvm/ADT/STLExtras.h" 21 #include "llvm/ADT/StringExtras.h" 22 #include "llvm/Support/CommandLine.h" 23 #include "llvm/Support/Timer.h" 24 #include "llvm/TableGen/Error.h" 25 #include "llvm/TableGen/Record.h" 26 #include "llvm/TableGen/TableGenBackend.h" 27 #include <algorithm> 28 using namespace llvm; 29 30 cl::OptionCategory AsmParserCat("Options for -gen-asm-parser"); 31 cl::OptionCategory AsmWriterCat("Options for -gen-asm-writer"); 32 33 static cl::opt<unsigned> 34 AsmParserNum("asmparsernum", cl::init(0), 35 cl::desc("Make -gen-asm-parser emit assembly parser #N"), 36 cl::cat(AsmParserCat)); 37 38 static cl::opt<unsigned> 39 AsmWriterNum("asmwriternum", cl::init(0), 40 cl::desc("Make -gen-asm-writer emit assembly writer #N"), 41 cl::cat(AsmWriterCat)); 42 43 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen 44 /// record corresponds to. 45 MVT::SimpleValueType llvm::getValueType(Record *Rec) { 46 return (MVT::SimpleValueType)Rec->getValueAsInt("Value"); 47 } 48 49 StringRef llvm::getName(MVT::SimpleValueType T) { 50 switch (T) { 51 case MVT::Other: return "UNKNOWN"; 52 case MVT::iPTR: return "TLI.getPointerTy()"; 53 case MVT::iPTRAny: return "TLI.getPointerTy()"; 54 default: return getEnumName(T); 55 } 56 } 57 58 StringRef llvm::getEnumName(MVT::SimpleValueType T) { 59 switch (T) { 60 case MVT::Other: return "MVT::Other"; 61 case MVT::i1: return "MVT::i1"; 62 case MVT::i8: return "MVT::i8"; 63 case MVT::i16: return "MVT::i16"; 64 case MVT::i32: return "MVT::i32"; 65 case MVT::i64: return "MVT::i64"; 66 case MVT::i128: return "MVT::i128"; 67 case MVT::Any: return "MVT::Any"; 68 case MVT::iAny: return "MVT::iAny"; 69 case MVT::fAny: return "MVT::fAny"; 70 case MVT::vAny: return "MVT::vAny"; 71 case MVT::f16: return "MVT::f16"; 72 case MVT::bf16: return "MVT::bf16"; 73 case MVT::f32: return "MVT::f32"; 74 case MVT::f64: return "MVT::f64"; 75 case MVT::f80: return "MVT::f80"; 76 case MVT::f128: return "MVT::f128"; 77 case MVT::ppcf128: return "MVT::ppcf128"; 78 case MVT::x86mmx: return "MVT::x86mmx"; 79 case MVT::Glue: return "MVT::Glue"; 80 case MVT::isVoid: return "MVT::isVoid"; 81 case MVT::v1i1: return "MVT::v1i1"; 82 case MVT::v2i1: return "MVT::v2i1"; 83 case MVT::v4i1: return "MVT::v4i1"; 84 case MVT::v8i1: return "MVT::v8i1"; 85 case MVT::v16i1: return "MVT::v16i1"; 86 case MVT::v32i1: return "MVT::v32i1"; 87 case MVT::v64i1: return "MVT::v64i1"; 88 case MVT::v128i1: return "MVT::v128i1"; 89 case MVT::v256i1: return "MVT::v256i1"; 90 case MVT::v512i1: return "MVT::v512i1"; 91 case MVT::v1024i1: return "MVT::v1024i1"; 92 case MVT::v1i8: return "MVT::v1i8"; 93 case MVT::v2i8: return "MVT::v2i8"; 94 case MVT::v4i8: return "MVT::v4i8"; 95 case MVT::v8i8: return "MVT::v8i8"; 96 case MVT::v16i8: return "MVT::v16i8"; 97 case MVT::v32i8: return "MVT::v32i8"; 98 case MVT::v64i8: return "MVT::v64i8"; 99 case MVT::v128i8: return "MVT::v128i8"; 100 case MVT::v256i8: return "MVT::v256i8"; 101 case MVT::v1i16: return "MVT::v1i16"; 102 case MVT::v2i16: return "MVT::v2i16"; 103 case MVT::v3i16: return "MVT::v3i16"; 104 case MVT::v4i16: return "MVT::v4i16"; 105 case MVT::v8i16: return "MVT::v8i16"; 106 case MVT::v16i16: return "MVT::v16i16"; 107 case MVT::v32i16: return "MVT::v32i16"; 108 case MVT::v64i16: return "MVT::v64i16"; 109 case MVT::v128i16: return "MVT::v128i16"; 110 case MVT::v1i32: return "MVT::v1i32"; 111 case MVT::v2i32: return "MVT::v2i32"; 112 case MVT::v3i32: return "MVT::v3i32"; 113 case MVT::v4i32: return "MVT::v4i32"; 114 case MVT::v5i32: return "MVT::v5i32"; 115 case MVT::v8i32: return "MVT::v8i32"; 116 case MVT::v16i32: return "MVT::v16i32"; 117 case MVT::v32i32: return "MVT::v32i32"; 118 case MVT::v64i32: return "MVT::v64i32"; 119 case MVT::v128i32: return "MVT::v128i32"; 120 case MVT::v256i32: return "MVT::v256i32"; 121 case MVT::v512i32: return "MVT::v512i32"; 122 case MVT::v1024i32: return "MVT::v1024i32"; 123 case MVT::v2048i32: return "MVT::v2048i32"; 124 case MVT::v1i64: return "MVT::v1i64"; 125 case MVT::v2i64: return "MVT::v2i64"; 126 case MVT::v4i64: return "MVT::v4i64"; 127 case MVT::v8i64: return "MVT::v8i64"; 128 case MVT::v16i64: return "MVT::v16i64"; 129 case MVT::v32i64: return "MVT::v32i64"; 130 case MVT::v64i64: return "MVT::v64i64"; 131 case MVT::v128i64: return "MVT::v128i64"; 132 case MVT::v256i64: return "MVT::v256i64"; 133 case MVT::v1i128: return "MVT::v1i128"; 134 case MVT::v2f16: return "MVT::v2f16"; 135 case MVT::v3f16: return "MVT::v3f16"; 136 case MVT::v4f16: return "MVT::v4f16"; 137 case MVT::v8f16: return "MVT::v8f16"; 138 case MVT::v16f16: return "MVT::v16f16"; 139 case MVT::v32f16: return "MVT::v32f16"; 140 case MVT::v64f16: return "MVT::v64f16"; 141 case MVT::v128f16: return "MVT::v128f16"; 142 case MVT::v2bf16: return "MVT::v2bf16"; 143 case MVT::v3bf16: return "MVT::v3bf16"; 144 case MVT::v4bf16: return "MVT::v4bf16"; 145 case MVT::v8bf16: return "MVT::v8bf16"; 146 case MVT::v16bf16: return "MVT::v16bf16"; 147 case MVT::v32bf16: return "MVT::v32bf16"; 148 case MVT::v64bf16: return "MVT::v64bf16"; 149 case MVT::v128bf16: return "MVT::v128bf16"; 150 case MVT::v1f32: return "MVT::v1f32"; 151 case MVT::v2f32: return "MVT::v2f32"; 152 case MVT::v3f32: return "MVT::v3f32"; 153 case MVT::v4f32: return "MVT::v4f32"; 154 case MVT::v5f32: return "MVT::v5f32"; 155 case MVT::v8f32: return "MVT::v8f32"; 156 case MVT::v16f32: return "MVT::v16f32"; 157 case MVT::v32f32: return "MVT::v32f32"; 158 case MVT::v64f32: return "MVT::v64f32"; 159 case MVT::v128f32: return "MVT::v128f32"; 160 case MVT::v256f32: return "MVT::v256f32"; 161 case MVT::v512f32: return "MVT::v512f32"; 162 case MVT::v1024f32: return "MVT::v1024f32"; 163 case MVT::v2048f32: return "MVT::v2048f32"; 164 case MVT::v1f64: return "MVT::v1f64"; 165 case MVT::v2f64: return "MVT::v2f64"; 166 case MVT::v4f64: return "MVT::v4f64"; 167 case MVT::v8f64: return "MVT::v8f64"; 168 case MVT::v16f64: return "MVT::v16f64"; 169 case MVT::v32f64: return "MVT::v32f64"; 170 case MVT::v64f64: return "MVT::v64f64"; 171 case MVT::v128f64: return "MVT::v128f64"; 172 case MVT::v256f64: return "MVT::v256f64"; 173 case MVT::nxv1i1: return "MVT::nxv1i1"; 174 case MVT::nxv2i1: return "MVT::nxv2i1"; 175 case MVT::nxv4i1: return "MVT::nxv4i1"; 176 case MVT::nxv8i1: return "MVT::nxv8i1"; 177 case MVT::nxv16i1: return "MVT::nxv16i1"; 178 case MVT::nxv32i1: return "MVT::nxv32i1"; 179 case MVT::nxv64i1: return "MVT::nxv64i1"; 180 case MVT::nxv1i8: return "MVT::nxv1i8"; 181 case MVT::nxv2i8: return "MVT::nxv2i8"; 182 case MVT::nxv4i8: return "MVT::nxv4i8"; 183 case MVT::nxv8i8: return "MVT::nxv8i8"; 184 case MVT::nxv16i8: return "MVT::nxv16i8"; 185 case MVT::nxv32i8: return "MVT::nxv32i8"; 186 case MVT::nxv64i8: return "MVT::nxv64i8"; 187 case MVT::nxv1i16: return "MVT::nxv1i16"; 188 case MVT::nxv2i16: return "MVT::nxv2i16"; 189 case MVT::nxv4i16: return "MVT::nxv4i16"; 190 case MVT::nxv8i16: return "MVT::nxv8i16"; 191 case MVT::nxv16i16: return "MVT::nxv16i16"; 192 case MVT::nxv32i16: return "MVT::nxv32i16"; 193 case MVT::nxv1i32: return "MVT::nxv1i32"; 194 case MVT::nxv2i32: return "MVT::nxv2i32"; 195 case MVT::nxv4i32: return "MVT::nxv4i32"; 196 case MVT::nxv8i32: return "MVT::nxv8i32"; 197 case MVT::nxv16i32: return "MVT::nxv16i32"; 198 case MVT::nxv32i32: return "MVT::nxv32i32"; 199 case MVT::nxv1i64: return "MVT::nxv1i64"; 200 case MVT::nxv2i64: return "MVT::nxv2i64"; 201 case MVT::nxv4i64: return "MVT::nxv4i64"; 202 case MVT::nxv8i64: return "MVT::nxv8i64"; 203 case MVT::nxv16i64: return "MVT::nxv16i64"; 204 case MVT::nxv32i64: return "MVT::nxv32i64"; 205 case MVT::nxv1f16: return "MVT::nxv1f16"; 206 case MVT::nxv2f16: return "MVT::nxv2f16"; 207 case MVT::nxv4f16: return "MVT::nxv4f16"; 208 case MVT::nxv8f16: return "MVT::nxv8f16"; 209 case MVT::nxv16f16: return "MVT::nxv16f16"; 210 case MVT::nxv32f16: return "MVT::nxv32f16"; 211 case MVT::nxv2bf16: return "MVT::nxv2bf16"; 212 case MVT::nxv4bf16: return "MVT::nxv4bf16"; 213 case MVT::nxv8bf16: return "MVT::nxv8bf16"; 214 case MVT::nxv1f32: return "MVT::nxv1f32"; 215 case MVT::nxv2f32: return "MVT::nxv2f32"; 216 case MVT::nxv4f32: return "MVT::nxv4f32"; 217 case MVT::nxv8f32: return "MVT::nxv8f32"; 218 case MVT::nxv16f32: return "MVT::nxv16f32"; 219 case MVT::nxv1f64: return "MVT::nxv1f64"; 220 case MVT::nxv2f64: return "MVT::nxv2f64"; 221 case MVT::nxv4f64: return "MVT::nxv4f64"; 222 case MVT::nxv8f64: return "MVT::nxv8f64"; 223 case MVT::token: return "MVT::token"; 224 case MVT::Metadata: return "MVT::Metadata"; 225 case MVT::iPTR: return "MVT::iPTR"; 226 case MVT::iPTRAny: return "MVT::iPTRAny"; 227 case MVT::Untyped: return "MVT::Untyped"; 228 case MVT::exnref: return "MVT::exnref"; 229 case MVT::funcref: return "MVT::funcref"; 230 case MVT::externref: return "MVT::externref"; 231 default: llvm_unreachable("ILLEGAL VALUE TYPE!"); 232 } 233 } 234 235 /// getQualifiedName - Return the name of the specified record, with a 236 /// namespace qualifier if the record contains one. 237 /// 238 std::string llvm::getQualifiedName(const Record *R) { 239 std::string Namespace; 240 if (R->getValue("Namespace")) 241 Namespace = std::string(R->getValueAsString("Namespace")); 242 if (Namespace.empty()) 243 return std::string(R->getName()); 244 return Namespace + "::" + R->getName().str(); 245 } 246 247 248 /// getTarget - Return the current instance of the Target class. 249 /// 250 CodeGenTarget::CodeGenTarget(RecordKeeper &records) 251 : Records(records), CGH(records) { 252 std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target"); 253 if (Targets.size() == 0) 254 PrintFatalError("ERROR: No 'Target' subclasses defined!"); 255 if (Targets.size() != 1) 256 PrintFatalError("ERROR: Multiple subclasses of Target defined!"); 257 TargetRec = Targets[0]; 258 } 259 260 CodeGenTarget::~CodeGenTarget() { 261 } 262 263 const StringRef CodeGenTarget::getName() const { 264 return TargetRec->getName(); 265 } 266 267 /// getInstNamespace - Find and return the target machine's instruction 268 /// namespace. The namespace is cached because it is requested multiple times. 269 StringRef CodeGenTarget::getInstNamespace() const { 270 if (InstNamespace.empty()) { 271 for (const CodeGenInstruction *Inst : getInstructionsByEnumValue()) { 272 // We are not interested in the "TargetOpcode" namespace. 273 if (Inst->Namespace != "TargetOpcode") { 274 InstNamespace = Inst->Namespace; 275 break; 276 } 277 } 278 } 279 280 return InstNamespace; 281 } 282 283 StringRef CodeGenTarget::getRegNamespace() const { 284 auto &RegClasses = RegBank->getRegClasses(); 285 return RegClasses.size() > 0 ? RegClasses.front().Namespace : ""; 286 } 287 288 Record *CodeGenTarget::getInstructionSet() const { 289 return TargetRec->getValueAsDef("InstructionSet"); 290 } 291 292 bool CodeGenTarget::getAllowRegisterRenaming() const { 293 return TargetRec->getValueAsInt("AllowRegisterRenaming"); 294 } 295 296 /// getAsmParser - Return the AssemblyParser definition for this target. 297 /// 298 Record *CodeGenTarget::getAsmParser() const { 299 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers"); 300 if (AsmParserNum >= LI.size()) 301 PrintFatalError("Target does not have an AsmParser #" + 302 Twine(AsmParserNum) + "!"); 303 return LI[AsmParserNum]; 304 } 305 306 /// getAsmParserVariant - Return the AssemblyParserVariant definition for 307 /// this target. 308 /// 309 Record *CodeGenTarget::getAsmParserVariant(unsigned i) const { 310 std::vector<Record*> LI = 311 TargetRec->getValueAsListOfDefs("AssemblyParserVariants"); 312 if (i >= LI.size()) 313 PrintFatalError("Target does not have an AsmParserVariant #" + Twine(i) + 314 "!"); 315 return LI[i]; 316 } 317 318 /// getAsmParserVariantCount - Return the AssemblyParserVariant definition 319 /// available for this target. 320 /// 321 unsigned CodeGenTarget::getAsmParserVariantCount() const { 322 std::vector<Record*> LI = 323 TargetRec->getValueAsListOfDefs("AssemblyParserVariants"); 324 return LI.size(); 325 } 326 327 /// getAsmWriter - Return the AssemblyWriter definition for this target. 328 /// 329 Record *CodeGenTarget::getAsmWriter() const { 330 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters"); 331 if (AsmWriterNum >= LI.size()) 332 PrintFatalError("Target does not have an AsmWriter #" + 333 Twine(AsmWriterNum) + "!"); 334 return LI[AsmWriterNum]; 335 } 336 337 CodeGenRegBank &CodeGenTarget::getRegBank() const { 338 if (!RegBank) 339 RegBank = std::make_unique<CodeGenRegBank>(Records, getHwModes()); 340 return *RegBank; 341 } 342 343 Optional<CodeGenRegisterClass *> 344 CodeGenTarget::getSuperRegForSubReg(const ValueTypeByHwMode &ValueTy, 345 CodeGenRegBank &RegBank, 346 const CodeGenSubRegIndex *SubIdx) const { 347 std::vector<CodeGenRegisterClass *> Candidates; 348 auto &RegClasses = RegBank.getRegClasses(); 349 350 // Try to find a register class which supports ValueTy, and also contains 351 // SubIdx. 352 for (CodeGenRegisterClass &RC : RegClasses) { 353 // Is there a subclass of this class which contains this subregister index? 354 CodeGenRegisterClass *SubClassWithSubReg = RC.getSubClassWithSubReg(SubIdx); 355 if (!SubClassWithSubReg) 356 continue; 357 358 // We have a class. Check if it supports this value type. 359 if (llvm::none_of(SubClassWithSubReg->VTs, 360 [&ValueTy](const ValueTypeByHwMode &ClassVT) { 361 return ClassVT == ValueTy; 362 })) 363 continue; 364 365 // We have a register class which supports both the value type and 366 // subregister index. Remember it. 367 Candidates.push_back(SubClassWithSubReg); 368 } 369 370 // If we didn't find anything, we're done. 371 if (Candidates.empty()) 372 return None; 373 374 // Find and return the largest of our candidate classes. 375 llvm::stable_sort(Candidates, [&](const CodeGenRegisterClass *A, 376 const CodeGenRegisterClass *B) { 377 if (A->getMembers().size() > B->getMembers().size()) 378 return true; 379 380 if (A->getMembers().size() < B->getMembers().size()) 381 return false; 382 383 // Order by name as a tie-breaker. 384 return StringRef(A->getName()) < B->getName(); 385 }); 386 387 return Candidates[0]; 388 } 389 390 void CodeGenTarget::ReadRegAltNameIndices() const { 391 RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex"); 392 llvm::sort(RegAltNameIndices, LessRecord()); 393 } 394 395 /// getRegisterByName - If there is a register with the specific AsmName, 396 /// return it. 397 const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const { 398 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName(); 399 StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name); 400 if (I == Regs.end()) 401 return nullptr; 402 return I->second; 403 } 404 405 std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R) 406 const { 407 const CodeGenRegister *Reg = getRegBank().getReg(R); 408 std::vector<ValueTypeByHwMode> Result; 409 for (const auto &RC : getRegBank().getRegClasses()) { 410 if (RC.contains(Reg)) { 411 ArrayRef<ValueTypeByHwMode> InVTs = RC.getValueTypes(); 412 Result.insert(Result.end(), InVTs.begin(), InVTs.end()); 413 } 414 } 415 416 // Remove duplicates. 417 llvm::sort(Result); 418 Result.erase(std::unique(Result.begin(), Result.end()), Result.end()); 419 return Result; 420 } 421 422 423 void CodeGenTarget::ReadLegalValueTypes() const { 424 for (const auto &RC : getRegBank().getRegClasses()) 425 LegalValueTypes.insert(LegalValueTypes.end(), RC.VTs.begin(), RC.VTs.end()); 426 427 // Remove duplicates. 428 llvm::sort(LegalValueTypes); 429 LegalValueTypes.erase(std::unique(LegalValueTypes.begin(), 430 LegalValueTypes.end()), 431 LegalValueTypes.end()); 432 } 433 434 CodeGenSchedModels &CodeGenTarget::getSchedModels() const { 435 if (!SchedModels) 436 SchedModels = std::make_unique<CodeGenSchedModels>(Records, *this); 437 return *SchedModels; 438 } 439 440 void CodeGenTarget::ReadInstructions() const { 441 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction"); 442 if (Insts.size() <= 2) 443 PrintFatalError("No 'Instruction' subclasses defined!"); 444 445 // Parse the instructions defined in the .td file. 446 for (unsigned i = 0, e = Insts.size(); i != e; ++i) 447 Instructions[Insts[i]] = std::make_unique<CodeGenInstruction>(Insts[i]); 448 } 449 450 static const CodeGenInstruction * 451 GetInstByName(const char *Name, 452 const DenseMap<const Record*, 453 std::unique_ptr<CodeGenInstruction>> &Insts, 454 RecordKeeper &Records) { 455 const Record *Rec = Records.getDef(Name); 456 457 const auto I = Insts.find(Rec); 458 if (!Rec || I == Insts.end()) 459 PrintFatalError(Twine("Could not find '") + Name + "' instruction!"); 460 return I->second.get(); 461 } 462 463 static const char *const FixedInstrs[] = { 464 #define HANDLE_TARGET_OPCODE(OPC) #OPC, 465 #include "llvm/Support/TargetOpcodes.def" 466 nullptr}; 467 468 unsigned CodeGenTarget::getNumFixedInstructions() { 469 return array_lengthof(FixedInstrs) - 1; 470 } 471 472 /// Return all of the instructions defined by the target, ordered by 473 /// their enum value. 474 void CodeGenTarget::ComputeInstrsByEnum() const { 475 const auto &Insts = getInstructions(); 476 for (const char *const *p = FixedInstrs; *p; ++p) { 477 const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records); 478 assert(Instr && "Missing target independent instruction"); 479 assert(Instr->Namespace == "TargetOpcode" && "Bad namespace"); 480 InstrsByEnum.push_back(Instr); 481 } 482 unsigned EndOfPredefines = InstrsByEnum.size(); 483 assert(EndOfPredefines == getNumFixedInstructions() && 484 "Missing generic opcode"); 485 486 for (const auto &I : Insts) { 487 const CodeGenInstruction *CGI = I.second.get(); 488 if (CGI->Namespace != "TargetOpcode") { 489 InstrsByEnum.push_back(CGI); 490 if (CGI->TheDef->getValueAsBit("isPseudo")) 491 ++NumPseudoInstructions; 492 } 493 } 494 495 assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr"); 496 497 // All of the instructions are now in random order based on the map iteration. 498 llvm::sort( 499 InstrsByEnum.begin() + EndOfPredefines, InstrsByEnum.end(), 500 [](const CodeGenInstruction *Rec1, const CodeGenInstruction *Rec2) { 501 const auto &D1 = *Rec1->TheDef; 502 const auto &D2 = *Rec2->TheDef; 503 return std::make_tuple(!D1.getValueAsBit("isPseudo"), D1.getName()) < 504 std::make_tuple(!D2.getValueAsBit("isPseudo"), D2.getName()); 505 }); 506 } 507 508 509 /// isLittleEndianEncoding - Return whether this target encodes its instruction 510 /// in little-endian format, i.e. bits laid out in the order [0..n] 511 /// 512 bool CodeGenTarget::isLittleEndianEncoding() const { 513 return getInstructionSet()->getValueAsBit("isLittleEndianEncoding"); 514 } 515 516 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit 517 /// encodings, reverse the bit order of all instructions. 518 void CodeGenTarget::reverseBitsForLittleEndianEncoding() { 519 if (!isLittleEndianEncoding()) 520 return; 521 522 std::vector<Record *> Insts = 523 Records.getAllDerivedDefinitions("InstructionEncoding"); 524 for (Record *R : Insts) { 525 if (R->getValueAsString("Namespace") == "TargetOpcode" || 526 R->getValueAsBit("isPseudo")) 527 continue; 528 529 BitsInit *BI = R->getValueAsBitsInit("Inst"); 530 531 unsigned numBits = BI->getNumBits(); 532 533 SmallVector<Init *, 16> NewBits(numBits); 534 535 for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) { 536 unsigned bitSwapIdx = numBits - bit - 1; 537 Init *OrigBit = BI->getBit(bit); 538 Init *BitSwap = BI->getBit(bitSwapIdx); 539 NewBits[bit] = BitSwap; 540 NewBits[bitSwapIdx] = OrigBit; 541 } 542 if (numBits % 2) { 543 unsigned middle = (numBits + 1) / 2; 544 NewBits[middle] = BI->getBit(middle); 545 } 546 547 BitsInit *NewBI = BitsInit::get(NewBits); 548 549 // Update the bits in reversed order so that emitInstrOpBits will get the 550 // correct endianness. 551 R->getValue("Inst")->setValue(NewBI); 552 } 553 } 554 555 /// guessInstructionProperties - Return true if it's OK to guess instruction 556 /// properties instead of raising an error. 557 /// 558 /// This is configurable as a temporary migration aid. It will eventually be 559 /// permanently false. 560 bool CodeGenTarget::guessInstructionProperties() const { 561 return getInstructionSet()->getValueAsBit("guessInstructionProperties"); 562 } 563 564 //===----------------------------------------------------------------------===// 565 // ComplexPattern implementation 566 // 567 ComplexPattern::ComplexPattern(Record *R) { 568 Ty = ::getValueType(R->getValueAsDef("Ty")); 569 NumOperands = R->getValueAsInt("NumOperands"); 570 SelectFunc = std::string(R->getValueAsString("SelectFunc")); 571 RootNodes = R->getValueAsListOfDefs("RootNodes"); 572 573 // FIXME: This is a hack to statically increase the priority of patterns which 574 // maps a sub-dag to a complex pattern. e.g. favors LEA over ADD. To get best 575 // possible pattern match we'll need to dynamically calculate the complexity 576 // of all patterns a dag can potentially map to. 577 int64_t RawComplexity = R->getValueAsInt("Complexity"); 578 if (RawComplexity == -1) 579 Complexity = NumOperands * 3; 580 else 581 Complexity = RawComplexity; 582 583 // FIXME: Why is this different from parseSDPatternOperatorProperties? 584 // Parse the properties. 585 Properties = 0; 586 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties"); 587 for (unsigned i = 0, e = PropList.size(); i != e; ++i) 588 if (PropList[i]->getName() == "SDNPHasChain") { 589 Properties |= 1 << SDNPHasChain; 590 } else if (PropList[i]->getName() == "SDNPOptInGlue") { 591 Properties |= 1 << SDNPOptInGlue; 592 } else if (PropList[i]->getName() == "SDNPMayStore") { 593 Properties |= 1 << SDNPMayStore; 594 } else if (PropList[i]->getName() == "SDNPMayLoad") { 595 Properties |= 1 << SDNPMayLoad; 596 } else if (PropList[i]->getName() == "SDNPSideEffect") { 597 Properties |= 1 << SDNPSideEffect; 598 } else if (PropList[i]->getName() == "SDNPMemOperand") { 599 Properties |= 1 << SDNPMemOperand; 600 } else if (PropList[i]->getName() == "SDNPVariadic") { 601 Properties |= 1 << SDNPVariadic; 602 } else if (PropList[i]->getName() == "SDNPWantRoot") { 603 Properties |= 1 << SDNPWantRoot; 604 } else if (PropList[i]->getName() == "SDNPWantParent") { 605 Properties |= 1 << SDNPWantParent; 606 } else { 607 PrintFatalError(R->getLoc(), "Unsupported SD Node property '" + 608 PropList[i]->getName() + 609 "' on ComplexPattern '" + R->getName() + 610 "'!"); 611 } 612 } 613 614 //===----------------------------------------------------------------------===// 615 // CodeGenIntrinsic Implementation 616 //===----------------------------------------------------------------------===// 617 618 CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC) { 619 std::vector<Record *> IntrProperties = 620 RC.getAllDerivedDefinitions("IntrinsicProperty"); 621 622 std::vector<Record *> DefaultProperties; 623 for (Record *Rec : IntrProperties) 624 if (Rec->getValueAsBit("IsDefault")) 625 DefaultProperties.push_back(Rec); 626 627 std::vector<Record *> Defs = RC.getAllDerivedDefinitions("Intrinsic"); 628 Intrinsics.reserve(Defs.size()); 629 630 for (unsigned I = 0, e = Defs.size(); I != e; ++I) 631 Intrinsics.push_back(CodeGenIntrinsic(Defs[I], DefaultProperties)); 632 633 llvm::sort(Intrinsics, 634 [](const CodeGenIntrinsic &LHS, const CodeGenIntrinsic &RHS) { 635 return std::tie(LHS.TargetPrefix, LHS.Name) < 636 std::tie(RHS.TargetPrefix, RHS.Name); 637 }); 638 Targets.push_back({"", 0, 0}); 639 for (size_t I = 0, E = Intrinsics.size(); I < E; ++I) 640 if (Intrinsics[I].TargetPrefix != Targets.back().Name) { 641 Targets.back().Count = I - Targets.back().Offset; 642 Targets.push_back({Intrinsics[I].TargetPrefix, I, 0}); 643 } 644 Targets.back().Count = Intrinsics.size() - Targets.back().Offset; 645 } 646 647 CodeGenIntrinsic::CodeGenIntrinsic(Record *R, 648 std::vector<Record *> DefaultProperties) { 649 TheDef = R; 650 std::string DefName = std::string(R->getName()); 651 ArrayRef<SMLoc> DefLoc = R->getLoc(); 652 ModRef = ReadWriteMem; 653 Properties = 0; 654 isOverloaded = false; 655 isCommutative = false; 656 canThrow = false; 657 isNoReturn = false; 658 isNoSync = false; 659 isNoFree = false; 660 isWillReturn = false; 661 isCold = false; 662 isNoDuplicate = false; 663 isConvergent = false; 664 isSpeculatable = false; 665 hasSideEffects = false; 666 667 if (DefName.size() <= 4 || 668 std::string(DefName.begin(), DefName.begin() + 4) != "int_") 669 PrintFatalError(DefLoc, 670 "Intrinsic '" + DefName + "' does not start with 'int_'!"); 671 672 EnumName = std::string(DefName.begin()+4, DefName.end()); 673 674 if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field. 675 GCCBuiltinName = std::string(R->getValueAsString("GCCBuiltinName")); 676 if (R->getValue("MSBuiltinName")) // Ignore a missing MSBuiltinName field. 677 MSBuiltinName = std::string(R->getValueAsString("MSBuiltinName")); 678 679 TargetPrefix = std::string(R->getValueAsString("TargetPrefix")); 680 Name = std::string(R->getValueAsString("LLVMName")); 681 682 if (Name == "") { 683 // If an explicit name isn't specified, derive one from the DefName. 684 Name = "llvm."; 685 686 for (unsigned i = 0, e = EnumName.size(); i != e; ++i) 687 Name += (EnumName[i] == '_') ? '.' : EnumName[i]; 688 } else { 689 // Verify it starts with "llvm.". 690 if (Name.size() <= 5 || 691 std::string(Name.begin(), Name.begin() + 5) != "llvm.") 692 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 693 "'s name does not start with 'llvm.'!"); 694 } 695 696 // If TargetPrefix is specified, make sure that Name starts with 697 // "llvm.<targetprefix>.". 698 if (!TargetPrefix.empty()) { 699 if (Name.size() < 6+TargetPrefix.size() || 700 std::string(Name.begin() + 5, Name.begin() + 6 + TargetPrefix.size()) 701 != (TargetPrefix + ".")) 702 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 703 "' does not start with 'llvm." + 704 TargetPrefix + ".'!"); 705 } 706 707 ListInit *RetTypes = R->getValueAsListInit("RetTypes"); 708 ListInit *ParamTypes = R->getValueAsListInit("ParamTypes"); 709 710 // First collate a list of overloaded types. 711 std::vector<MVT::SimpleValueType> OverloadedVTs; 712 for (ListInit *TypeList : {RetTypes, ParamTypes}) { 713 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 714 Record *TyEl = TypeList->getElementAsRecord(i); 715 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 716 717 if (TyEl->isSubClassOf("LLVMMatchType")) 718 continue; 719 720 MVT::SimpleValueType VT = getValueType(TyEl->getValueAsDef("VT")); 721 if (MVT(VT).isOverloaded()) { 722 OverloadedVTs.push_back(VT); 723 isOverloaded = true; 724 } 725 } 726 } 727 728 // Parse the list of return types. 729 ListInit *TypeList = RetTypes; 730 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 731 Record *TyEl = TypeList->getElementAsRecord(i); 732 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 733 MVT::SimpleValueType VT; 734 if (TyEl->isSubClassOf("LLVMMatchType")) { 735 unsigned MatchTy = TyEl->getValueAsInt("Number"); 736 assert(MatchTy < OverloadedVTs.size() && 737 "Invalid matching number!"); 738 VT = OverloadedVTs[MatchTy]; 739 // It only makes sense to use the extended and truncated vector element 740 // variants with iAny types; otherwise, if the intrinsic is not 741 // overloaded, all the types can be specified directly. 742 assert(((!TyEl->isSubClassOf("LLVMExtendedType") && 743 !TyEl->isSubClassOf("LLVMTruncatedType")) || 744 VT == MVT::iAny || VT == MVT::vAny) && 745 "Expected iAny or vAny type"); 746 } else { 747 VT = getValueType(TyEl->getValueAsDef("VT")); 748 } 749 750 // Reject invalid types. 751 if (VT == MVT::isVoid) 752 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 753 " has void in result type list!"); 754 755 IS.RetVTs.push_back(VT); 756 IS.RetTypeDefs.push_back(TyEl); 757 } 758 759 // Parse the list of parameter types. 760 TypeList = ParamTypes; 761 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 762 Record *TyEl = TypeList->getElementAsRecord(i); 763 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 764 MVT::SimpleValueType VT; 765 if (TyEl->isSubClassOf("LLVMMatchType")) { 766 unsigned MatchTy = TyEl->getValueAsInt("Number"); 767 if (MatchTy >= OverloadedVTs.size()) { 768 PrintError(R->getLoc(), 769 "Parameter #" + Twine(i) + " has out of bounds matching " 770 "number " + Twine(MatchTy)); 771 PrintFatalError(DefLoc, 772 Twine("ParamTypes is ") + TypeList->getAsString()); 773 } 774 VT = OverloadedVTs[MatchTy]; 775 // It only makes sense to use the extended and truncated vector element 776 // variants with iAny types; otherwise, if the intrinsic is not 777 // overloaded, all the types can be specified directly. 778 assert(((!TyEl->isSubClassOf("LLVMExtendedType") && 779 !TyEl->isSubClassOf("LLVMTruncatedType")) || 780 VT == MVT::iAny || VT == MVT::vAny) && 781 "Expected iAny or vAny type"); 782 } else 783 VT = getValueType(TyEl->getValueAsDef("VT")); 784 785 // Reject invalid types. 786 if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/) 787 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 788 " has void in result type list!"); 789 790 IS.ParamVTs.push_back(VT); 791 IS.ParamTypeDefs.push_back(TyEl); 792 } 793 794 // Parse the intrinsic properties. 795 ListInit *PropList = R->getValueAsListInit("IntrProperties"); 796 for (unsigned i = 0, e = PropList->size(); i != e; ++i) { 797 Record *Property = PropList->getElementAsRecord(i); 798 assert(Property->isSubClassOf("IntrinsicProperty") && 799 "Expected a property!"); 800 801 setProperty(Property); 802 } 803 804 // Set default properties to true. 805 setDefaultProperties(R, DefaultProperties); 806 807 // Also record the SDPatternOperator Properties. 808 Properties = parseSDPatternOperatorProperties(R); 809 810 // Sort the argument attributes for later benefit. 811 llvm::sort(ArgumentAttributes); 812 } 813 814 void CodeGenIntrinsic::setDefaultProperties( 815 Record *R, std::vector<Record *> DefaultProperties) { 816 // opt-out of using default attributes. 817 if (R->getValueAsBit("DisableDefaultAttributes")) 818 return; 819 820 for (Record *Rec : DefaultProperties) 821 setProperty(Rec); 822 } 823 824 void CodeGenIntrinsic::setProperty(Record *R) { 825 if (R->getName() == "IntrNoMem") 826 ModRef = NoMem; 827 else if (R->getName() == "IntrReadMem") 828 ModRef = ModRefBehavior(ModRef & ~MR_Mod); 829 else if (R->getName() == "IntrWriteMem") 830 ModRef = ModRefBehavior(ModRef & ~MR_Ref); 831 else if (R->getName() == "IntrArgMemOnly") 832 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem); 833 else if (R->getName() == "IntrInaccessibleMemOnly") 834 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_InaccessibleMem); 835 else if (R->getName() == "IntrInaccessibleMemOrArgMemOnly") 836 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem | 837 MR_InaccessibleMem); 838 else if (R->getName() == "Commutative") 839 isCommutative = true; 840 else if (R->getName() == "Throws") 841 canThrow = true; 842 else if (R->getName() == "IntrNoDuplicate") 843 isNoDuplicate = true; 844 else if (R->getName() == "IntrConvergent") 845 isConvergent = true; 846 else if (R->getName() == "IntrNoReturn") 847 isNoReturn = true; 848 else if (R->getName() == "IntrNoSync") 849 isNoSync = true; 850 else if (R->getName() == "IntrNoFree") 851 isNoFree = true; 852 else if (R->getName() == "IntrWillReturn") 853 isWillReturn = !isNoReturn; 854 else if (R->getName() == "IntrCold") 855 isCold = true; 856 else if (R->getName() == "IntrSpeculatable") 857 isSpeculatable = true; 858 else if (R->getName() == "IntrHasSideEffects") 859 hasSideEffects = true; 860 else if (R->isSubClassOf("NoCapture")) { 861 unsigned ArgNo = R->getValueAsInt("ArgNo"); 862 ArgumentAttributes.emplace_back(ArgNo, NoCapture, 0); 863 } else if (R->isSubClassOf("NoAlias")) { 864 unsigned ArgNo = R->getValueAsInt("ArgNo"); 865 ArgumentAttributes.emplace_back(ArgNo, NoAlias, 0); 866 } else if (R->isSubClassOf("NoUndef")) { 867 unsigned ArgNo = R->getValueAsInt("ArgNo"); 868 ArgumentAttributes.emplace_back(ArgNo, NoUndef, 0); 869 } else if (R->isSubClassOf("Returned")) { 870 unsigned ArgNo = R->getValueAsInt("ArgNo"); 871 ArgumentAttributes.emplace_back(ArgNo, Returned, 0); 872 } else if (R->isSubClassOf("ReadOnly")) { 873 unsigned ArgNo = R->getValueAsInt("ArgNo"); 874 ArgumentAttributes.emplace_back(ArgNo, ReadOnly, 0); 875 } else if (R->isSubClassOf("WriteOnly")) { 876 unsigned ArgNo = R->getValueAsInt("ArgNo"); 877 ArgumentAttributes.emplace_back(ArgNo, WriteOnly, 0); 878 } else if (R->isSubClassOf("ReadNone")) { 879 unsigned ArgNo = R->getValueAsInt("ArgNo"); 880 ArgumentAttributes.emplace_back(ArgNo, ReadNone, 0); 881 } else if (R->isSubClassOf("ImmArg")) { 882 unsigned ArgNo = R->getValueAsInt("ArgNo"); 883 ArgumentAttributes.emplace_back(ArgNo, ImmArg, 0); 884 } else if (R->isSubClassOf("Align")) { 885 unsigned ArgNo = R->getValueAsInt("ArgNo"); 886 uint64_t Align = R->getValueAsInt("Align"); 887 ArgumentAttributes.emplace_back(ArgNo, Alignment, Align); 888 } else 889 llvm_unreachable("Unknown property!"); 890 } 891 892 bool CodeGenIntrinsic::isParamAPointer(unsigned ParamIdx) const { 893 if (ParamIdx >= IS.ParamVTs.size()) 894 return false; 895 MVT ParamType = MVT(IS.ParamVTs[ParamIdx]); 896 return ParamType == MVT::iPTR || ParamType == MVT::iPTRAny; 897 } 898 899 bool CodeGenIntrinsic::isParamImmArg(unsigned ParamIdx) const { 900 // Convert argument index to attribute index starting from `FirstArgIndex`. 901 ArgAttribute Val{ParamIdx + 1, ImmArg, 0}; 902 return std::binary_search(ArgumentAttributes.begin(), 903 ArgumentAttributes.end(), Val); 904 } 905