1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This class wraps target description classes used by the various code 10 // generation TableGen backends. This makes it easier to access the data and 11 // provides a single place that needs to check it for validity. All of these 12 // classes abort on error conditions. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "CodeGenTarget.h" 17 #include "CodeGenInstruction.h" 18 #include "CodeGenIntrinsics.h" 19 #include "CodeGenSchedule.h" 20 #include "llvm/ADT/STLExtras.h" 21 #include "llvm/Support/CommandLine.h" 22 #include "llvm/TableGen/Error.h" 23 #include "llvm/TableGen/Record.h" 24 #include <algorithm> 25 using namespace llvm; 26 27 cl::OptionCategory AsmParserCat("Options for -gen-asm-parser"); 28 cl::OptionCategory AsmWriterCat("Options for -gen-asm-writer"); 29 30 static cl::opt<unsigned> 31 AsmParserNum("asmparsernum", cl::init(0), 32 cl::desc("Make -gen-asm-parser emit assembly parser #N"), 33 cl::cat(AsmParserCat)); 34 35 static cl::opt<unsigned> 36 AsmWriterNum("asmwriternum", cl::init(0), 37 cl::desc("Make -gen-asm-writer emit assembly writer #N"), 38 cl::cat(AsmWriterCat)); 39 40 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen 41 /// record corresponds to. 42 MVT::SimpleValueType llvm::getValueType(Record *Rec) { 43 return (MVT::SimpleValueType)Rec->getValueAsInt("Value"); 44 } 45 46 StringRef llvm::getName(MVT::SimpleValueType T) { 47 switch (T) { 48 case MVT::Other: return "UNKNOWN"; 49 case MVT::iPTR: return "TLI.getPointerTy()"; 50 case MVT::iPTRAny: return "TLI.getPointerTy()"; 51 default: return getEnumName(T); 52 } 53 } 54 55 StringRef llvm::getEnumName(MVT::SimpleValueType T) { 56 switch (T) { 57 case MVT::Other: return "MVT::Other"; 58 case MVT::i1: return "MVT::i1"; 59 case MVT::i8: return "MVT::i8"; 60 case MVT::i16: return "MVT::i16"; 61 case MVT::i32: return "MVT::i32"; 62 case MVT::i64: return "MVT::i64"; 63 case MVT::i128: return "MVT::i128"; 64 case MVT::Any: return "MVT::Any"; 65 case MVT::iAny: return "MVT::iAny"; 66 case MVT::fAny: return "MVT::fAny"; 67 case MVT::vAny: return "MVT::vAny"; 68 case MVT::f16: return "MVT::f16"; 69 case MVT::bf16: return "MVT::bf16"; 70 case MVT::f32: return "MVT::f32"; 71 case MVT::f64: return "MVT::f64"; 72 case MVT::f80: return "MVT::f80"; 73 case MVT::f128: return "MVT::f128"; 74 case MVT::ppcf128: return "MVT::ppcf128"; 75 case MVT::x86mmx: return "MVT::x86mmx"; 76 case MVT::x86amx: return "MVT::x86amx"; 77 case MVT::i64x8: return "MVT::i64x8"; 78 case MVT::Glue: return "MVT::Glue"; 79 case MVT::isVoid: return "MVT::isVoid"; 80 case MVT::v1i1: return "MVT::v1i1"; 81 case MVT::v2i1: return "MVT::v2i1"; 82 case MVT::v4i1: return "MVT::v4i1"; 83 case MVT::v8i1: return "MVT::v8i1"; 84 case MVT::v16i1: return "MVT::v16i1"; 85 case MVT::v32i1: return "MVT::v32i1"; 86 case MVT::v64i1: return "MVT::v64i1"; 87 case MVT::v128i1: return "MVT::v128i1"; 88 case MVT::v256i1: return "MVT::v256i1"; 89 case MVT::v512i1: return "MVT::v512i1"; 90 case MVT::v1024i1: return "MVT::v1024i1"; 91 case MVT::v1i8: return "MVT::v1i8"; 92 case MVT::v2i8: return "MVT::v2i8"; 93 case MVT::v4i8: return "MVT::v4i8"; 94 case MVT::v8i8: return "MVT::v8i8"; 95 case MVT::v16i8: return "MVT::v16i8"; 96 case MVT::v32i8: return "MVT::v32i8"; 97 case MVT::v64i8: return "MVT::v64i8"; 98 case MVT::v128i8: return "MVT::v128i8"; 99 case MVT::v256i8: return "MVT::v256i8"; 100 case MVT::v512i8: return "MVT::v512i8"; 101 case MVT::v1024i8: return "MVT::v1024i8"; 102 case MVT::v1i16: return "MVT::v1i16"; 103 case MVT::v2i16: return "MVT::v2i16"; 104 case MVT::v3i16: return "MVT::v3i16"; 105 case MVT::v4i16: return "MVT::v4i16"; 106 case MVT::v8i16: return "MVT::v8i16"; 107 case MVT::v16i16: return "MVT::v16i16"; 108 case MVT::v32i16: return "MVT::v32i16"; 109 case MVT::v64i16: return "MVT::v64i16"; 110 case MVT::v128i16: return "MVT::v128i16"; 111 case MVT::v256i16: return "MVT::v256i16"; 112 case MVT::v512i16: return "MVT::v512i16"; 113 case MVT::v1i32: return "MVT::v1i32"; 114 case MVT::v2i32: return "MVT::v2i32"; 115 case MVT::v3i32: return "MVT::v3i32"; 116 case MVT::v4i32: return "MVT::v4i32"; 117 case MVT::v5i32: return "MVT::v5i32"; 118 case MVT::v6i32: return "MVT::v6i32"; 119 case MVT::v7i32: return "MVT::v7i32"; 120 case MVT::v8i32: return "MVT::v8i32"; 121 case MVT::v16i32: return "MVT::v16i32"; 122 case MVT::v32i32: return "MVT::v32i32"; 123 case MVT::v64i32: return "MVT::v64i32"; 124 case MVT::v128i32: return "MVT::v128i32"; 125 case MVT::v256i32: return "MVT::v256i32"; 126 case MVT::v512i32: return "MVT::v512i32"; 127 case MVT::v1024i32: return "MVT::v1024i32"; 128 case MVT::v2048i32: return "MVT::v2048i32"; 129 case MVT::v1i64: return "MVT::v1i64"; 130 case MVT::v2i64: return "MVT::v2i64"; 131 case MVT::v3i64: return "MVT::v3i64"; 132 case MVT::v4i64: return "MVT::v4i64"; 133 case MVT::v8i64: return "MVT::v8i64"; 134 case MVT::v16i64: return "MVT::v16i64"; 135 case MVT::v32i64: return "MVT::v32i64"; 136 case MVT::v64i64: return "MVT::v64i64"; 137 case MVT::v128i64: return "MVT::v128i64"; 138 case MVT::v256i64: return "MVT::v256i64"; 139 case MVT::v1i128: return "MVT::v1i128"; 140 case MVT::v1f16: return "MVT::v1f16"; 141 case MVT::v2f16: return "MVT::v2f16"; 142 case MVT::v3f16: return "MVT::v3f16"; 143 case MVT::v4f16: return "MVT::v4f16"; 144 case MVT::v8f16: return "MVT::v8f16"; 145 case MVT::v16f16: return "MVT::v16f16"; 146 case MVT::v32f16: return "MVT::v32f16"; 147 case MVT::v64f16: return "MVT::v64f16"; 148 case MVT::v128f16: return "MVT::v128f16"; 149 case MVT::v256f16: return "MVT::v256f16"; 150 case MVT::v512f16: return "MVT::v512f16"; 151 case MVT::v2bf16: return "MVT::v2bf16"; 152 case MVT::v3bf16: return "MVT::v3bf16"; 153 case MVT::v4bf16: return "MVT::v4bf16"; 154 case MVT::v8bf16: return "MVT::v8bf16"; 155 case MVT::v16bf16: return "MVT::v16bf16"; 156 case MVT::v32bf16: return "MVT::v32bf16"; 157 case MVT::v64bf16: return "MVT::v64bf16"; 158 case MVT::v128bf16: return "MVT::v128bf16"; 159 case MVT::v1f32: return "MVT::v1f32"; 160 case MVT::v2f32: return "MVT::v2f32"; 161 case MVT::v3f32: return "MVT::v3f32"; 162 case MVT::v4f32: return "MVT::v4f32"; 163 case MVT::v5f32: return "MVT::v5f32"; 164 case MVT::v6f32: return "MVT::v6f32"; 165 case MVT::v7f32: return "MVT::v7f32"; 166 case MVT::v8f32: return "MVT::v8f32"; 167 case MVT::v16f32: return "MVT::v16f32"; 168 case MVT::v32f32: return "MVT::v32f32"; 169 case MVT::v64f32: return "MVT::v64f32"; 170 case MVT::v128f32: return "MVT::v128f32"; 171 case MVT::v256f32: return "MVT::v256f32"; 172 case MVT::v512f32: return "MVT::v512f32"; 173 case MVT::v1024f32: return "MVT::v1024f32"; 174 case MVT::v2048f32: return "MVT::v2048f32"; 175 case MVT::v1f64: return "MVT::v1f64"; 176 case MVT::v2f64: return "MVT::v2f64"; 177 case MVT::v3f64: return "MVT::v3f64"; 178 case MVT::v4f64: return "MVT::v4f64"; 179 case MVT::v8f64: return "MVT::v8f64"; 180 case MVT::v16f64: return "MVT::v16f64"; 181 case MVT::v32f64: return "MVT::v32f64"; 182 case MVT::v64f64: return "MVT::v64f64"; 183 case MVT::v128f64: return "MVT::v128f64"; 184 case MVT::v256f64: return "MVT::v256f64"; 185 case MVT::nxv1i1: return "MVT::nxv1i1"; 186 case MVT::nxv2i1: return "MVT::nxv2i1"; 187 case MVT::nxv4i1: return "MVT::nxv4i1"; 188 case MVT::nxv8i1: return "MVT::nxv8i1"; 189 case MVT::nxv16i1: return "MVT::nxv16i1"; 190 case MVT::nxv32i1: return "MVT::nxv32i1"; 191 case MVT::nxv64i1: return "MVT::nxv64i1"; 192 case MVT::nxv1i8: return "MVT::nxv1i8"; 193 case MVT::nxv2i8: return "MVT::nxv2i8"; 194 case MVT::nxv4i8: return "MVT::nxv4i8"; 195 case MVT::nxv8i8: return "MVT::nxv8i8"; 196 case MVT::nxv16i8: return "MVT::nxv16i8"; 197 case MVT::nxv32i8: return "MVT::nxv32i8"; 198 case MVT::nxv64i8: return "MVT::nxv64i8"; 199 case MVT::nxv1i16: return "MVT::nxv1i16"; 200 case MVT::nxv2i16: return "MVT::nxv2i16"; 201 case MVT::nxv4i16: return "MVT::nxv4i16"; 202 case MVT::nxv8i16: return "MVT::nxv8i16"; 203 case MVT::nxv16i16: return "MVT::nxv16i16"; 204 case MVT::nxv32i16: return "MVT::nxv32i16"; 205 case MVT::nxv1i32: return "MVT::nxv1i32"; 206 case MVT::nxv2i32: return "MVT::nxv2i32"; 207 case MVT::nxv4i32: return "MVT::nxv4i32"; 208 case MVT::nxv8i32: return "MVT::nxv8i32"; 209 case MVT::nxv16i32: return "MVT::nxv16i32"; 210 case MVT::nxv32i32: return "MVT::nxv32i32"; 211 case MVT::nxv1i64: return "MVT::nxv1i64"; 212 case MVT::nxv2i64: return "MVT::nxv2i64"; 213 case MVT::nxv4i64: return "MVT::nxv4i64"; 214 case MVT::nxv8i64: return "MVT::nxv8i64"; 215 case MVT::nxv16i64: return "MVT::nxv16i64"; 216 case MVT::nxv32i64: return "MVT::nxv32i64"; 217 case MVT::nxv1f16: return "MVT::nxv1f16"; 218 case MVT::nxv2f16: return "MVT::nxv2f16"; 219 case MVT::nxv4f16: return "MVT::nxv4f16"; 220 case MVT::nxv8f16: return "MVT::nxv8f16"; 221 case MVT::nxv16f16: return "MVT::nxv16f16"; 222 case MVT::nxv32f16: return "MVT::nxv32f16"; 223 case MVT::nxv1bf16: return "MVT::nxv1bf16"; 224 case MVT::nxv2bf16: return "MVT::nxv2bf16"; 225 case MVT::nxv4bf16: return "MVT::nxv4bf16"; 226 case MVT::nxv8bf16: return "MVT::nxv8bf16"; 227 case MVT::nxv1f32: return "MVT::nxv1f32"; 228 case MVT::nxv2f32: return "MVT::nxv2f32"; 229 case MVT::nxv4f32: return "MVT::nxv4f32"; 230 case MVT::nxv8f32: return "MVT::nxv8f32"; 231 case MVT::nxv16f32: return "MVT::nxv16f32"; 232 case MVT::nxv1f64: return "MVT::nxv1f64"; 233 case MVT::nxv2f64: return "MVT::nxv2f64"; 234 case MVT::nxv4f64: return "MVT::nxv4f64"; 235 case MVT::nxv8f64: return "MVT::nxv8f64"; 236 case MVT::token: return "MVT::token"; 237 case MVT::Metadata: return "MVT::Metadata"; 238 case MVT::iPTR: return "MVT::iPTR"; 239 case MVT::iPTRAny: return "MVT::iPTRAny"; 240 case MVT::Untyped: return "MVT::Untyped"; 241 case MVT::funcref: return "MVT::funcref"; 242 case MVT::externref: return "MVT::externref"; 243 default: llvm_unreachable("ILLEGAL VALUE TYPE!"); 244 } 245 } 246 247 /// getQualifiedName - Return the name of the specified record, with a 248 /// namespace qualifier if the record contains one. 249 /// 250 std::string llvm::getQualifiedName(const Record *R) { 251 std::string Namespace; 252 if (R->getValue("Namespace")) 253 Namespace = std::string(R->getValueAsString("Namespace")); 254 if (Namespace.empty()) 255 return std::string(R->getName()); 256 return Namespace + "::" + R->getName().str(); 257 } 258 259 260 /// getTarget - Return the current instance of the Target class. 261 /// 262 CodeGenTarget::CodeGenTarget(RecordKeeper &records) 263 : Records(records), CGH(records) { 264 std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target"); 265 if (Targets.size() == 0) 266 PrintFatalError("No 'Target' subclasses defined!"); 267 if (Targets.size() != 1) 268 PrintFatalError("Multiple subclasses of Target defined!"); 269 TargetRec = Targets[0]; 270 } 271 272 CodeGenTarget::~CodeGenTarget() { 273 } 274 275 StringRef CodeGenTarget::getName() const { return TargetRec->getName(); } 276 277 /// getInstNamespace - Find and return the target machine's instruction 278 /// namespace. The namespace is cached because it is requested multiple times. 279 StringRef CodeGenTarget::getInstNamespace() const { 280 if (InstNamespace.empty()) { 281 for (const CodeGenInstruction *Inst : getInstructionsByEnumValue()) { 282 // We are not interested in the "TargetOpcode" namespace. 283 if (Inst->Namespace != "TargetOpcode") { 284 InstNamespace = Inst->Namespace; 285 break; 286 } 287 } 288 } 289 290 return InstNamespace; 291 } 292 293 StringRef CodeGenTarget::getRegNamespace() const { 294 auto &RegClasses = RegBank->getRegClasses(); 295 return RegClasses.size() > 0 ? RegClasses.front().Namespace : ""; 296 } 297 298 Record *CodeGenTarget::getInstructionSet() const { 299 return TargetRec->getValueAsDef("InstructionSet"); 300 } 301 302 bool CodeGenTarget::getAllowRegisterRenaming() const { 303 return TargetRec->getValueAsInt("AllowRegisterRenaming"); 304 } 305 306 /// getAsmParser - Return the AssemblyParser definition for this target. 307 /// 308 Record *CodeGenTarget::getAsmParser() const { 309 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers"); 310 if (AsmParserNum >= LI.size()) 311 PrintFatalError("Target does not have an AsmParser #" + 312 Twine(AsmParserNum) + "!"); 313 return LI[AsmParserNum]; 314 } 315 316 /// getAsmParserVariant - Return the AssemblyParserVariant definition for 317 /// this target. 318 /// 319 Record *CodeGenTarget::getAsmParserVariant(unsigned i) const { 320 std::vector<Record*> LI = 321 TargetRec->getValueAsListOfDefs("AssemblyParserVariants"); 322 if (i >= LI.size()) 323 PrintFatalError("Target does not have an AsmParserVariant #" + Twine(i) + 324 "!"); 325 return LI[i]; 326 } 327 328 /// getAsmParserVariantCount - Return the AssemblyParserVariant definition 329 /// available for this target. 330 /// 331 unsigned CodeGenTarget::getAsmParserVariantCount() const { 332 std::vector<Record*> LI = 333 TargetRec->getValueAsListOfDefs("AssemblyParserVariants"); 334 return LI.size(); 335 } 336 337 /// getAsmWriter - Return the AssemblyWriter definition for this target. 338 /// 339 Record *CodeGenTarget::getAsmWriter() const { 340 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters"); 341 if (AsmWriterNum >= LI.size()) 342 PrintFatalError("Target does not have an AsmWriter #" + 343 Twine(AsmWriterNum) + "!"); 344 return LI[AsmWriterNum]; 345 } 346 347 CodeGenRegBank &CodeGenTarget::getRegBank() const { 348 if (!RegBank) 349 RegBank = std::make_unique<CodeGenRegBank>(Records, getHwModes()); 350 return *RegBank; 351 } 352 353 Optional<CodeGenRegisterClass *> 354 CodeGenTarget::getSuperRegForSubReg(const ValueTypeByHwMode &ValueTy, 355 CodeGenRegBank &RegBank, 356 const CodeGenSubRegIndex *SubIdx, 357 bool MustBeAllocatable) const { 358 std::vector<CodeGenRegisterClass *> Candidates; 359 auto &RegClasses = RegBank.getRegClasses(); 360 361 // Try to find a register class which supports ValueTy, and also contains 362 // SubIdx. 363 for (CodeGenRegisterClass &RC : RegClasses) { 364 // Is there a subclass of this class which contains this subregister index? 365 CodeGenRegisterClass *SubClassWithSubReg = RC.getSubClassWithSubReg(SubIdx); 366 if (!SubClassWithSubReg) 367 continue; 368 369 // We have a class. Check if it supports this value type. 370 if (!llvm::is_contained(SubClassWithSubReg->VTs, ValueTy)) 371 continue; 372 373 // If necessary, check that it is allocatable. 374 if (MustBeAllocatable && !SubClassWithSubReg->Allocatable) 375 continue; 376 377 // We have a register class which supports both the value type and 378 // subregister index. Remember it. 379 Candidates.push_back(SubClassWithSubReg); 380 } 381 382 // If we didn't find anything, we're done. 383 if (Candidates.empty()) 384 return None; 385 386 // Find and return the largest of our candidate classes. 387 llvm::stable_sort(Candidates, [&](const CodeGenRegisterClass *A, 388 const CodeGenRegisterClass *B) { 389 if (A->getMembers().size() > B->getMembers().size()) 390 return true; 391 392 if (A->getMembers().size() < B->getMembers().size()) 393 return false; 394 395 // Order by name as a tie-breaker. 396 return StringRef(A->getName()) < B->getName(); 397 }); 398 399 return Candidates[0]; 400 } 401 402 void CodeGenTarget::ReadRegAltNameIndices() const { 403 RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex"); 404 llvm::sort(RegAltNameIndices, LessRecord()); 405 } 406 407 /// getRegisterByName - If there is a register with the specific AsmName, 408 /// return it. 409 const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const { 410 return getRegBank().getRegistersByName().lookup(Name); 411 } 412 413 std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R) 414 const { 415 const CodeGenRegister *Reg = getRegBank().getReg(R); 416 std::vector<ValueTypeByHwMode> Result; 417 for (const auto &RC : getRegBank().getRegClasses()) { 418 if (RC.contains(Reg)) { 419 ArrayRef<ValueTypeByHwMode> InVTs = RC.getValueTypes(); 420 llvm::append_range(Result, InVTs); 421 } 422 } 423 424 // Remove duplicates. 425 llvm::sort(Result); 426 Result.erase(std::unique(Result.begin(), Result.end()), Result.end()); 427 return Result; 428 } 429 430 431 void CodeGenTarget::ReadLegalValueTypes() const { 432 for (const auto &RC : getRegBank().getRegClasses()) 433 llvm::append_range(LegalValueTypes, RC.VTs); 434 435 // Remove duplicates. 436 llvm::sort(LegalValueTypes); 437 LegalValueTypes.erase(std::unique(LegalValueTypes.begin(), 438 LegalValueTypes.end()), 439 LegalValueTypes.end()); 440 } 441 442 CodeGenSchedModels &CodeGenTarget::getSchedModels() const { 443 if (!SchedModels) 444 SchedModels = std::make_unique<CodeGenSchedModels>(Records, *this); 445 return *SchedModels; 446 } 447 448 void CodeGenTarget::ReadInstructions() const { 449 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction"); 450 if (Insts.size() <= 2) 451 PrintFatalError("No 'Instruction' subclasses defined!"); 452 453 // Parse the instructions defined in the .td file. 454 for (unsigned i = 0, e = Insts.size(); i != e; ++i) 455 Instructions[Insts[i]] = std::make_unique<CodeGenInstruction>(Insts[i]); 456 } 457 458 static const CodeGenInstruction * 459 GetInstByName(const char *Name, 460 const DenseMap<const Record*, 461 std::unique_ptr<CodeGenInstruction>> &Insts, 462 RecordKeeper &Records) { 463 const Record *Rec = Records.getDef(Name); 464 465 const auto I = Insts.find(Rec); 466 if (!Rec || I == Insts.end()) 467 PrintFatalError(Twine("Could not find '") + Name + "' instruction!"); 468 return I->second.get(); 469 } 470 471 static const char *const FixedInstrs[] = { 472 #define HANDLE_TARGET_OPCODE(OPC) #OPC, 473 #include "llvm/Support/TargetOpcodes.def" 474 nullptr}; 475 476 unsigned CodeGenTarget::getNumFixedInstructions() { 477 return array_lengthof(FixedInstrs) - 1; 478 } 479 480 /// Return all of the instructions defined by the target, ordered by 481 /// their enum value. 482 void CodeGenTarget::ComputeInstrsByEnum() const { 483 const auto &Insts = getInstructions(); 484 for (const char *const *p = FixedInstrs; *p; ++p) { 485 const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records); 486 assert(Instr && "Missing target independent instruction"); 487 assert(Instr->Namespace == "TargetOpcode" && "Bad namespace"); 488 InstrsByEnum.push_back(Instr); 489 } 490 unsigned EndOfPredefines = InstrsByEnum.size(); 491 assert(EndOfPredefines == getNumFixedInstructions() && 492 "Missing generic opcode"); 493 494 for (const auto &I : Insts) { 495 const CodeGenInstruction *CGI = I.second.get(); 496 if (CGI->Namespace != "TargetOpcode") { 497 InstrsByEnum.push_back(CGI); 498 if (CGI->TheDef->getValueAsBit("isPseudo")) 499 ++NumPseudoInstructions; 500 } 501 } 502 503 assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr"); 504 505 // All of the instructions are now in random order based on the map iteration. 506 llvm::sort( 507 InstrsByEnum.begin() + EndOfPredefines, InstrsByEnum.end(), 508 [](const CodeGenInstruction *Rec1, const CodeGenInstruction *Rec2) { 509 const auto &D1 = *Rec1->TheDef; 510 const auto &D2 = *Rec2->TheDef; 511 return std::make_tuple(!D1.getValueAsBit("isPseudo"), D1.getName()) < 512 std::make_tuple(!D2.getValueAsBit("isPseudo"), D2.getName()); 513 }); 514 } 515 516 517 /// isLittleEndianEncoding - Return whether this target encodes its instruction 518 /// in little-endian format, i.e. bits laid out in the order [0..n] 519 /// 520 bool CodeGenTarget::isLittleEndianEncoding() const { 521 return getInstructionSet()->getValueAsBit("isLittleEndianEncoding"); 522 } 523 524 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit 525 /// encodings, reverse the bit order of all instructions. 526 void CodeGenTarget::reverseBitsForLittleEndianEncoding() { 527 if (!isLittleEndianEncoding()) 528 return; 529 530 std::vector<Record *> Insts = 531 Records.getAllDerivedDefinitions("InstructionEncoding"); 532 for (Record *R : Insts) { 533 if (R->getValueAsString("Namespace") == "TargetOpcode" || 534 R->getValueAsBit("isPseudo")) 535 continue; 536 537 BitsInit *BI = R->getValueAsBitsInit("Inst"); 538 539 unsigned numBits = BI->getNumBits(); 540 541 SmallVector<Init *, 16> NewBits(numBits); 542 543 for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) { 544 unsigned bitSwapIdx = numBits - bit - 1; 545 Init *OrigBit = BI->getBit(bit); 546 Init *BitSwap = BI->getBit(bitSwapIdx); 547 NewBits[bit] = BitSwap; 548 NewBits[bitSwapIdx] = OrigBit; 549 } 550 if (numBits % 2) { 551 unsigned middle = (numBits + 1) / 2; 552 NewBits[middle] = BI->getBit(middle); 553 } 554 555 BitsInit *NewBI = BitsInit::get(NewBits); 556 557 // Update the bits in reversed order so that emitInstrOpBits will get the 558 // correct endianness. 559 R->getValue("Inst")->setValue(NewBI); 560 } 561 } 562 563 /// guessInstructionProperties - Return true if it's OK to guess instruction 564 /// properties instead of raising an error. 565 /// 566 /// This is configurable as a temporary migration aid. It will eventually be 567 /// permanently false. 568 bool CodeGenTarget::guessInstructionProperties() const { 569 return getInstructionSet()->getValueAsBit("guessInstructionProperties"); 570 } 571 572 //===----------------------------------------------------------------------===// 573 // ComplexPattern implementation 574 // 575 ComplexPattern::ComplexPattern(Record *R) { 576 Ty = R->getValueAsDef("Ty"); 577 NumOperands = R->getValueAsInt("NumOperands"); 578 SelectFunc = std::string(R->getValueAsString("SelectFunc")); 579 RootNodes = R->getValueAsListOfDefs("RootNodes"); 580 581 // FIXME: This is a hack to statically increase the priority of patterns which 582 // maps a sub-dag to a complex pattern. e.g. favors LEA over ADD. To get best 583 // possible pattern match we'll need to dynamically calculate the complexity 584 // of all patterns a dag can potentially map to. 585 int64_t RawComplexity = R->getValueAsInt("Complexity"); 586 if (RawComplexity == -1) 587 Complexity = NumOperands * 3; 588 else 589 Complexity = RawComplexity; 590 591 // FIXME: Why is this different from parseSDPatternOperatorProperties? 592 // Parse the properties. 593 Properties = 0; 594 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties"); 595 for (unsigned i = 0, e = PropList.size(); i != e; ++i) 596 if (PropList[i]->getName() == "SDNPHasChain") { 597 Properties |= 1 << SDNPHasChain; 598 } else if (PropList[i]->getName() == "SDNPOptInGlue") { 599 Properties |= 1 << SDNPOptInGlue; 600 } else if (PropList[i]->getName() == "SDNPMayStore") { 601 Properties |= 1 << SDNPMayStore; 602 } else if (PropList[i]->getName() == "SDNPMayLoad") { 603 Properties |= 1 << SDNPMayLoad; 604 } else if (PropList[i]->getName() == "SDNPSideEffect") { 605 Properties |= 1 << SDNPSideEffect; 606 } else if (PropList[i]->getName() == "SDNPMemOperand") { 607 Properties |= 1 << SDNPMemOperand; 608 } else if (PropList[i]->getName() == "SDNPVariadic") { 609 Properties |= 1 << SDNPVariadic; 610 } else if (PropList[i]->getName() == "SDNPWantRoot") { 611 Properties |= 1 << SDNPWantRoot; 612 } else if (PropList[i]->getName() == "SDNPWantParent") { 613 Properties |= 1 << SDNPWantParent; 614 } else { 615 PrintFatalError(R->getLoc(), "Unsupported SD Node property '" + 616 PropList[i]->getName() + 617 "' on ComplexPattern '" + R->getName() + 618 "'!"); 619 } 620 } 621 622 //===----------------------------------------------------------------------===// 623 // CodeGenIntrinsic Implementation 624 //===----------------------------------------------------------------------===// 625 626 CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC) { 627 std::vector<Record *> IntrProperties = 628 RC.getAllDerivedDefinitions("IntrinsicProperty"); 629 630 std::vector<Record *> DefaultProperties; 631 for (Record *Rec : IntrProperties) 632 if (Rec->getValueAsBit("IsDefault")) 633 DefaultProperties.push_back(Rec); 634 635 std::vector<Record *> Defs = RC.getAllDerivedDefinitions("Intrinsic"); 636 Intrinsics.reserve(Defs.size()); 637 638 for (unsigned I = 0, e = Defs.size(); I != e; ++I) 639 Intrinsics.push_back(CodeGenIntrinsic(Defs[I], DefaultProperties)); 640 641 llvm::sort(Intrinsics, 642 [](const CodeGenIntrinsic &LHS, const CodeGenIntrinsic &RHS) { 643 return std::tie(LHS.TargetPrefix, LHS.Name) < 644 std::tie(RHS.TargetPrefix, RHS.Name); 645 }); 646 Targets.push_back({"", 0, 0}); 647 for (size_t I = 0, E = Intrinsics.size(); I < E; ++I) 648 if (Intrinsics[I].TargetPrefix != Targets.back().Name) { 649 Targets.back().Count = I - Targets.back().Offset; 650 Targets.push_back({Intrinsics[I].TargetPrefix, I, 0}); 651 } 652 Targets.back().Count = Intrinsics.size() - Targets.back().Offset; 653 } 654 655 CodeGenIntrinsic::CodeGenIntrinsic(Record *R, 656 std::vector<Record *> DefaultProperties) { 657 TheDef = R; 658 std::string DefName = std::string(R->getName()); 659 ArrayRef<SMLoc> DefLoc = R->getLoc(); 660 ModRef = ReadWriteMem; 661 Properties = 0; 662 isOverloaded = false; 663 isCommutative = false; 664 canThrow = false; 665 isNoReturn = false; 666 isNoSync = false; 667 isNoFree = false; 668 isWillReturn = false; 669 isCold = false; 670 isNoDuplicate = false; 671 isNoMerge = false; 672 isConvergent = false; 673 isSpeculatable = false; 674 hasSideEffects = false; 675 676 if (DefName.size() <= 4 || DefName.substr(0, 4) != "int_") 677 PrintFatalError(DefLoc, 678 "Intrinsic '" + DefName + "' does not start with 'int_'!"); 679 680 EnumName = DefName.substr(4); 681 682 if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field. 683 GCCBuiltinName = std::string(R->getValueAsString("GCCBuiltinName")); 684 if (R->getValue("MSBuiltinName")) // Ignore a missing MSBuiltinName field. 685 MSBuiltinName = std::string(R->getValueAsString("MSBuiltinName")); 686 687 TargetPrefix = std::string(R->getValueAsString("TargetPrefix")); 688 Name = std::string(R->getValueAsString("LLVMName")); 689 690 if (Name == "") { 691 // If an explicit name isn't specified, derive one from the DefName. 692 Name = "llvm."; 693 694 for (unsigned i = 0, e = EnumName.size(); i != e; ++i) 695 Name += (EnumName[i] == '_') ? '.' : EnumName[i]; 696 } else { 697 // Verify it starts with "llvm.". 698 if (Name.size() <= 5 || Name.substr(0, 5) != "llvm.") 699 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 700 "'s name does not start with 'llvm.'!"); 701 } 702 703 // If TargetPrefix is specified, make sure that Name starts with 704 // "llvm.<targetprefix>.". 705 if (!TargetPrefix.empty()) { 706 if (Name.size() < 6+TargetPrefix.size() || 707 Name.substr(5, 1 + TargetPrefix.size()) != (TargetPrefix + ".")) 708 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 709 "' does not start with 'llvm." + 710 TargetPrefix + ".'!"); 711 } 712 713 ListInit *RetTypes = R->getValueAsListInit("RetTypes"); 714 ListInit *ParamTypes = R->getValueAsListInit("ParamTypes"); 715 716 // First collate a list of overloaded types. 717 std::vector<MVT::SimpleValueType> OverloadedVTs; 718 for (ListInit *TypeList : {RetTypes, ParamTypes}) { 719 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 720 Record *TyEl = TypeList->getElementAsRecord(i); 721 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 722 723 if (TyEl->isSubClassOf("LLVMMatchType")) 724 continue; 725 726 MVT::SimpleValueType VT = getValueType(TyEl->getValueAsDef("VT")); 727 if (MVT(VT).isOverloaded()) { 728 OverloadedVTs.push_back(VT); 729 isOverloaded = true; 730 } 731 } 732 } 733 734 // Parse the list of return types. 735 ListInit *TypeList = RetTypes; 736 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 737 Record *TyEl = TypeList->getElementAsRecord(i); 738 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 739 MVT::SimpleValueType VT; 740 if (TyEl->isSubClassOf("LLVMMatchType")) { 741 unsigned MatchTy = TyEl->getValueAsInt("Number"); 742 assert(MatchTy < OverloadedVTs.size() && 743 "Invalid matching number!"); 744 VT = OverloadedVTs[MatchTy]; 745 // It only makes sense to use the extended and truncated vector element 746 // variants with iAny types; otherwise, if the intrinsic is not 747 // overloaded, all the types can be specified directly. 748 assert(((!TyEl->isSubClassOf("LLVMExtendedType") && 749 !TyEl->isSubClassOf("LLVMTruncatedType")) || 750 VT == MVT::iAny || VT == MVT::vAny) && 751 "Expected iAny or vAny type"); 752 } else { 753 VT = getValueType(TyEl->getValueAsDef("VT")); 754 } 755 756 // Reject invalid types. 757 if (VT == MVT::isVoid) 758 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 759 " has void in result type list!"); 760 761 IS.RetVTs.push_back(VT); 762 IS.RetTypeDefs.push_back(TyEl); 763 } 764 765 // Parse the list of parameter types. 766 TypeList = ParamTypes; 767 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 768 Record *TyEl = TypeList->getElementAsRecord(i); 769 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 770 MVT::SimpleValueType VT; 771 if (TyEl->isSubClassOf("LLVMMatchType")) { 772 unsigned MatchTy = TyEl->getValueAsInt("Number"); 773 if (MatchTy >= OverloadedVTs.size()) { 774 PrintError(R->getLoc(), 775 "Parameter #" + Twine(i) + " has out of bounds matching " 776 "number " + Twine(MatchTy)); 777 PrintFatalError(DefLoc, 778 Twine("ParamTypes is ") + TypeList->getAsString()); 779 } 780 VT = OverloadedVTs[MatchTy]; 781 // It only makes sense to use the extended and truncated vector element 782 // variants with iAny types; otherwise, if the intrinsic is not 783 // overloaded, all the types can be specified directly. 784 assert(((!TyEl->isSubClassOf("LLVMExtendedType") && 785 !TyEl->isSubClassOf("LLVMTruncatedType")) || 786 VT == MVT::iAny || VT == MVT::vAny) && 787 "Expected iAny or vAny type"); 788 } else 789 VT = getValueType(TyEl->getValueAsDef("VT")); 790 791 // Reject invalid types. 792 if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/) 793 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 794 " has void in result type list!"); 795 796 IS.ParamVTs.push_back(VT); 797 IS.ParamTypeDefs.push_back(TyEl); 798 } 799 800 // Parse the intrinsic properties. 801 ListInit *PropList = R->getValueAsListInit("IntrProperties"); 802 for (unsigned i = 0, e = PropList->size(); i != e; ++i) { 803 Record *Property = PropList->getElementAsRecord(i); 804 assert(Property->isSubClassOf("IntrinsicProperty") && 805 "Expected a property!"); 806 807 setProperty(Property); 808 } 809 810 // Set default properties to true. 811 setDefaultProperties(R, DefaultProperties); 812 813 // Also record the SDPatternOperator Properties. 814 Properties = parseSDPatternOperatorProperties(R); 815 816 // Sort the argument attributes for later benefit. 817 llvm::sort(ArgumentAttributes); 818 } 819 820 void CodeGenIntrinsic::setDefaultProperties( 821 Record *R, std::vector<Record *> DefaultProperties) { 822 // opt-out of using default attributes. 823 if (R->getValueAsBit("DisableDefaultAttributes")) 824 return; 825 826 for (Record *Rec : DefaultProperties) 827 setProperty(Rec); 828 } 829 830 void CodeGenIntrinsic::setProperty(Record *R) { 831 if (R->getName() == "IntrNoMem") 832 ModRef = NoMem; 833 else if (R->getName() == "IntrReadMem") { 834 if (!(ModRef & MR_Ref)) 835 PrintFatalError(TheDef->getLoc(), 836 Twine("IntrReadMem cannot be used after IntrNoMem or " 837 "IntrWriteMem. Default is ReadWrite")); 838 ModRef = ModRefBehavior(ModRef & ~MR_Mod); 839 } else if (R->getName() == "IntrWriteMem") { 840 if (!(ModRef & MR_Mod)) 841 PrintFatalError(TheDef->getLoc(), 842 Twine("IntrWriteMem cannot be used after IntrNoMem or " 843 "IntrReadMem. Default is ReadWrite")); 844 ModRef = ModRefBehavior(ModRef & ~MR_Ref); 845 } else if (R->getName() == "IntrArgMemOnly") 846 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem); 847 else if (R->getName() == "IntrInaccessibleMemOnly") 848 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_InaccessibleMem); 849 else if (R->getName() == "IntrInaccessibleMemOrArgMemOnly") 850 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem | 851 MR_InaccessibleMem); 852 else if (R->getName() == "Commutative") 853 isCommutative = true; 854 else if (R->getName() == "Throws") 855 canThrow = true; 856 else if (R->getName() == "IntrNoDuplicate") 857 isNoDuplicate = true; 858 else if (R->getName() == "IntrNoMerge") 859 isNoMerge = true; 860 else if (R->getName() == "IntrConvergent") 861 isConvergent = true; 862 else if (R->getName() == "IntrNoReturn") 863 isNoReturn = true; 864 else if (R->getName() == "IntrNoSync") 865 isNoSync = true; 866 else if (R->getName() == "IntrNoFree") 867 isNoFree = true; 868 else if (R->getName() == "IntrWillReturn") 869 isWillReturn = !isNoReturn; 870 else if (R->getName() == "IntrCold") 871 isCold = true; 872 else if (R->getName() == "IntrSpeculatable") 873 isSpeculatable = true; 874 else if (R->getName() == "IntrHasSideEffects") 875 hasSideEffects = true; 876 else if (R->isSubClassOf("NoCapture")) { 877 unsigned ArgNo = R->getValueAsInt("ArgNo"); 878 ArgumentAttributes.emplace_back(ArgNo, NoCapture, 0); 879 } else if (R->isSubClassOf("NoAlias")) { 880 unsigned ArgNo = R->getValueAsInt("ArgNo"); 881 ArgumentAttributes.emplace_back(ArgNo, NoAlias, 0); 882 } else if (R->isSubClassOf("NoUndef")) { 883 unsigned ArgNo = R->getValueAsInt("ArgNo"); 884 ArgumentAttributes.emplace_back(ArgNo, NoUndef, 0); 885 } else if (R->isSubClassOf("Returned")) { 886 unsigned ArgNo = R->getValueAsInt("ArgNo"); 887 ArgumentAttributes.emplace_back(ArgNo, Returned, 0); 888 } else if (R->isSubClassOf("ReadOnly")) { 889 unsigned ArgNo = R->getValueAsInt("ArgNo"); 890 ArgumentAttributes.emplace_back(ArgNo, ReadOnly, 0); 891 } else if (R->isSubClassOf("WriteOnly")) { 892 unsigned ArgNo = R->getValueAsInt("ArgNo"); 893 ArgumentAttributes.emplace_back(ArgNo, WriteOnly, 0); 894 } else if (R->isSubClassOf("ReadNone")) { 895 unsigned ArgNo = R->getValueAsInt("ArgNo"); 896 ArgumentAttributes.emplace_back(ArgNo, ReadNone, 0); 897 } else if (R->isSubClassOf("ImmArg")) { 898 unsigned ArgNo = R->getValueAsInt("ArgNo"); 899 ArgumentAttributes.emplace_back(ArgNo, ImmArg, 0); 900 } else if (R->isSubClassOf("Align")) { 901 unsigned ArgNo = R->getValueAsInt("ArgNo"); 902 uint64_t Align = R->getValueAsInt("Align"); 903 ArgumentAttributes.emplace_back(ArgNo, Alignment, Align); 904 } else 905 llvm_unreachable("Unknown property!"); 906 } 907 908 bool CodeGenIntrinsic::isParamAPointer(unsigned ParamIdx) const { 909 if (ParamIdx >= IS.ParamVTs.size()) 910 return false; 911 MVT ParamType = MVT(IS.ParamVTs[ParamIdx]); 912 return ParamType == MVT::iPTR || ParamType == MVT::iPTRAny; 913 } 914 915 bool CodeGenIntrinsic::isParamImmArg(unsigned ParamIdx) const { 916 // Convert argument index to attribute index starting from `FirstArgIndex`. 917 ArgAttribute Val{ParamIdx + 1, ImmArg, 0}; 918 return std::binary_search(ArgumentAttributes.begin(), 919 ArgumentAttributes.end(), Val); 920 } 921