1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This class wraps target description classes used by the various code 10 // generation TableGen backends. This makes it easier to access the data and 11 // provides a single place that needs to check it for validity. All of these 12 // classes abort on error conditions. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "CodeGenTarget.h" 17 #include "CodeGenDAGPatterns.h" 18 #include "CodeGenIntrinsics.h" 19 #include "CodeGenSchedule.h" 20 #include "llvm/ADT/STLExtras.h" 21 #include "llvm/ADT/StringExtras.h" 22 #include "llvm/Support/CommandLine.h" 23 #include "llvm/Support/Timer.h" 24 #include "llvm/TableGen/Error.h" 25 #include "llvm/TableGen/Record.h" 26 #include "llvm/TableGen/TableGenBackend.h" 27 #include <algorithm> 28 using namespace llvm; 29 30 cl::OptionCategory AsmParserCat("Options for -gen-asm-parser"); 31 cl::OptionCategory AsmWriterCat("Options for -gen-asm-writer"); 32 33 static cl::opt<unsigned> 34 AsmParserNum("asmparsernum", cl::init(0), 35 cl::desc("Make -gen-asm-parser emit assembly parser #N"), 36 cl::cat(AsmParserCat)); 37 38 static cl::opt<unsigned> 39 AsmWriterNum("asmwriternum", cl::init(0), 40 cl::desc("Make -gen-asm-writer emit assembly writer #N"), 41 cl::cat(AsmWriterCat)); 42 43 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen 44 /// record corresponds to. 45 MVT::SimpleValueType llvm::getValueType(Record *Rec) { 46 return (MVT::SimpleValueType)Rec->getValueAsInt("Value"); 47 } 48 49 StringRef llvm::getName(MVT::SimpleValueType T) { 50 switch (T) { 51 case MVT::Other: return "UNKNOWN"; 52 case MVT::iPTR: return "TLI.getPointerTy()"; 53 case MVT::iPTRAny: return "TLI.getPointerTy()"; 54 default: return getEnumName(T); 55 } 56 } 57 58 StringRef llvm::getEnumName(MVT::SimpleValueType T) { 59 switch (T) { 60 case MVT::Other: return "MVT::Other"; 61 case MVT::i1: return "MVT::i1"; 62 case MVT::i8: return "MVT::i8"; 63 case MVT::i16: return "MVT::i16"; 64 case MVT::i32: return "MVT::i32"; 65 case MVT::i64: return "MVT::i64"; 66 case MVT::i128: return "MVT::i128"; 67 case MVT::Any: return "MVT::Any"; 68 case MVT::iAny: return "MVT::iAny"; 69 case MVT::fAny: return "MVT::fAny"; 70 case MVT::vAny: return "MVT::vAny"; 71 case MVT::f16: return "MVT::f16"; 72 case MVT::bf16: return "MVT::bf16"; 73 case MVT::f32: return "MVT::f32"; 74 case MVT::f64: return "MVT::f64"; 75 case MVT::f80: return "MVT::f80"; 76 case MVT::f128: return "MVT::f128"; 77 case MVT::ppcf128: return "MVT::ppcf128"; 78 case MVT::x86mmx: return "MVT::x86mmx"; 79 case MVT::Glue: return "MVT::Glue"; 80 case MVT::isVoid: return "MVT::isVoid"; 81 case MVT::v1i1: return "MVT::v1i1"; 82 case MVT::v2i1: return "MVT::v2i1"; 83 case MVT::v4i1: return "MVT::v4i1"; 84 case MVT::v8i1: return "MVT::v8i1"; 85 case MVT::v16i1: return "MVT::v16i1"; 86 case MVT::v32i1: return "MVT::v32i1"; 87 case MVT::v64i1: return "MVT::v64i1"; 88 case MVT::v128i1: return "MVT::v128i1"; 89 case MVT::v512i1: return "MVT::v512i1"; 90 case MVT::v1024i1: return "MVT::v1024i1"; 91 case MVT::v1i8: return "MVT::v1i8"; 92 case MVT::v2i8: return "MVT::v2i8"; 93 case MVT::v4i8: return "MVT::v4i8"; 94 case MVT::v8i8: return "MVT::v8i8"; 95 case MVT::v16i8: return "MVT::v16i8"; 96 case MVT::v32i8: return "MVT::v32i8"; 97 case MVT::v64i8: return "MVT::v64i8"; 98 case MVT::v128i8: return "MVT::v128i8"; 99 case MVT::v256i8: return "MVT::v256i8"; 100 case MVT::v1i16: return "MVT::v1i16"; 101 case MVT::v2i16: return "MVT::v2i16"; 102 case MVT::v3i16: return "MVT::v3i16"; 103 case MVT::v4i16: return "MVT::v4i16"; 104 case MVT::v8i16: return "MVT::v8i16"; 105 case MVT::v16i16: return "MVT::v16i16"; 106 case MVT::v32i16: return "MVT::v32i16"; 107 case MVT::v64i16: return "MVT::v64i16"; 108 case MVT::v128i16: return "MVT::v128i16"; 109 case MVT::v1i32: return "MVT::v1i32"; 110 case MVT::v2i32: return "MVT::v2i32"; 111 case MVT::v3i32: return "MVT::v3i32"; 112 case MVT::v4i32: return "MVT::v4i32"; 113 case MVT::v5i32: return "MVT::v5i32"; 114 case MVT::v8i32: return "MVT::v8i32"; 115 case MVT::v16i32: return "MVT::v16i32"; 116 case MVT::v32i32: return "MVT::v32i32"; 117 case MVT::v64i32: return "MVT::v64i32"; 118 case MVT::v128i32: return "MVT::v128i32"; 119 case MVT::v256i32: return "MVT::v256i32"; 120 case MVT::v512i32: return "MVT::v512i32"; 121 case MVT::v1024i32: return "MVT::v1024i32"; 122 case MVT::v2048i32: return "MVT::v2048i32"; 123 case MVT::v1i64: return "MVT::v1i64"; 124 case MVT::v2i64: return "MVT::v2i64"; 125 case MVT::v4i64: return "MVT::v4i64"; 126 case MVT::v8i64: return "MVT::v8i64"; 127 case MVT::v16i64: return "MVT::v16i64"; 128 case MVT::v32i64: return "MVT::v32i64"; 129 case MVT::v1i128: return "MVT::v1i128"; 130 case MVT::v2f16: return "MVT::v2f16"; 131 case MVT::v3f16: return "MVT::v3f16"; 132 case MVT::v4f16: return "MVT::v4f16"; 133 case MVT::v8f16: return "MVT::v8f16"; 134 case MVT::v16f16: return "MVT::v16f16"; 135 case MVT::v32f16: return "MVT::v32f16"; 136 case MVT::v64f16: return "MVT::v64f16"; 137 case MVT::v128f16: return "MVT::v128f16"; 138 case MVT::v2bf16: return "MVT::v2bf16"; 139 case MVT::v3bf16: return "MVT::v3bf16"; 140 case MVT::v4bf16: return "MVT::v4bf16"; 141 case MVT::v8bf16: return "MVT::v8bf16"; 142 case MVT::v16bf16: return "MVT::v16bf16"; 143 case MVT::v32bf16: return "MVT::v32bf16"; 144 case MVT::v64bf16: return "MVT::v64bf16"; 145 case MVT::v128bf16: return "MVT::v128bf16"; 146 case MVT::v1f32: return "MVT::v1f32"; 147 case MVT::v2f32: return "MVT::v2f32"; 148 case MVT::v3f32: return "MVT::v3f32"; 149 case MVT::v4f32: return "MVT::v4f32"; 150 case MVT::v5f32: return "MVT::v5f32"; 151 case MVT::v8f32: return "MVT::v8f32"; 152 case MVT::v16f32: return "MVT::v16f32"; 153 case MVT::v32f32: return "MVT::v32f32"; 154 case MVT::v64f32: return "MVT::v64f32"; 155 case MVT::v128f32: return "MVT::v128f32"; 156 case MVT::v256f32: return "MVT::v256f32"; 157 case MVT::v512f32: return "MVT::v512f32"; 158 case MVT::v1024f32: return "MVT::v1024f32"; 159 case MVT::v2048f32: return "MVT::v2048f32"; 160 case MVT::v1f64: return "MVT::v1f64"; 161 case MVT::v2f64: return "MVT::v2f64"; 162 case MVT::v4f64: return "MVT::v4f64"; 163 case MVT::v8f64: return "MVT::v8f64"; 164 case MVT::v16f64: return "MVT::v16f64"; 165 case MVT::v32f64: return "MVT::v32f64"; 166 case MVT::nxv1i1: return "MVT::nxv1i1"; 167 case MVT::nxv2i1: return "MVT::nxv2i1"; 168 case MVT::nxv4i1: return "MVT::nxv4i1"; 169 case MVT::nxv8i1: return "MVT::nxv8i1"; 170 case MVT::nxv16i1: return "MVT::nxv16i1"; 171 case MVT::nxv32i1: return "MVT::nxv32i1"; 172 case MVT::nxv64i1: return "MVT::nxv64i1"; 173 case MVT::nxv1i8: return "MVT::nxv1i8"; 174 case MVT::nxv2i8: return "MVT::nxv2i8"; 175 case MVT::nxv4i8: return "MVT::nxv4i8"; 176 case MVT::nxv8i8: return "MVT::nxv8i8"; 177 case MVT::nxv16i8: return "MVT::nxv16i8"; 178 case MVT::nxv32i8: return "MVT::nxv32i8"; 179 case MVT::nxv64i8: return "MVT::nxv64i8"; 180 case MVT::nxv1i16: return "MVT::nxv1i16"; 181 case MVT::nxv2i16: return "MVT::nxv2i16"; 182 case MVT::nxv4i16: return "MVT::nxv4i16"; 183 case MVT::nxv8i16: return "MVT::nxv8i16"; 184 case MVT::nxv16i16: return "MVT::nxv16i16"; 185 case MVT::nxv32i16: return "MVT::nxv32i16"; 186 case MVT::nxv1i32: return "MVT::nxv1i32"; 187 case MVT::nxv2i32: return "MVT::nxv2i32"; 188 case MVT::nxv4i32: return "MVT::nxv4i32"; 189 case MVT::nxv8i32: return "MVT::nxv8i32"; 190 case MVT::nxv16i32: return "MVT::nxv16i32"; 191 case MVT::nxv32i32: return "MVT::nxv32i32"; 192 case MVT::nxv1i64: return "MVT::nxv1i64"; 193 case MVT::nxv2i64: return "MVT::nxv2i64"; 194 case MVT::nxv4i64: return "MVT::nxv4i64"; 195 case MVT::nxv8i64: return "MVT::nxv8i64"; 196 case MVT::nxv16i64: return "MVT::nxv16i64"; 197 case MVT::nxv32i64: return "MVT::nxv32i64"; 198 case MVT::nxv1f16: return "MVT::nxv1f16"; 199 case MVT::nxv2f16: return "MVT::nxv2f16"; 200 case MVT::nxv4f16: return "MVT::nxv4f16"; 201 case MVT::nxv8f16: return "MVT::nxv8f16"; 202 case MVT::nxv16f16: return "MVT::nxv16f16"; 203 case MVT::nxv32f16: return "MVT::nxv32f16"; 204 case MVT::nxv2bf16: return "MVT::nxv2bf16"; 205 case MVT::nxv4bf16: return "MVT::nxv4bf16"; 206 case MVT::nxv8bf16: return "MVT::nxv8bf16"; 207 case MVT::nxv1f32: return "MVT::nxv1f32"; 208 case MVT::nxv2f32: return "MVT::nxv2f32"; 209 case MVT::nxv4f32: return "MVT::nxv4f32"; 210 case MVT::nxv8f32: return "MVT::nxv8f32"; 211 case MVT::nxv16f32: return "MVT::nxv16f32"; 212 case MVT::nxv1f64: return "MVT::nxv1f64"; 213 case MVT::nxv2f64: return "MVT::nxv2f64"; 214 case MVT::nxv4f64: return "MVT::nxv4f64"; 215 case MVT::nxv8f64: return "MVT::nxv8f64"; 216 case MVT::token: return "MVT::token"; 217 case MVT::Metadata: return "MVT::Metadata"; 218 case MVT::iPTR: return "MVT::iPTR"; 219 case MVT::iPTRAny: return "MVT::iPTRAny"; 220 case MVT::Untyped: return "MVT::Untyped"; 221 case MVT::exnref: return "MVT::exnref"; 222 default: llvm_unreachable("ILLEGAL VALUE TYPE!"); 223 } 224 } 225 226 /// getQualifiedName - Return the name of the specified record, with a 227 /// namespace qualifier if the record contains one. 228 /// 229 std::string llvm::getQualifiedName(const Record *R) { 230 std::string Namespace; 231 if (R->getValue("Namespace")) 232 Namespace = std::string(R->getValueAsString("Namespace")); 233 if (Namespace.empty()) 234 return std::string(R->getName()); 235 return Namespace + "::" + R->getName().str(); 236 } 237 238 239 /// getTarget - Return the current instance of the Target class. 240 /// 241 CodeGenTarget::CodeGenTarget(RecordKeeper &records) 242 : Records(records), CGH(records) { 243 std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target"); 244 if (Targets.size() == 0) 245 PrintFatalError("ERROR: No 'Target' subclasses defined!"); 246 if (Targets.size() != 1) 247 PrintFatalError("ERROR: Multiple subclasses of Target defined!"); 248 TargetRec = Targets[0]; 249 } 250 251 CodeGenTarget::~CodeGenTarget() { 252 } 253 254 const StringRef CodeGenTarget::getName() const { 255 return TargetRec->getName(); 256 } 257 258 StringRef CodeGenTarget::getInstNamespace() const { 259 for (const CodeGenInstruction *Inst : getInstructionsByEnumValue()) { 260 // Make sure not to pick up "TargetOpcode" by accidentally getting 261 // the namespace off the PHI instruction or something. 262 if (Inst->Namespace != "TargetOpcode") 263 return Inst->Namespace; 264 } 265 266 return ""; 267 } 268 269 StringRef CodeGenTarget::getRegNamespace() const { 270 auto &RegClasses = RegBank->getRegClasses(); 271 return RegClasses.size() > 0 ? RegClasses.front().Namespace : ""; 272 } 273 274 Record *CodeGenTarget::getInstructionSet() const { 275 return TargetRec->getValueAsDef("InstructionSet"); 276 } 277 278 bool CodeGenTarget::getAllowRegisterRenaming() const { 279 return TargetRec->getValueAsInt("AllowRegisterRenaming"); 280 } 281 282 /// getAsmParser - Return the AssemblyParser definition for this target. 283 /// 284 Record *CodeGenTarget::getAsmParser() const { 285 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers"); 286 if (AsmParserNum >= LI.size()) 287 PrintFatalError("Target does not have an AsmParser #" + 288 Twine(AsmParserNum) + "!"); 289 return LI[AsmParserNum]; 290 } 291 292 /// getAsmParserVariant - Return the AssemblyParserVariant definition for 293 /// this target. 294 /// 295 Record *CodeGenTarget::getAsmParserVariant(unsigned i) const { 296 std::vector<Record*> LI = 297 TargetRec->getValueAsListOfDefs("AssemblyParserVariants"); 298 if (i >= LI.size()) 299 PrintFatalError("Target does not have an AsmParserVariant #" + Twine(i) + 300 "!"); 301 return LI[i]; 302 } 303 304 /// getAsmParserVariantCount - Return the AssemblyParserVariant definition 305 /// available for this target. 306 /// 307 unsigned CodeGenTarget::getAsmParserVariantCount() const { 308 std::vector<Record*> LI = 309 TargetRec->getValueAsListOfDefs("AssemblyParserVariants"); 310 return LI.size(); 311 } 312 313 /// getAsmWriter - Return the AssemblyWriter definition for this target. 314 /// 315 Record *CodeGenTarget::getAsmWriter() const { 316 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters"); 317 if (AsmWriterNum >= LI.size()) 318 PrintFatalError("Target does not have an AsmWriter #" + 319 Twine(AsmWriterNum) + "!"); 320 return LI[AsmWriterNum]; 321 } 322 323 CodeGenRegBank &CodeGenTarget::getRegBank() const { 324 if (!RegBank) 325 RegBank = std::make_unique<CodeGenRegBank>(Records, getHwModes()); 326 return *RegBank; 327 } 328 329 Optional<CodeGenRegisterClass *> 330 CodeGenTarget::getSuperRegForSubReg(const ValueTypeByHwMode &ValueTy, 331 CodeGenRegBank &RegBank, 332 const CodeGenSubRegIndex *SubIdx) const { 333 std::vector<CodeGenRegisterClass *> Candidates; 334 auto &RegClasses = RegBank.getRegClasses(); 335 336 // Try to find a register class which supports ValueTy, and also contains 337 // SubIdx. 338 for (CodeGenRegisterClass &RC : RegClasses) { 339 // Is there a subclass of this class which contains this subregister index? 340 CodeGenRegisterClass *SubClassWithSubReg = RC.getSubClassWithSubReg(SubIdx); 341 if (!SubClassWithSubReg) 342 continue; 343 344 // We have a class. Check if it supports this value type. 345 if (llvm::none_of(SubClassWithSubReg->VTs, 346 [&ValueTy](const ValueTypeByHwMode &ClassVT) { 347 return ClassVT == ValueTy; 348 })) 349 continue; 350 351 // We have a register class which supports both the value type and 352 // subregister index. Remember it. 353 Candidates.push_back(SubClassWithSubReg); 354 } 355 356 // If we didn't find anything, we're done. 357 if (Candidates.empty()) 358 return None; 359 360 // Find and return the largest of our candidate classes. 361 llvm::stable_sort(Candidates, [&](const CodeGenRegisterClass *A, 362 const CodeGenRegisterClass *B) { 363 if (A->getMembers().size() > B->getMembers().size()) 364 return true; 365 366 if (A->getMembers().size() < B->getMembers().size()) 367 return false; 368 369 // Order by name as a tie-breaker. 370 return StringRef(A->getName()) < B->getName(); 371 }); 372 373 return Candidates[0]; 374 } 375 376 void CodeGenTarget::ReadRegAltNameIndices() const { 377 RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex"); 378 llvm::sort(RegAltNameIndices, LessRecord()); 379 } 380 381 /// getRegisterByName - If there is a register with the specific AsmName, 382 /// return it. 383 const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const { 384 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName(); 385 StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name); 386 if (I == Regs.end()) 387 return nullptr; 388 return I->second; 389 } 390 391 std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R) 392 const { 393 const CodeGenRegister *Reg = getRegBank().getReg(R); 394 std::vector<ValueTypeByHwMode> Result; 395 for (const auto &RC : getRegBank().getRegClasses()) { 396 if (RC.contains(Reg)) { 397 ArrayRef<ValueTypeByHwMode> InVTs = RC.getValueTypes(); 398 Result.insert(Result.end(), InVTs.begin(), InVTs.end()); 399 } 400 } 401 402 // Remove duplicates. 403 llvm::sort(Result); 404 Result.erase(std::unique(Result.begin(), Result.end()), Result.end()); 405 return Result; 406 } 407 408 409 void CodeGenTarget::ReadLegalValueTypes() const { 410 for (const auto &RC : getRegBank().getRegClasses()) 411 LegalValueTypes.insert(LegalValueTypes.end(), RC.VTs.begin(), RC.VTs.end()); 412 413 // Remove duplicates. 414 llvm::sort(LegalValueTypes); 415 LegalValueTypes.erase(std::unique(LegalValueTypes.begin(), 416 LegalValueTypes.end()), 417 LegalValueTypes.end()); 418 } 419 420 CodeGenSchedModels &CodeGenTarget::getSchedModels() const { 421 if (!SchedModels) 422 SchedModels = std::make_unique<CodeGenSchedModels>(Records, *this); 423 return *SchedModels; 424 } 425 426 void CodeGenTarget::ReadInstructions() const { 427 NamedRegionTimer T("Read Instructions", "Time spent reading instructions", 428 "CodeGenTarget", "CodeGenTarget", TimeRegions); 429 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction"); 430 if (Insts.size() <= 2) 431 PrintFatalError("No 'Instruction' subclasses defined!"); 432 433 // Parse the instructions defined in the .td file. 434 for (unsigned i = 0, e = Insts.size(); i != e; ++i) 435 Instructions[Insts[i]] = std::make_unique<CodeGenInstruction>(Insts[i]); 436 } 437 438 static const CodeGenInstruction * 439 GetInstByName(const char *Name, 440 const DenseMap<const Record*, 441 std::unique_ptr<CodeGenInstruction>> &Insts, 442 RecordKeeper &Records) { 443 const Record *Rec = Records.getDef(Name); 444 445 const auto I = Insts.find(Rec); 446 if (!Rec || I == Insts.end()) 447 PrintFatalError(Twine("Could not find '") + Name + "' instruction!"); 448 return I->second.get(); 449 } 450 451 static const char *const FixedInstrs[] = { 452 #define HANDLE_TARGET_OPCODE(OPC) #OPC, 453 #include "llvm/Support/TargetOpcodes.def" 454 nullptr}; 455 456 unsigned CodeGenTarget::getNumFixedInstructions() { 457 return array_lengthof(FixedInstrs) - 1; 458 } 459 460 /// Return all of the instructions defined by the target, ordered by 461 /// their enum value. 462 void CodeGenTarget::ComputeInstrsByEnum() const { 463 const auto &Insts = getInstructions(); 464 for (const char *const *p = FixedInstrs; *p; ++p) { 465 const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records); 466 assert(Instr && "Missing target independent instruction"); 467 assert(Instr->Namespace == "TargetOpcode" && "Bad namespace"); 468 InstrsByEnum.push_back(Instr); 469 } 470 unsigned EndOfPredefines = InstrsByEnum.size(); 471 assert(EndOfPredefines == getNumFixedInstructions() && 472 "Missing generic opcode"); 473 474 for (const auto &I : Insts) { 475 const CodeGenInstruction *CGI = I.second.get(); 476 if (CGI->Namespace != "TargetOpcode") { 477 InstrsByEnum.push_back(CGI); 478 if (CGI->TheDef->getValueAsBit("isPseudo")) 479 ++NumPseudoInstructions; 480 } 481 } 482 483 assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr"); 484 485 // All of the instructions are now in random order based on the map iteration. 486 llvm::sort( 487 InstrsByEnum.begin() + EndOfPredefines, InstrsByEnum.end(), 488 [](const CodeGenInstruction *Rec1, const CodeGenInstruction *Rec2) { 489 const auto &D1 = *Rec1->TheDef; 490 const auto &D2 = *Rec2->TheDef; 491 return std::make_tuple(!D1.getValueAsBit("isPseudo"), D1.getName()) < 492 std::make_tuple(!D2.getValueAsBit("isPseudo"), D2.getName()); 493 }); 494 } 495 496 497 /// isLittleEndianEncoding - Return whether this target encodes its instruction 498 /// in little-endian format, i.e. bits laid out in the order [0..n] 499 /// 500 bool CodeGenTarget::isLittleEndianEncoding() const { 501 return getInstructionSet()->getValueAsBit("isLittleEndianEncoding"); 502 } 503 504 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit 505 /// encodings, reverse the bit order of all instructions. 506 void CodeGenTarget::reverseBitsForLittleEndianEncoding() { 507 if (!isLittleEndianEncoding()) 508 return; 509 510 std::vector<Record *> Insts = 511 Records.getAllDerivedDefinitions("InstructionEncoding"); 512 for (Record *R : Insts) { 513 if (R->getValueAsString("Namespace") == "TargetOpcode" || 514 R->getValueAsBit("isPseudo")) 515 continue; 516 517 BitsInit *BI = R->getValueAsBitsInit("Inst"); 518 519 unsigned numBits = BI->getNumBits(); 520 521 SmallVector<Init *, 16> NewBits(numBits); 522 523 for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) { 524 unsigned bitSwapIdx = numBits - bit - 1; 525 Init *OrigBit = BI->getBit(bit); 526 Init *BitSwap = BI->getBit(bitSwapIdx); 527 NewBits[bit] = BitSwap; 528 NewBits[bitSwapIdx] = OrigBit; 529 } 530 if (numBits % 2) { 531 unsigned middle = (numBits + 1) / 2; 532 NewBits[middle] = BI->getBit(middle); 533 } 534 535 BitsInit *NewBI = BitsInit::get(NewBits); 536 537 // Update the bits in reversed order so that emitInstrOpBits will get the 538 // correct endianness. 539 R->getValue("Inst")->setValue(NewBI); 540 } 541 } 542 543 /// guessInstructionProperties - Return true if it's OK to guess instruction 544 /// properties instead of raising an error. 545 /// 546 /// This is configurable as a temporary migration aid. It will eventually be 547 /// permanently false. 548 bool CodeGenTarget::guessInstructionProperties() const { 549 return getInstructionSet()->getValueAsBit("guessInstructionProperties"); 550 } 551 552 //===----------------------------------------------------------------------===// 553 // ComplexPattern implementation 554 // 555 ComplexPattern::ComplexPattern(Record *R) { 556 Ty = ::getValueType(R->getValueAsDef("Ty")); 557 NumOperands = R->getValueAsInt("NumOperands"); 558 SelectFunc = std::string(R->getValueAsString("SelectFunc")); 559 RootNodes = R->getValueAsListOfDefs("RootNodes"); 560 561 // FIXME: This is a hack to statically increase the priority of patterns which 562 // maps a sub-dag to a complex pattern. e.g. favors LEA over ADD. To get best 563 // possible pattern match we'll need to dynamically calculate the complexity 564 // of all patterns a dag can potentially map to. 565 int64_t RawComplexity = R->getValueAsInt("Complexity"); 566 if (RawComplexity == -1) 567 Complexity = NumOperands * 3; 568 else 569 Complexity = RawComplexity; 570 571 // FIXME: Why is this different from parseSDPatternOperatorProperties? 572 // Parse the properties. 573 Properties = 0; 574 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties"); 575 for (unsigned i = 0, e = PropList.size(); i != e; ++i) 576 if (PropList[i]->getName() == "SDNPHasChain") { 577 Properties |= 1 << SDNPHasChain; 578 } else if (PropList[i]->getName() == "SDNPOptInGlue") { 579 Properties |= 1 << SDNPOptInGlue; 580 } else if (PropList[i]->getName() == "SDNPMayStore") { 581 Properties |= 1 << SDNPMayStore; 582 } else if (PropList[i]->getName() == "SDNPMayLoad") { 583 Properties |= 1 << SDNPMayLoad; 584 } else if (PropList[i]->getName() == "SDNPSideEffect") { 585 Properties |= 1 << SDNPSideEffect; 586 } else if (PropList[i]->getName() == "SDNPMemOperand") { 587 Properties |= 1 << SDNPMemOperand; 588 } else if (PropList[i]->getName() == "SDNPVariadic") { 589 Properties |= 1 << SDNPVariadic; 590 } else if (PropList[i]->getName() == "SDNPWantRoot") { 591 Properties |= 1 << SDNPWantRoot; 592 } else if (PropList[i]->getName() == "SDNPWantParent") { 593 Properties |= 1 << SDNPWantParent; 594 } else { 595 PrintFatalError(R->getLoc(), "Unsupported SD Node property '" + 596 PropList[i]->getName() + 597 "' on ComplexPattern '" + R->getName() + 598 "'!"); 599 } 600 } 601 602 //===----------------------------------------------------------------------===// 603 // CodeGenIntrinsic Implementation 604 //===----------------------------------------------------------------------===// 605 606 CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC) { 607 std::vector<Record *> IntrProperties = 608 RC.getAllDerivedDefinitions("IntrinsicProperty"); 609 610 std::vector<Record *> DefaultProperties; 611 for (Record *Rec : IntrProperties) 612 if (Rec->getValueAsBit("IsDefault")) 613 DefaultProperties.push_back(Rec); 614 615 std::vector<Record *> Defs = RC.getAllDerivedDefinitions("Intrinsic"); 616 Intrinsics.reserve(Defs.size()); 617 618 for (unsigned I = 0, e = Defs.size(); I != e; ++I) 619 Intrinsics.push_back(CodeGenIntrinsic(Defs[I], DefaultProperties)); 620 621 llvm::sort(Intrinsics, 622 [](const CodeGenIntrinsic &LHS, const CodeGenIntrinsic &RHS) { 623 return std::tie(LHS.TargetPrefix, LHS.Name) < 624 std::tie(RHS.TargetPrefix, RHS.Name); 625 }); 626 Targets.push_back({"", 0, 0}); 627 for (size_t I = 0, E = Intrinsics.size(); I < E; ++I) 628 if (Intrinsics[I].TargetPrefix != Targets.back().Name) { 629 Targets.back().Count = I - Targets.back().Offset; 630 Targets.push_back({Intrinsics[I].TargetPrefix, I, 0}); 631 } 632 Targets.back().Count = Intrinsics.size() - Targets.back().Offset; 633 } 634 635 CodeGenIntrinsic::CodeGenIntrinsic(Record *R, 636 std::vector<Record *> DefaultProperties) { 637 TheDef = R; 638 std::string DefName = std::string(R->getName()); 639 ArrayRef<SMLoc> DefLoc = R->getLoc(); 640 ModRef = ReadWriteMem; 641 Properties = 0; 642 isOverloaded = false; 643 isCommutative = false; 644 canThrow = false; 645 isNoReturn = false; 646 isNoSync = false; 647 isNoFree = false; 648 isWillReturn = false; 649 isCold = false; 650 isNoDuplicate = false; 651 isConvergent = false; 652 isSpeculatable = false; 653 hasSideEffects = false; 654 655 if (DefName.size() <= 4 || 656 std::string(DefName.begin(), DefName.begin() + 4) != "int_") 657 PrintFatalError(DefLoc, 658 "Intrinsic '" + DefName + "' does not start with 'int_'!"); 659 660 EnumName = std::string(DefName.begin()+4, DefName.end()); 661 662 if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field. 663 GCCBuiltinName = std::string(R->getValueAsString("GCCBuiltinName")); 664 if (R->getValue("MSBuiltinName")) // Ignore a missing MSBuiltinName field. 665 MSBuiltinName = std::string(R->getValueAsString("MSBuiltinName")); 666 667 TargetPrefix = std::string(R->getValueAsString("TargetPrefix")); 668 Name = std::string(R->getValueAsString("LLVMName")); 669 670 if (Name == "") { 671 // If an explicit name isn't specified, derive one from the DefName. 672 Name = "llvm."; 673 674 for (unsigned i = 0, e = EnumName.size(); i != e; ++i) 675 Name += (EnumName[i] == '_') ? '.' : EnumName[i]; 676 } else { 677 // Verify it starts with "llvm.". 678 if (Name.size() <= 5 || 679 std::string(Name.begin(), Name.begin() + 5) != "llvm.") 680 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 681 "'s name does not start with 'llvm.'!"); 682 } 683 684 // If TargetPrefix is specified, make sure that Name starts with 685 // "llvm.<targetprefix>.". 686 if (!TargetPrefix.empty()) { 687 if (Name.size() < 6+TargetPrefix.size() || 688 std::string(Name.begin() + 5, Name.begin() + 6 + TargetPrefix.size()) 689 != (TargetPrefix + ".")) 690 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 691 "' does not start with 'llvm." + 692 TargetPrefix + ".'!"); 693 } 694 695 ListInit *RetTypes = R->getValueAsListInit("RetTypes"); 696 ListInit *ParamTypes = R->getValueAsListInit("ParamTypes"); 697 698 // First collate a list of overloaded types. 699 std::vector<MVT::SimpleValueType> OverloadedVTs; 700 for (ListInit *TypeList : {RetTypes, ParamTypes}) { 701 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 702 Record *TyEl = TypeList->getElementAsRecord(i); 703 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 704 705 if (TyEl->isSubClassOf("LLVMMatchType")) 706 continue; 707 708 MVT::SimpleValueType VT = getValueType(TyEl->getValueAsDef("VT")); 709 if (MVT(VT).isOverloaded()) { 710 OverloadedVTs.push_back(VT); 711 isOverloaded = true; 712 } 713 } 714 } 715 716 // Parse the list of return types. 717 ListInit *TypeList = RetTypes; 718 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 719 Record *TyEl = TypeList->getElementAsRecord(i); 720 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 721 MVT::SimpleValueType VT; 722 if (TyEl->isSubClassOf("LLVMMatchType")) { 723 unsigned MatchTy = TyEl->getValueAsInt("Number"); 724 assert(MatchTy < OverloadedVTs.size() && 725 "Invalid matching number!"); 726 VT = OverloadedVTs[MatchTy]; 727 // It only makes sense to use the extended and truncated vector element 728 // variants with iAny types; otherwise, if the intrinsic is not 729 // overloaded, all the types can be specified directly. 730 assert(((!TyEl->isSubClassOf("LLVMExtendedType") && 731 !TyEl->isSubClassOf("LLVMTruncatedType")) || 732 VT == MVT::iAny || VT == MVT::vAny) && 733 "Expected iAny or vAny type"); 734 } else { 735 VT = getValueType(TyEl->getValueAsDef("VT")); 736 } 737 738 // Reject invalid types. 739 if (VT == MVT::isVoid) 740 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 741 " has void in result type list!"); 742 743 IS.RetVTs.push_back(VT); 744 IS.RetTypeDefs.push_back(TyEl); 745 } 746 747 // Parse the list of parameter types. 748 TypeList = ParamTypes; 749 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 750 Record *TyEl = TypeList->getElementAsRecord(i); 751 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 752 MVT::SimpleValueType VT; 753 if (TyEl->isSubClassOf("LLVMMatchType")) { 754 unsigned MatchTy = TyEl->getValueAsInt("Number"); 755 if (MatchTy >= OverloadedVTs.size()) { 756 PrintError(R->getLoc(), 757 "Parameter #" + Twine(i) + " has out of bounds matching " 758 "number " + Twine(MatchTy)); 759 PrintFatalError(DefLoc, 760 Twine("ParamTypes is ") + TypeList->getAsString()); 761 } 762 VT = OverloadedVTs[MatchTy]; 763 // It only makes sense to use the extended and truncated vector element 764 // variants with iAny types; otherwise, if the intrinsic is not 765 // overloaded, all the types can be specified directly. 766 assert(((!TyEl->isSubClassOf("LLVMExtendedType") && 767 !TyEl->isSubClassOf("LLVMTruncatedType")) || 768 VT == MVT::iAny || VT == MVT::vAny) && 769 "Expected iAny or vAny type"); 770 } else 771 VT = getValueType(TyEl->getValueAsDef("VT")); 772 773 // Reject invalid types. 774 if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/) 775 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 776 " has void in result type list!"); 777 778 IS.ParamVTs.push_back(VT); 779 IS.ParamTypeDefs.push_back(TyEl); 780 } 781 782 // Set default properties to true. 783 setDefaultProperties(R, DefaultProperties); 784 785 // Parse the intrinsic properties. 786 ListInit *PropList = R->getValueAsListInit("IntrProperties"); 787 for (unsigned i = 0, e = PropList->size(); i != e; ++i) { 788 Record *Property = PropList->getElementAsRecord(i); 789 assert(Property->isSubClassOf("IntrinsicProperty") && 790 "Expected a property!"); 791 792 setProperty(Property); 793 } 794 795 // Also record the SDPatternOperator Properties. 796 Properties = parseSDPatternOperatorProperties(R); 797 798 // Sort the argument attributes for later benefit. 799 llvm::sort(ArgumentAttributes); 800 } 801 802 void CodeGenIntrinsic::setDefaultProperties( 803 Record *R, std::vector<Record *> DefaultProperties) { 804 // opt-out of using default attributes. 805 if (R->getValueAsBit("DisableDefaultAttributes")) 806 return; 807 808 for (Record *Rec : DefaultProperties) 809 setProperty(Rec); 810 } 811 812 void CodeGenIntrinsic::setProperty(Record *R) { 813 if (R->getName() == "IntrNoMem") 814 ModRef = NoMem; 815 else if (R->getName() == "IntrReadMem") 816 ModRef = ModRefBehavior(ModRef & ~MR_Mod); 817 else if (R->getName() == "IntrWriteMem") 818 ModRef = ModRefBehavior(ModRef & ~MR_Ref); 819 else if (R->getName() == "IntrArgMemOnly") 820 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem); 821 else if (R->getName() == "IntrInaccessibleMemOnly") 822 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_InaccessibleMem); 823 else if (R->getName() == "IntrInaccessibleMemOrArgMemOnly") 824 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem | 825 MR_InaccessibleMem); 826 else if (R->getName() == "Commutative") 827 isCommutative = true; 828 else if (R->getName() == "Throws") 829 canThrow = true; 830 else if (R->getName() == "IntrNoDuplicate") 831 isNoDuplicate = true; 832 else if (R->getName() == "IntrConvergent") 833 isConvergent = true; 834 else if (R->getName() == "IntrNoReturn") 835 isNoReturn = true; 836 else if (R->getName() == "IntrNoSync") 837 isNoSync = true; 838 else if (R->getName() == "IntrNoFree") 839 isNoFree = true; 840 else if (R->getName() == "IntrWillReturn") 841 isWillReturn = true; 842 else if (R->getName() == "IntrCold") 843 isCold = true; 844 else if (R->getName() == "IntrSpeculatable") 845 isSpeculatable = true; 846 else if (R->getName() == "IntrHasSideEffects") 847 hasSideEffects = true; 848 else if (R->isSubClassOf("NoCapture")) { 849 unsigned ArgNo = R->getValueAsInt("ArgNo"); 850 ArgumentAttributes.emplace_back(ArgNo, NoCapture, 0); 851 } else if (R->isSubClassOf("NoAlias")) { 852 unsigned ArgNo = R->getValueAsInt("ArgNo"); 853 ArgumentAttributes.emplace_back(ArgNo, NoAlias, 0); 854 } else if (R->isSubClassOf("NoUndef")) { 855 unsigned ArgNo = R->getValueAsInt("ArgNo"); 856 ArgumentAttributes.emplace_back(ArgNo, NoUndef, 0); 857 } else if (R->isSubClassOf("Returned")) { 858 unsigned ArgNo = R->getValueAsInt("ArgNo"); 859 ArgumentAttributes.emplace_back(ArgNo, Returned, 0); 860 } else if (R->isSubClassOf("ReadOnly")) { 861 unsigned ArgNo = R->getValueAsInt("ArgNo"); 862 ArgumentAttributes.emplace_back(ArgNo, ReadOnly, 0); 863 } else if (R->isSubClassOf("WriteOnly")) { 864 unsigned ArgNo = R->getValueAsInt("ArgNo"); 865 ArgumentAttributes.emplace_back(ArgNo, WriteOnly, 0); 866 } else if (R->isSubClassOf("ReadNone")) { 867 unsigned ArgNo = R->getValueAsInt("ArgNo"); 868 ArgumentAttributes.emplace_back(ArgNo, ReadNone, 0); 869 } else if (R->isSubClassOf("ImmArg")) { 870 unsigned ArgNo = R->getValueAsInt("ArgNo"); 871 ArgumentAttributes.emplace_back(ArgNo, ImmArg, 0); 872 } else if (R->isSubClassOf("Align")) { 873 unsigned ArgNo = R->getValueAsInt("ArgNo"); 874 uint64_t Align = R->getValueAsInt("Align"); 875 ArgumentAttributes.emplace_back(ArgNo, Alignment, Align); 876 } else 877 llvm_unreachable("Unknown property!"); 878 } 879 880 bool CodeGenIntrinsic::isParamAPointer(unsigned ParamIdx) const { 881 if (ParamIdx >= IS.ParamVTs.size()) 882 return false; 883 MVT ParamType = MVT(IS.ParamVTs[ParamIdx]); 884 return ParamType == MVT::iPTR || ParamType == MVT::iPTRAny; 885 } 886 887 bool CodeGenIntrinsic::isParamImmArg(unsigned ParamIdx) const { 888 // Convert argument index to attribute index starting from `FirstArgIndex`. 889 ArgAttribute Val{ParamIdx + 1, ImmArg, 0}; 890 return std::binary_search(ArgumentAttributes.begin(), 891 ArgumentAttributes.end(), Val); 892 } 893