1 //===- CodeEmitterGen.cpp - Code Emitter Generator ------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // CodeEmitterGen uses the descriptions of instructions and their fields to
11 // construct an automated code emitter: a function that, given a MachineInstr,
12 // returns the (currently, 32-bit unsigned) value of the instruction.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "CodeEmitterGen.h"
17 #include "CodeGenTarget.h"
18 #include "Record.h"
19 #include "llvm/ADT/StringExtras.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/Debug.h"
22 #include <map>
23 using namespace llvm;
24 
25 // FIXME: Somewhat hackish to use a command line option for this. There should
26 // be a CodeEmitter class in the Target.td that controls this sort of thing
27 // instead.
28 static cl::opt<bool>
29 MCEmitter("mc-emitter",
30           cl::desc("Generate CodeEmitter for use with the MC library."),
31           cl::init(false));
32 
33 void CodeEmitterGen::reverseBits(std::vector<Record*> &Insts) {
34   for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
35        I != E; ++I) {
36     Record *R = *I;
37     if (R->getValueAsString("Namespace") == "TargetOpcode")
38       continue;
39 
40     BitsInit *BI = R->getValueAsBitsInit("Inst");
41 
42     unsigned numBits = BI->getNumBits();
43     BitsInit *NewBI = new BitsInit(numBits);
44     for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) {
45       unsigned bitSwapIdx = numBits - bit - 1;
46       Init *OrigBit = BI->getBit(bit);
47       Init *BitSwap = BI->getBit(bitSwapIdx);
48       NewBI->setBit(bit, BitSwap);
49       NewBI->setBit(bitSwapIdx, OrigBit);
50     }
51     if (numBits % 2) {
52       unsigned middle = (numBits + 1) / 2;
53       NewBI->setBit(middle, BI->getBit(middle));
54     }
55 
56     // Update the bits in reversed order so that emitInstrOpBits will get the
57     // correct endianness.
58     R->getValue("Inst")->setValue(NewBI);
59   }
60 }
61 
62 // If the VarBitInit at position 'bit' matches the specified variable then
63 // return the variable bit position.  Otherwise return -1.
64 int CodeEmitterGen::getVariableBit(const std::string &VarName,
65                                    BitsInit *BI, int bit) {
66   if (VarBitInit *VBI = dynamic_cast<VarBitInit*>(BI->getBit(bit)))
67     if (VarInit *VI = dynamic_cast<VarInit*>(VBI->getVariable()))
68       if (VI->getName() == VarName)
69         return VBI->getBitNum();
70 
71   return -1;
72 }
73 
74 void CodeEmitterGen::
75 AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName,
76                         unsigned &NumberedOp,
77                         std::string &Case, CodeGenTarget &Target) {
78   CodeGenInstruction &CGI = Target.getInstruction(R);
79 
80   // Determine if VarName actually contributes to the Inst encoding.
81   int bit = BI->getNumBits()-1;
82 
83   // Scan for a bit that this contributed to.
84   for (; bit >= 0; ) {
85     if (getVariableBit(VarName, BI, bit) != -1)
86       break;
87 
88     --bit;
89   }
90 
91   // If we found no bits, ignore this value, otherwise emit the call to get the
92   // operand encoding.
93   if (bit < 0) return;
94 
95   // If the operand matches by name, reference according to that
96   // operand number. Non-matching operands are assumed to be in
97   // order.
98   unsigned OpIdx;
99   if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) {
100     // Get the machine operand number for the indicated operand.
101     OpIdx = CGI.Operands[OpIdx].MIOperandNo;
102     assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) &&
103            "Explicitly used operand also marked as not emitted!");
104   } else {
105     /// If this operand is not supposed to be emitted by the
106     /// generated emitter, skip it.
107     while (CGI.Operands.isFlatOperandNotEmitted(NumberedOp))
108       ++NumberedOp;
109     OpIdx = NumberedOp++;
110   }
111 
112   std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx);
113   std::string &EncoderMethodName = CGI.Operands[SO.first].EncoderMethodName;
114 
115   // If the source operand has a custom encoder, use it. This will
116   // get the encoding for all of the suboperands.
117   if (!EncoderMethodName.empty()) {
118     // A custom encoder has all of the information for the
119     // sub-operands, if there are more than one, so only
120     // query the encoder once per source operand.
121     if (SO.second == 0) {
122       Case += "      // op: " + VarName + "\n" +
123               "      op = " + EncoderMethodName + "(MI, " + utostr(OpIdx);
124       if (MCEmitter)
125         Case += ", Fixups";
126       Case += ");\n";
127     }
128   } else {
129     Case += "      // op: " + VarName + "\n" +
130       "      op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")";
131     if (MCEmitter)
132       Case += ", Fixups";
133     Case += ");\n";
134   }
135 
136   for (; bit >= 0; ) {
137     int varBit = getVariableBit(VarName, BI, bit);
138 
139     // If this bit isn't from a variable, skip it.
140     if (varBit == -1) {
141       --bit;
142       continue;
143     }
144 
145     // Figure out the consequtive range of bits covered by this operand, in
146     // order to generate better encoding code.
147     int beginInstBit = bit;
148     int beginVarBit = varBit;
149     int N = 1;
150     for (--bit; bit >= 0;) {
151       varBit = getVariableBit(VarName, BI, bit);
152       if (varBit == -1 || varBit != (beginVarBit - N)) break;
153       ++N;
154       --bit;
155     }
156 
157     unsigned opMask = ~0U >> (32-N);
158     int opShift = beginVarBit - N + 1;
159     opMask <<= opShift;
160     opShift = beginInstBit - beginVarBit;
161 
162     if (opShift > 0) {
163       Case += "      Value |= (op & " + utostr(opMask) + "U) << " +
164               itostr(opShift) + ";\n";
165     } else if (opShift < 0) {
166       Case += "      Value |= (op & " + utostr(opMask) + "U) >> " +
167               itostr(-opShift) + ";\n";
168     } else {
169       Case += "      Value |= op & " + utostr(opMask) + "U;\n";
170     }
171   }
172 }
173 
174 
175 std::string CodeEmitterGen::getInstructionCase(Record *R,
176                                                CodeGenTarget &Target) {
177   std::string Case;
178 
179   BitsInit *BI = R->getValueAsBitsInit("Inst");
180   const std::vector<RecordVal> &Vals = R->getValues();
181   unsigned NumberedOp = 0;
182 
183   // Loop over all of the fields in the instruction, determining which are the
184   // operands to the instruction.
185   for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
186     // Ignore fixed fields in the record, we're looking for values like:
187     //    bits<5> RST = { ?, ?, ?, ?, ? };
188     if (Vals[i].getPrefix() || Vals[i].getValue()->isComplete())
189       continue;
190 
191     AddCodeToMergeInOperand(R, BI, Vals[i].getName(), NumberedOp, Case, Target);
192   }
193 
194   std::string PostEmitter = R->getValueAsString("PostEncoderMethod");
195   if (!PostEmitter.empty())
196     Case += "      Value = " + PostEmitter + "(MI, Value);\n";
197 
198   return Case;
199 }
200 
201 void CodeEmitterGen::run(raw_ostream &o) {
202   CodeGenTarget Target(Records);
203   std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
204 
205   // For little-endian instruction bit encodings, reverse the bit order
206   if (Target.isLittleEndianEncoding()) reverseBits(Insts);
207 
208   EmitSourceFileHeader("Machine Code Emitter", o);
209   std::string Namespace = Insts[0]->getValueAsString("Namespace") + "::";
210 
211   const std::vector<const CodeGenInstruction*> &NumberedInstructions =
212     Target.getInstructionsByEnumValue();
213 
214   // Emit function declaration
215   o << "unsigned " << Target.getName();
216   if (MCEmitter)
217     o << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n"
218       << "    SmallVectorImpl<MCFixup> &Fixups) const {\n";
219   else
220     o << "CodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) const {\n";
221 
222   // Emit instruction base values
223   o << "  static const unsigned InstBits[] = {\n";
224   for (std::vector<const CodeGenInstruction*>::const_iterator
225           IN = NumberedInstructions.begin(),
226           EN = NumberedInstructions.end();
227        IN != EN; ++IN) {
228     const CodeGenInstruction *CGI = *IN;
229     Record *R = CGI->TheDef;
230 
231     if (R->getValueAsString("Namespace") == "TargetOpcode") {
232       o << "    0U,\n";
233       continue;
234     }
235 
236     BitsInit *BI = R->getValueAsBitsInit("Inst");
237 
238     // Start by filling in fixed values.
239     unsigned Value = 0;
240     for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) {
241       if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(e-i-1)))
242         Value |= B->getValue() << (e-i-1);
243     }
244     o << "    " << Value << "U," << '\t' << "// " << R->getName() << "\n";
245   }
246   o << "    0U\n  };\n";
247 
248   // Map to accumulate all the cases.
249   std::map<std::string, std::vector<std::string> > CaseMap;
250 
251   // Construct all cases statement for each opcode
252   for (std::vector<Record*>::iterator IC = Insts.begin(), EC = Insts.end();
253         IC != EC; ++IC) {
254     Record *R = *IC;
255     if (R->getValueAsString("Namespace") == "TargetOpcode")
256       continue;
257     const std::string &InstName = R->getName();
258     std::string Case = getInstructionCase(R, Target);
259 
260     CaseMap[Case].push_back(InstName);
261   }
262 
263   // Emit initial function code
264   o << "  const unsigned opcode = MI.getOpcode();\n"
265     << "  unsigned Value = InstBits[opcode];\n"
266     << "  unsigned op = 0;\n"
267     << "  (void)op;  // suppress warning\n"
268     << "  switch (opcode) {\n";
269 
270   // Emit each case statement
271   std::map<std::string, std::vector<std::string> >::iterator IE, EE;
272   for (IE = CaseMap.begin(), EE = CaseMap.end(); IE != EE; ++IE) {
273     const std::string &Case = IE->first;
274     std::vector<std::string> &InstList = IE->second;
275 
276     for (int i = 0, N = InstList.size(); i < N; i++) {
277       if (i) o << "\n";
278       o << "    case " << Namespace << InstList[i]  << ":";
279     }
280     o << " {\n";
281     o << Case;
282     o << "      break;\n"
283       << "    }\n";
284   }
285 
286   // Default case: unhandled opcode
287   o << "  default:\n"
288     << "    std::string msg;\n"
289     << "    raw_string_ostream Msg(msg);\n"
290     << "    Msg << \"Not supported instr: \" << MI;\n"
291     << "    report_fatal_error(Msg.str());\n"
292     << "  }\n"
293     << "  return Value;\n"
294     << "}\n\n";
295 }
296