1 //===- CodeEmitterGen.cpp - Code Emitter Generator ------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // CodeEmitterGen uses the descriptions of instructions and their fields to
11 // construct an automated code emitter: a function that, given a MachineInstr,
12 // returns the (currently, 32-bit unsigned) value of the instruction.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "CodeEmitterGen.h"
17 #include "CodeGenTarget.h"
18 #include "Record.h"
19 #include "llvm/ADT/StringExtras.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/Debug.h"
22 #include <map>
23 using namespace llvm;
24 
25 // FIXME: Somewhat hackish to use a command line option for this. There should
26 // be a CodeEmitter class in the Target.td that controls this sort of thing
27 // instead.
28 static cl::opt<bool>
29 MCEmitter("mc-emitter",
30           cl::desc("Generate CodeEmitter for use with the MC library."),
31           cl::init(false));
32 
33 void CodeEmitterGen::reverseBits(std::vector<Record*> &Insts) {
34   for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
35        I != E; ++I) {
36     Record *R = *I;
37     if (R->getValueAsString("Namespace") == "TargetOpcode")
38       continue;
39 
40     BitsInit *BI = R->getValueAsBitsInit("Inst");
41 
42     unsigned numBits = BI->getNumBits();
43     BitsInit *NewBI = new BitsInit(numBits);
44     for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) {
45       unsigned bitSwapIdx = numBits - bit - 1;
46       Init *OrigBit = BI->getBit(bit);
47       Init *BitSwap = BI->getBit(bitSwapIdx);
48       NewBI->setBit(bit, BitSwap);
49       NewBI->setBit(bitSwapIdx, OrigBit);
50     }
51     if (numBits % 2) {
52       unsigned middle = (numBits + 1) / 2;
53       NewBI->setBit(middle, BI->getBit(middle));
54     }
55 
56     // Update the bits in reversed order so that emitInstrOpBits will get the
57     // correct endianness.
58     R->getValue("Inst")->setValue(NewBI);
59   }
60 }
61 
62 // If the VarBitInit at position 'bit' matches the specified variable then
63 // return the variable bit position.  Otherwise return -1.
64 int CodeEmitterGen::getVariableBit(const std::string &VarName,
65                                    BitsInit *BI, int bit) {
66   if (VarBitInit *VBI = dynamic_cast<VarBitInit*>(BI->getBit(bit))) {
67     if (VarInit *VI = dynamic_cast<VarInit*>(VBI->getVariable()))
68       if (VI->getName() == VarName)
69         return VBI->getBitNum();
70   } else if (VarInit *VI = dynamic_cast<VarInit*>(BI->getBit(bit))) {
71     if (VI->getName() == VarName)
72       return 0;
73   }
74 
75   return -1;
76 }
77 
78 void CodeEmitterGen::
79 AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName,
80                         unsigned &NumberedOp,
81                         std::string &Case, CodeGenTarget &Target) {
82   CodeGenInstruction &CGI = Target.getInstruction(R);
83 
84   // Determine if VarName actually contributes to the Inst encoding.
85   int bit = BI->getNumBits()-1;
86 
87   // Scan for a bit that this contributed to.
88   for (; bit >= 0; ) {
89     if (getVariableBit(VarName, BI, bit) != -1)
90       break;
91 
92     --bit;
93   }
94 
95   // If we found no bits, ignore this value, otherwise emit the call to get the
96   // operand encoding.
97   if (bit < 0) return;
98 
99   // If the operand matches by name, reference according to that
100   // operand number. Non-matching operands are assumed to be in
101   // order.
102   unsigned OpIdx;
103   if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) {
104     // Get the machine operand number for the indicated operand.
105     OpIdx = CGI.Operands[OpIdx].MIOperandNo;
106     assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) &&
107            "Explicitly used operand also marked as not emitted!");
108   } else {
109     /// If this operand is not supposed to be emitted by the
110     /// generated emitter, skip it.
111     while (CGI.Operands.isFlatOperandNotEmitted(NumberedOp))
112       ++NumberedOp;
113     OpIdx = NumberedOp++;
114   }
115 
116   std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx);
117   std::string &EncoderMethodName = CGI.Operands[SO.first].EncoderMethodName;
118 
119   // If the source operand has a custom encoder, use it. This will
120   // get the encoding for all of the suboperands.
121   if (!EncoderMethodName.empty()) {
122     // A custom encoder has all of the information for the
123     // sub-operands, if there are more than one, so only
124     // query the encoder once per source operand.
125     if (SO.second == 0) {
126       Case += "      // op: " + VarName + "\n" +
127               "      op = " + EncoderMethodName + "(MI, " + utostr(OpIdx);
128       if (MCEmitter)
129         Case += ", Fixups";
130       Case += ");\n";
131     }
132   } else {
133     Case += "      // op: " + VarName + "\n" +
134       "      op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")";
135     if (MCEmitter)
136       Case += ", Fixups";
137     Case += ");\n";
138   }
139 
140   for (; bit >= 0; ) {
141     int varBit = getVariableBit(VarName, BI, bit);
142 
143     // If this bit isn't from a variable, skip it.
144     if (varBit == -1) {
145       --bit;
146       continue;
147     }
148 
149     // Figure out the consecutive range of bits covered by this operand, in
150     // order to generate better encoding code.
151     int beginInstBit = bit;
152     int beginVarBit = varBit;
153     int N = 1;
154     for (--bit; bit >= 0;) {
155       varBit = getVariableBit(VarName, BI, bit);
156       if (varBit == -1 || varBit != (beginVarBit - N)) break;
157       ++N;
158       --bit;
159     }
160 
161     unsigned opMask = ~0U >> (32-N);
162     int opShift = beginVarBit - N + 1;
163     opMask <<= opShift;
164     opShift = beginInstBit - beginVarBit;
165 
166     if (opShift > 0) {
167       Case += "      Value |= (op & " + utostr(opMask) + "U) << " +
168               itostr(opShift) + ";\n";
169     } else if (opShift < 0) {
170       Case += "      Value |= (op & " + utostr(opMask) + "U) >> " +
171               itostr(-opShift) + ";\n";
172     } else {
173       Case += "      Value |= op & " + utostr(opMask) + "U;\n";
174     }
175   }
176 }
177 
178 
179 std::string CodeEmitterGen::getInstructionCase(Record *R,
180                                                CodeGenTarget &Target) {
181   std::string Case;
182 
183   BitsInit *BI = R->getValueAsBitsInit("Inst");
184   const std::vector<RecordVal> &Vals = R->getValues();
185   unsigned NumberedOp = 0;
186 
187   // Loop over all of the fields in the instruction, determining which are the
188   // operands to the instruction.
189   for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
190     // Ignore fixed fields in the record, we're looking for values like:
191     //    bits<5> RST = { ?, ?, ?, ?, ? };
192     if (Vals[i].getPrefix() || Vals[i].getValue()->isComplete())
193       continue;
194 
195     AddCodeToMergeInOperand(R, BI, Vals[i].getName(), NumberedOp, Case, Target);
196   }
197 
198   std::string PostEmitter = R->getValueAsString("PostEncoderMethod");
199   if (!PostEmitter.empty())
200     Case += "      Value = " + PostEmitter + "(MI, Value);\n";
201 
202   return Case;
203 }
204 
205 void CodeEmitterGen::run(raw_ostream &o) {
206   CodeGenTarget Target(Records);
207   std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
208 
209   // For little-endian instruction bit encodings, reverse the bit order
210   if (Target.isLittleEndianEncoding()) reverseBits(Insts);
211 
212   EmitSourceFileHeader("Machine Code Emitter", o);
213 
214   const std::vector<const CodeGenInstruction*> &NumberedInstructions =
215     Target.getInstructionsByEnumValue();
216 
217   // Emit function declaration
218   o << "unsigned " << Target.getName();
219   if (MCEmitter)
220     o << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n"
221       << "    SmallVectorImpl<MCFixup> &Fixups) const {\n";
222   else
223     o << "CodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) const {\n";
224 
225   // Emit instruction base values
226   o << "  static const unsigned InstBits[] = {\n";
227   for (std::vector<const CodeGenInstruction*>::const_iterator
228           IN = NumberedInstructions.begin(),
229           EN = NumberedInstructions.end();
230        IN != EN; ++IN) {
231     const CodeGenInstruction *CGI = *IN;
232     Record *R = CGI->TheDef;
233 
234     if (R->getValueAsString("Namespace") == "TargetOpcode") {
235       o << "    0U,\n";
236       continue;
237     }
238 
239     BitsInit *BI = R->getValueAsBitsInit("Inst");
240 
241     // Start by filling in fixed values.
242     unsigned Value = 0;
243     for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) {
244       if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(e-i-1)))
245         Value |= B->getValue() << (e-i-1);
246     }
247     o << "    " << Value << "U," << '\t' << "// " << R->getName() << "\n";
248   }
249   o << "    0U\n  };\n";
250 
251   // Map to accumulate all the cases.
252   std::map<std::string, std::vector<std::string> > CaseMap;
253 
254   // Construct all cases statement for each opcode
255   for (std::vector<Record*>::iterator IC = Insts.begin(), EC = Insts.end();
256         IC != EC; ++IC) {
257     Record *R = *IC;
258     if (R->getValueAsString("Namespace") == "TargetOpcode")
259       continue;
260     const std::string &InstName = R->getValueAsString("Namespace") + "::"
261       + R->getName();
262     std::string Case = getInstructionCase(R, Target);
263 
264     CaseMap[Case].push_back(InstName);
265   }
266 
267   // Emit initial function code
268   o << "  const unsigned opcode = MI.getOpcode();\n"
269     << "  unsigned Value = InstBits[opcode];\n"
270     << "  unsigned op = 0;\n"
271     << "  (void)op;  // suppress warning\n"
272     << "  switch (opcode) {\n";
273 
274   // Emit each case statement
275   std::map<std::string, std::vector<std::string> >::iterator IE, EE;
276   for (IE = CaseMap.begin(), EE = CaseMap.end(); IE != EE; ++IE) {
277     const std::string &Case = IE->first;
278     std::vector<std::string> &InstList = IE->second;
279 
280     for (int i = 0, N = InstList.size(); i < N; i++) {
281       if (i) o << "\n";
282       o << "    case " << InstList[i]  << ":";
283     }
284     o << " {\n";
285     o << Case;
286     o << "      break;\n"
287       << "    }\n";
288   }
289 
290   // Default case: unhandled opcode
291   o << "  default:\n"
292     << "    std::string msg;\n"
293     << "    raw_string_ostream Msg(msg);\n"
294     << "    Msg << \"Not supported instr: \" << MI;\n"
295     << "    report_fatal_error(Msg.str());\n"
296     << "  }\n"
297     << "  return Value;\n"
298     << "}\n\n";
299 }
300