1 //===- CodeEmitterGen.cpp - Code Emitter Generator ------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // CodeEmitterGen uses the descriptions of instructions and their fields to
11 // construct an automated code emitter: a function that, given a MachineInstr,
12 // returns the (currently, 32-bit unsigned) value of the instruction.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "CodeEmitterGen.h"
17 #include "CodeGenTarget.h"
18 #include "Record.h"
19 #include "llvm/ADT/StringExtras.h"
20 #include "llvm/Support/Debug.h"
21 using namespace llvm;
22 
23 void CodeEmitterGen::reverseBits(std::vector<Record*> &Insts) {
24   for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
25        I != E; ++I) {
26     Record *R = *I;
27     if (R->getName() == "PHI" ||
28         R->getName() == "INLINEASM" ||
29         R->getName() == "DBG_LABEL" ||
30         R->getName() == "EH_LABEL" ||
31         R->getName() == "GC_LABEL" ||
32         R->getName() == "KILL" ||
33         R->getName() == "EXTRACT_SUBREG" ||
34         R->getName() == "INSERT_SUBREG" ||
35         R->getName() == "IMPLICIT_DEF" ||
36         R->getName() == "SUBREG_TO_REG" ||
37         R->getName() == "COPY_TO_REGCLASS") continue;
38 
39     BitsInit *BI = R->getValueAsBitsInit("Inst");
40 
41     unsigned numBits = BI->getNumBits();
42     BitsInit *NewBI = new BitsInit(numBits);
43     for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) {
44       unsigned bitSwapIdx = numBits - bit - 1;
45       Init *OrigBit = BI->getBit(bit);
46       Init *BitSwap = BI->getBit(bitSwapIdx);
47       NewBI->setBit(bit, BitSwap);
48       NewBI->setBit(bitSwapIdx, OrigBit);
49     }
50     if (numBits % 2) {
51       unsigned middle = (numBits + 1) / 2;
52       NewBI->setBit(middle, BI->getBit(middle));
53     }
54 
55     // Update the bits in reversed order so that emitInstrOpBits will get the
56     // correct endianness.
57     R->getValue("Inst")->setValue(NewBI);
58   }
59 }
60 
61 
62 // If the VarBitInit at position 'bit' matches the specified variable then
63 // return the variable bit position.  Otherwise return -1.
64 int CodeEmitterGen::getVariableBit(const Init *VarVal,
65             BitsInit *BI, int bit) {
66   if (VarBitInit *VBI = dynamic_cast<VarBitInit*>(BI->getBit(bit))) {
67     TypedInit *TI = VBI->getVariable();
68     if (TI == VarVal) return VBI->getBitNum();
69   }
70 
71   return -1;
72 }
73 
74 
75 void CodeEmitterGen::run(raw_ostream &o) {
76   CodeGenTarget Target;
77   std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
78 
79   // For little-endian instruction bit encodings, reverse the bit order
80   if (Target.isLittleEndianEncoding()) reverseBits(Insts);
81 
82   EmitSourceFileHeader("Machine Code Emitter", o);
83   std::string Namespace = Insts[0]->getValueAsString("Namespace") + "::";
84 
85   std::vector<const CodeGenInstruction*> NumberedInstructions;
86   Target.getInstructionsByEnumValue(NumberedInstructions);
87 
88   // Emit function declaration
89   o << "unsigned " << Target.getName() << "CodeEmitter::"
90     << "getBinaryCodeForInstr(const MachineInstr &MI) {\n";
91 
92   // Emit instruction base values
93   o << "  static const unsigned InstBits[] = {\n";
94   for (std::vector<const CodeGenInstruction*>::iterator
95           IN = NumberedInstructions.begin(),
96           EN = NumberedInstructions.end();
97        IN != EN; ++IN) {
98     const CodeGenInstruction *CGI = *IN;
99     Record *R = CGI->TheDef;
100 
101     if (R->getName() == "PHI" ||
102         R->getName() == "INLINEASM" ||
103         R->getName() == "DBG_LABEL" ||
104         R->getName() == "EH_LABEL" ||
105         R->getName() == "GC_LABEL" ||
106         R->getName() == "KILL" ||
107         R->getName() == "EXTRACT_SUBREG" ||
108         R->getName() == "INSERT_SUBREG" ||
109         R->getName() == "IMPLICIT_DEF" ||
110         R->getName() == "SUBREG_TO_REG" ||
111         R->getName() == "COPY_TO_REGCLASS") {
112       o << "    0U,\n";
113       continue;
114     }
115 
116     BitsInit *BI = R->getValueAsBitsInit("Inst");
117 
118     // Start by filling in fixed values...
119     unsigned Value = 0;
120     for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) {
121       if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(e-i-1))) {
122         Value |= B->getValue() << (e-i-1);
123       }
124     }
125     o << "    " << Value << "U," << '\t' << "// " << R->getName() << "\n";
126   }
127   o << "    0U\n  };\n";
128 
129   // Map to accumulate all the cases.
130   std::map<std::string, std::vector<std::string> > CaseMap;
131 
132   // Construct all cases statement for each opcode
133   for (std::vector<Record*>::iterator IC = Insts.begin(), EC = Insts.end();
134         IC != EC; ++IC) {
135     Record *R = *IC;
136     const std::string &InstName = R->getName();
137     std::string Case("");
138 
139     if (InstName == "PHI" ||
140         InstName == "INLINEASM" ||
141         InstName == "DBG_LABEL"||
142         InstName == "EH_LABEL"||
143         InstName == "GC_LABEL"||
144         InstName == "KILL"||
145         InstName == "EXTRACT_SUBREG" ||
146         InstName == "INSERT_SUBREG" ||
147         InstName == "IMPLICIT_DEF" ||
148         InstName == "SUBREG_TO_REG" ||
149         InstName == "COPY_TO_REGCLASS") continue;
150 
151     BitsInit *BI = R->getValueAsBitsInit("Inst");
152     const std::vector<RecordVal> &Vals = R->getValues();
153     CodeGenInstruction &CGI = Target.getInstruction(InstName);
154 
155     // Loop over all of the fields in the instruction, determining which are the
156     // operands to the instruction.
157     unsigned op = 0;
158     for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
159       if (!Vals[i].getPrefix() && !Vals[i].getValue()->isComplete()) {
160         // Is the operand continuous? If so, we can just mask and OR it in
161         // instead of doing it bit-by-bit, saving a lot in runtime cost.
162         const Init *VarVal = Vals[i].getValue();
163         bool gotOp = false;
164 
165         for (int bit = BI->getNumBits()-1; bit >= 0; ) {
166           int varBit = getVariableBit(VarVal, BI, bit);
167 
168           if (varBit == -1) {
169             --bit;
170           } else {
171             int beginInstBit = bit;
172             int beginVarBit = varBit;
173             int N = 1;
174 
175             for (--bit; bit >= 0;) {
176               varBit = getVariableBit(VarVal, BI, bit);
177               if (varBit == -1 || varBit != (beginVarBit - N)) break;
178               ++N;
179               --bit;
180             }
181 
182             if (!gotOp) {
183               /// If this operand is not supposed to be emitted by the generated
184               /// emitter, skip it.
185               while (CGI.isFlatOperandNotEmitted(op))
186                 ++op;
187 
188               Case += "      // op: " + Vals[i].getName() + "\n"
189                    +  "      op = getMachineOpValue(MI, MI.getOperand("
190                    +  utostr(op++) + "));\n";
191               gotOp = true;
192             }
193 
194             unsigned opMask = ~0U >> (32-N);
195             int opShift = beginVarBit - N + 1;
196             opMask <<= opShift;
197             opShift = beginInstBit - beginVarBit;
198 
199             if (opShift > 0) {
200               Case += "      Value |= (op & " + utostr(opMask) + "U) << "
201                    +  itostr(opShift) + ";\n";
202             } else if (opShift < 0) {
203               Case += "      Value |= (op & " + utostr(opMask) + "U) >> "
204                    +  itostr(-opShift) + ";\n";
205             } else {
206               Case += "      Value |= op & " + utostr(opMask) + "U;\n";
207             }
208           }
209         }
210       }
211     }
212 
213     std::vector<std::string> &InstList = CaseMap[Case];
214     InstList.push_back(InstName);
215   }
216 
217 
218   // Emit initial function code
219   o << "  const unsigned opcode = MI.getOpcode();\n"
220     << "  unsigned Value = InstBits[opcode];\n"
221     << "  unsigned op = 0;\n"
222     << "  op = op;  // suppress warning\n"
223     << "  switch (opcode) {\n";
224 
225   // Emit each case statement
226   std::map<std::string, std::vector<std::string> >::iterator IE, EE;
227   for (IE = CaseMap.begin(), EE = CaseMap.end(); IE != EE; ++IE) {
228     const std::string &Case = IE->first;
229     std::vector<std::string> &InstList = IE->second;
230 
231     for (int i = 0, N = InstList.size(); i < N; i++) {
232       if (i) o << "\n";
233       o << "    case " << Namespace << InstList[i]  << ":";
234     }
235     o << " {\n";
236     o << Case;
237     o << "      break;\n"
238       << "    }\n";
239   }
240 
241   // Default case: unhandled opcode
242   o << "  default:\n"
243     << "    std::string msg;\n"
244     << "    raw_string_ostream Msg(msg);\n"
245     << "    Msg << \"Not supported instr: \" << MI;\n"
246     << "    llvm_report_error(Msg.str());\n"
247     << "  }\n"
248     << "  return Value;\n"
249     << "}\n\n";
250 }
251