1 #include "ARMBaseInstrInfo.h"
2 #include "ARMSubtarget.h"
3 #include "ARMTargetMachine.h"
4 #include "llvm/Support/TargetRegistry.h"
5 #include "llvm/Support/TargetSelect.h"
6 #include "llvm/Target/TargetMachine.h"
7 #include "llvm/Target/TargetOptions.h"
8 
9 #include "gtest/gtest.h"
10 
11 using namespace llvm;
12 
13 // Test for instructions that aren't immediately obviously valid within a
14 // tail-predicated loop. This should be marked up in their tablegen
15 // descriptions. Currently we, conservatively, disallow:
16 // - cross beat carries.
17 // - narrowing of results.
18 // - complex operations.
19 // - horizontal operations.
20 // - byte swapping.
21 // - interleaved memory instructions.
22 // TODO: Add to this list once we can handle them safely.
23 TEST(MachineInstrValidTailPredication, IsCorrect) {
24 
25   using namespace ARM;
26 
27   auto IsValidTPOpcode = [](unsigned Opcode) {
28     switch (Opcode) {
29     default:
30       return false;
31     case MVE_ASRLi:
32     case MVE_ASRLr:
33     case MVE_LSRL:
34     case MVE_SQRSHR:
35     case MVE_SQSHL:
36     case MVE_SRSHR:
37     case MVE_UQRSHL:
38     case MVE_UQSHL:
39     case MVE_URSHR:
40     case MVE_VABDf16:
41     case MVE_VABDf32:
42     case MVE_VABDs16:
43     case MVE_VABDs32:
44     case MVE_VABDs8:
45     case MVE_VABDu16:
46     case MVE_VABDu32:
47     case MVE_VABDu8:
48     case MVE_VABSf16:
49     case MVE_VABSf32:
50     case MVE_VABSs16:
51     case MVE_VABSs32:
52     case MVE_VABSs8:
53     case MVE_VADD_qr_f16:
54     case MVE_VADD_qr_f32:
55     case MVE_VADD_qr_i16:
56     case MVE_VADD_qr_i32:
57     case MVE_VADD_qr_i8:
58     case MVE_VADDf16:
59     case MVE_VADDf32:
60     case MVE_VADDi16:
61     case MVE_VADDi32:
62     case MVE_VADDi8:
63     case MVE_VAND:
64     case MVE_VBIC:
65     case MVE_VBICIZ0v4i32:
66     case MVE_VBICIZ0v8i16:
67     case MVE_VBICIZ16v4i32:
68     case MVE_VBICIZ24v4i32:
69     case MVE_VBICIZ8v4i32:
70     case MVE_VBICIZ8v8i16:
71     case MVE_VBRSR16:
72     case MVE_VBRSR32:
73     case MVE_VBRSR8:
74     case MVE_VCLSs16:
75     case MVE_VCLSs32:
76     case MVE_VCLSs8:
77     case MVE_VCLZs16:
78     case MVE_VCLZs32:
79     case MVE_VCLZs8:
80     case MVE_VCMPf16:
81     case MVE_VCMPf16r:
82     case MVE_VCMPf32:
83     case MVE_VCMPf32r:
84     case MVE_VCMPi16:
85     case MVE_VCMPi16r:
86     case MVE_VCMPi32:
87     case MVE_VCMPi32r:
88     case MVE_VCMPi8:
89     case MVE_VCMPi8r:
90     case MVE_VCMPs16:
91     case MVE_VCMPs16r:
92     case MVE_VCMPs32:
93     case MVE_VCMPs32r:
94     case MVE_VCMPs8:
95     case MVE_VCMPs8r:
96     case MVE_VCMPu16:
97     case MVE_VCMPu16r:
98     case MVE_VCMPu32:
99     case MVE_VCMPu32r:
100     case MVE_VCMPu8:
101     case MVE_VCMPu8r:
102     case MVE_VCTP16:
103     case MVE_VCTP32:
104     case MVE_VCTP64:
105     case MVE_VCTP8:
106     case MVE_VCVTf16s16_fix:
107     case MVE_VCVTf16s16n:
108     case MVE_VCVTf16u16_fix:
109     case MVE_VCVTf16u16n:
110     case MVE_VCVTf32s32_fix:
111     case MVE_VCVTf32s32n:
112     case MVE_VCVTf32u32_fix:
113     case MVE_VCVTf32u32n:
114     case MVE_VCVTs16f16_fix:
115     case MVE_VCVTs16f16a:
116     case MVE_VCVTs16f16m:
117     case MVE_VCVTs16f16n:
118     case MVE_VCVTs16f16p:
119     case MVE_VCVTs16f16z:
120     case MVE_VCVTs32f32_fix:
121     case MVE_VCVTs32f32a:
122     case MVE_VCVTs32f32m:
123     case MVE_VCVTs32f32n:
124     case MVE_VCVTs32f32p:
125     case MVE_VCVTs32f32z:
126     case MVE_VCVTu16f16_fix:
127     case MVE_VCVTu16f16a:
128     case MVE_VCVTu16f16m:
129     case MVE_VCVTu16f16n:
130     case MVE_VCVTu16f16p:
131     case MVE_VCVTu16f16z:
132     case MVE_VCVTu32f32_fix:
133     case MVE_VCVTu32f32a:
134     case MVE_VCVTu32f32m:
135     case MVE_VCVTu32f32n:
136     case MVE_VCVTu32f32p:
137     case MVE_VCVTu32f32z:
138     case MVE_VDDUPu16:
139     case MVE_VDDUPu32:
140     case MVE_VDDUPu8:
141     case MVE_VDUP16:
142     case MVE_VDUP32:
143     case MVE_VDUP8:
144     case MVE_VDWDUPu16:
145     case MVE_VDWDUPu32:
146     case MVE_VDWDUPu8:
147     case MVE_VEOR:
148     case MVE_VFMA_qr_Sf16:
149     case MVE_VFMA_qr_Sf32:
150     case MVE_VFMA_qr_f16:
151     case MVE_VFMA_qr_f32:
152     case MVE_VMLAS_qr_s16:
153     case MVE_VMLAS_qr_s32:
154     case MVE_VMLAS_qr_s8:
155     case MVE_VMLAS_qr_u16:
156     case MVE_VMLAS_qr_u32:
157     case MVE_VMLAS_qr_u8:
158     case MVE_VMLA_qr_s16:
159     case MVE_VMLA_qr_s32:
160     case MVE_VMLA_qr_s8:
161     case MVE_VMLA_qr_u16:
162     case MVE_VMLA_qr_u32:
163     case MVE_VMLA_qr_u8:
164     case MVE_VHADD_qr_s16:
165     case MVE_VHADD_qr_s32:
166     case MVE_VHADD_qr_s8:
167     case MVE_VHADD_qr_u16:
168     case MVE_VHADD_qr_u32:
169     case MVE_VHADD_qr_u8:
170     case MVE_VHADDs16:
171     case MVE_VHADDs32:
172     case MVE_VHADDs8:
173     case MVE_VHADDu16:
174     case MVE_VHADDu32:
175     case MVE_VHADDu8:
176     case MVE_VHSUB_qr_s16:
177     case MVE_VHSUB_qr_s32:
178     case MVE_VHSUB_qr_s8:
179     case MVE_VHSUB_qr_u16:
180     case MVE_VHSUB_qr_u32:
181     case MVE_VHSUB_qr_u8:
182     case MVE_VHSUBs16:
183     case MVE_VHSUBs32:
184     case MVE_VHSUBs8:
185     case MVE_VHSUBu16:
186     case MVE_VHSUBu32:
187     case MVE_VHSUBu8:
188     case MVE_VIDUPu16:
189     case MVE_VIDUPu32:
190     case MVE_VIDUPu8:
191     case MVE_VIWDUPu16:
192     case MVE_VIWDUPu32:
193     case MVE_VIWDUPu8:
194     case MVE_VLDRBS16:
195     case MVE_VLDRBS16_post:
196     case MVE_VLDRBS16_pre:
197     case MVE_VLDRBS16_rq:
198     case MVE_VLDRBS32:
199     case MVE_VLDRBS32_post:
200     case MVE_VLDRBS32_pre:
201     case MVE_VLDRBS32_rq:
202     case MVE_VLDRBU16:
203     case MVE_VLDRBU16_post:
204     case MVE_VLDRBU16_pre:
205     case MVE_VLDRBU16_rq:
206     case MVE_VLDRBU32:
207     case MVE_VLDRBU32_post:
208     case MVE_VLDRBU32_pre:
209     case MVE_VLDRBU32_rq:
210     case MVE_VLDRBU8:
211     case MVE_VLDRBU8_post:
212     case MVE_VLDRBU8_pre:
213     case MVE_VLDRBU8_rq:
214     case MVE_VLDRDU64_qi:
215     case MVE_VLDRDU64_qi_pre:
216     case MVE_VLDRDU64_rq:
217     case MVE_VLDRDU64_rq_u:
218     case MVE_VLDRHS32:
219     case MVE_VLDRHS32_post:
220     case MVE_VLDRHS32_pre:
221     case MVE_VLDRHS32_rq:
222     case MVE_VLDRHS32_rq_u:
223     case MVE_VLDRHU16:
224     case MVE_VLDRHU16_post:
225     case MVE_VLDRHU16_pre:
226     case MVE_VLDRHU16_rq:
227     case MVE_VLDRHU16_rq_u:
228     case MVE_VLDRHU32:
229     case MVE_VLDRHU32_post:
230     case MVE_VLDRHU32_pre:
231     case MVE_VLDRHU32_rq:
232     case MVE_VLDRHU32_rq_u:
233     case MVE_VLDRWU32:
234     case MVE_VLDRWU32_post:
235     case MVE_VLDRWU32_pre:
236     case MVE_VLDRWU32_qi:
237     case MVE_VLDRWU32_qi_pre:
238     case MVE_VLDRWU32_rq:
239     case MVE_VLDRWU32_rq_u:
240     case MVE_VMOVimmf32:
241     case MVE_VMOVimmi16:
242     case MVE_VMOVimmi32:
243     case MVE_VMOVimmi64:
244     case MVE_VMOVimmi8:
245     case MVE_VMULLBp16:
246     case MVE_VMULLBp8:
247     case MVE_VMULLBs16:
248     case MVE_VMULLBs32:
249     case MVE_VMULLBs8:
250     case MVE_VMULLBu16:
251     case MVE_VMULLBu32:
252     case MVE_VMULLBu8:
253     case MVE_VMULLTp16:
254     case MVE_VMULLTp8:
255     case MVE_VMULLTs16:
256     case MVE_VMULLTs32:
257     case MVE_VMULLTs8:
258     case MVE_VMULLTu16:
259     case MVE_VMULLTu32:
260     case MVE_VMULLTu8:
261     case MVE_VMUL_qr_f16:
262     case MVE_VMUL_qr_f32:
263     case MVE_VMUL_qr_i16:
264     case MVE_VMUL_qr_i32:
265     case MVE_VMUL_qr_i8:
266     case MVE_VMULf16:
267     case MVE_VMULf32:
268     case MVE_VMULi16:
269     case MVE_VMULi8:
270     case MVE_VMULi32:
271     case MVE_VMVN:
272     case MVE_VMVNimmi16:
273     case MVE_VMVNimmi32:
274     case MVE_VNEGf16:
275     case MVE_VNEGf32:
276     case MVE_VNEGs16:
277     case MVE_VNEGs32:
278     case MVE_VNEGs8:
279     case MVE_VORN:
280     case MVE_VORR:
281     case MVE_VORRIZ0v4i32:
282     case MVE_VORRIZ0v8i16:
283     case MVE_VORRIZ16v4i32:
284     case MVE_VORRIZ24v4i32:
285     case MVE_VORRIZ8v4i32:
286     case MVE_VORRIZ8v8i16:
287     case MVE_VPNOT:
288     case MVE_VPSEL:
289     case MVE_VPST:
290     case MVE_VQABSs16:
291     case MVE_VQABSs32:
292     case MVE_VQABSs8:
293     case MVE_VQADD_qr_s16:
294     case MVE_VQADD_qr_s32:
295     case MVE_VQADD_qr_s8:
296     case MVE_VQADD_qr_u16:
297     case MVE_VQADD_qr_u32:
298     case MVE_VQADD_qr_u8:
299     case MVE_VQADDs16:
300     case MVE_VQADDs32:
301     case MVE_VQADDs8:
302     case MVE_VQADDu16:
303     case MVE_VQADDu32:
304     case MVE_VQADDu8:
305     case MVE_VQDMULL_qr_s16bh:
306     case MVE_VQDMULL_qr_s16th:
307     case MVE_VQDMULL_qr_s32bh:
308     case MVE_VQDMULL_qr_s32th:
309     case MVE_VQDMULLs16bh:
310     case MVE_VQDMULLs16th:
311     case MVE_VQDMULLs32bh:
312     case MVE_VQDMULLs32th:
313     case MVE_VQNEGs16:
314     case MVE_VQNEGs32:
315     case MVE_VQNEGs8:
316     case MVE_VQRSHL_by_vecs16:
317     case MVE_VQRSHL_by_vecs32:
318     case MVE_VQRSHL_by_vecs8:
319     case MVE_VQRSHL_by_vecu16:
320     case MVE_VQRSHL_by_vecu32:
321     case MVE_VQRSHL_by_vecu8:
322     case MVE_VQRSHL_qrs16:
323     case MVE_VQRSHL_qrs32:
324     case MVE_VQRSHL_qrs8:
325     case MVE_VQRSHL_qru16:
326     case MVE_VQRSHL_qru8:
327     case MVE_VQRSHL_qru32:
328     case MVE_VQSHLU_imms16:
329     case MVE_VQSHLU_imms32:
330     case MVE_VQSHLU_imms8:
331     case MVE_VQSHLimms16:
332     case MVE_VQSHLimms32:
333     case MVE_VQSHLimms8:
334     case MVE_VQSHLimmu16:
335     case MVE_VQSHLimmu32:
336     case MVE_VQSHLimmu8:
337     case MVE_VQSHL_by_vecs16:
338     case MVE_VQSHL_by_vecs32:
339     case MVE_VQSHL_by_vecs8:
340     case MVE_VQSHL_by_vecu16:
341     case MVE_VQSHL_by_vecu32:
342     case MVE_VQSHL_by_vecu8:
343     case MVE_VQSHL_qrs16:
344     case MVE_VQSHL_qrs32:
345     case MVE_VQSHL_qrs8:
346     case MVE_VQSHL_qru16:
347     case MVE_VQSHL_qru32:
348     case MVE_VQSHL_qru8:
349     case MVE_VQSUB_qr_s16:
350     case MVE_VQSUB_qr_s32:
351     case MVE_VQSUB_qr_s8:
352     case MVE_VQSUB_qr_u16:
353     case MVE_VQSUB_qr_u32:
354     case MVE_VQSUB_qr_u8:
355     case MVE_VQSUBs16:
356     case MVE_VQSUBs32:
357     case MVE_VQSUBs8:
358     case MVE_VQSUBu16:
359     case MVE_VQSUBu32:
360     case MVE_VQSUBu8:
361     case MVE_VRHADDs16:
362     case MVE_VRHADDs32:
363     case MVE_VRHADDs8:
364     case MVE_VRHADDu16:
365     case MVE_VRHADDu32:
366     case MVE_VRHADDu8:
367     case MVE_VRINTf16A:
368     case MVE_VRINTf16M:
369     case MVE_VRINTf16N:
370     case MVE_VRINTf16P:
371     case MVE_VRINTf16X:
372     case MVE_VRINTf16Z:
373     case MVE_VRINTf32A:
374     case MVE_VRINTf32M:
375     case MVE_VRINTf32N:
376     case MVE_VRINTf32P:
377     case MVE_VRINTf32X:
378     case MVE_VRINTf32Z:
379     case MVE_VRSHL_by_vecs16:
380     case MVE_VRSHL_by_vecs32:
381     case MVE_VRSHL_by_vecs8:
382     case MVE_VRSHL_by_vecu16:
383     case MVE_VRSHL_by_vecu32:
384     case MVE_VRSHL_by_vecu8:
385     case MVE_VRSHL_qrs16:
386     case MVE_VRSHL_qrs32:
387     case MVE_VRSHL_qrs8:
388     case MVE_VRSHL_qru16:
389     case MVE_VRSHL_qru32:
390     case MVE_VRSHL_qru8:
391     case MVE_VRSHR_imms16:
392     case MVE_VRSHR_imms32:
393     case MVE_VRSHR_imms8:
394     case MVE_VRSHR_immu16:
395     case MVE_VRSHR_immu32:
396     case MVE_VRSHR_immu8:
397     case MVE_VSHL_by_vecs16:
398     case MVE_VSHL_by_vecs32:
399     case MVE_VSHL_by_vecs8:
400     case MVE_VSHL_by_vecu16:
401     case MVE_VSHL_by_vecu32:
402     case MVE_VSHL_by_vecu8:
403     case MVE_VSHL_immi16:
404     case MVE_VSHL_immi32:
405     case MVE_VSHL_immi8:
406     case MVE_VSHL_qrs16:
407     case MVE_VSHL_qrs32:
408     case MVE_VSHL_qrs8:
409     case MVE_VSHL_qru16:
410     case MVE_VSHL_qru32:
411     case MVE_VSHL_qru8:
412     case MVE_VSHR_imms16:
413     case MVE_VSHR_imms32:
414     case MVE_VSHR_imms8:
415     case MVE_VSHR_immu16:
416     case MVE_VSHR_immu32:
417     case MVE_VSHR_immu8:
418     case MVE_VSLIimm16:
419     case MVE_VSLIimm32:
420     case MVE_VSLIimm8:
421     case MVE_VSRIimm16:
422     case MVE_VSRIimm32:
423     case MVE_VSRIimm8:
424     case MVE_VSTRB16:
425     case MVE_VSTRB16_post:
426     case MVE_VSTRB16_pre:
427     case MVE_VSTRB16_rq:
428     case MVE_VSTRB32:
429     case MVE_VSTRB32_post:
430     case MVE_VSTRB32_pre:
431     case MVE_VSTRB32_rq:
432     case MVE_VSTRB8_rq:
433     case MVE_VSTRBU8:
434     case MVE_VSTRBU8_post:
435     case MVE_VSTRBU8_pre:
436     case MVE_VSTRD64_qi:
437     case MVE_VSTRD64_qi_pre:
438     case MVE_VSTRD64_rq:
439     case MVE_VSTRD64_rq_u:
440     case MVE_VSTRH16_rq:
441     case MVE_VSTRH16_rq_u:
442     case MVE_VSTRH32:
443     case MVE_VSTRH32_post:
444     case MVE_VSTRH32_pre:
445     case MVE_VSTRH32_rq:
446     case MVE_VSTRH32_rq_u:
447     case MVE_VSTRHU16:
448     case MVE_VSTRHU16_post:
449     case MVE_VSTRHU16_pre:
450     case MVE_VSTRW32_qi:
451     case MVE_VSTRW32_qi_pre:
452     case MVE_VSTRW32_rq:
453     case MVE_VSTRW32_rq_u:
454     case MVE_VSTRWU32:
455     case MVE_VSTRWU32_post:
456     case MVE_VSTRWU32_pre:
457     case MVE_VSUB_qr_f16:
458     case MVE_VSUB_qr_f32:
459     case MVE_VSUB_qr_i16:
460     case MVE_VSUB_qr_i32:
461     case MVE_VSUB_qr_i8:
462     case MVE_VSUBf16:
463     case MVE_VSUBf32:
464     case MVE_VSUBi16:
465     case MVE_VSUBi32:
466     case MVE_VSUBi8:
467       return true;
468     }
469   };
470 
471   LLVMInitializeARMTargetInfo();
472   LLVMInitializeARMTarget();
473   LLVMInitializeARMTargetMC();
474 
475   auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi"));
476   std::string Error;
477   const Target *T = TargetRegistry::lookupTarget(TT, Error);
478   if (!T) {
479     dbgs() << Error;
480     return;
481   }
482 
483   TargetOptions Options;
484   auto TM = std::unique_ptr<LLVMTargetMachine>(
485     static_cast<LLVMTargetMachine*>(
486       T->createTargetMachine(TT, "generic", "", Options, None, None,
487                              CodeGenOpt::Default)));
488   ARMSubtarget ST(TM->getTargetTriple(), TM->getTargetCPU(),
489                   TM->getTargetFeatureString(),
490                   *static_cast<const ARMBaseTargetMachine*>(TM.get()), false);
491   const ARMBaseInstrInfo *TII = ST.getInstrInfo();
492   auto MII = TM->getMCInstrInfo();
493 
494   for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {
495     const MCInstrDesc &Desc = TII->get(i);
496 
497     for (auto &Op : Desc.operands()) {
498       // Only check instructions that access the MQPR regs.
499       if ((Op.OperandType & MCOI::OPERAND_REGISTER) == 0 ||
500           Op.RegClass != ARM::MQPRRegClassID)
501         continue;
502 
503       uint64_t Flags = MII->get(i).TSFlags;
504       bool Valid = (Flags & ARMII::ValidForTailPredication) != 0;
505       ASSERT_EQ(IsValidTPOpcode(i), Valid)
506                 << MII->getName(i)
507                 << ": mismatched expectation for tail-predicated safety\n";
508       break;
509     }
510   }
511 }
512